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JPS558628A - Data processing system - Google Patents

Data processing system

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Publication number
JPS558628A
JPS558628AJP7956978AJP7956978AJPS558628AJP S558628 AJPS558628 AJP S558628AJP 7956978 AJP7956978 AJP 7956978AJP 7956978 AJP7956978 AJP 7956978AJP S558628 AJPS558628 AJP S558628A
Authority
JP
Japan
Prior art keywords
address information
buffer
access address
basis
plural
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7956978A
Other languages
Japanese (ja)
Inventor
Koichi Inoue
Shinichi Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu LtdfiledCriticalFujitsu Ltd
Priority to JP7956978ApriorityCriticalpatent/JPS558628A/en
Publication of JPS558628ApublicationCriticalpatent/JPS558628A/en
Pendinglegal-statusCriticalCurrent

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Abstract

PURPOSE: To simplify the access circuit constitution for a buffer memory to cope with storage capacity increment by selecting one of plural buffer memories on a basis of information which segments the storage space in access address information.
CONSTITUTION: Storage space 1 is segmented into plural storage spaces 2-0 to 2-3, and buffer memories 3-0 to 3-3 are provided correspondingly, and each buffer memory is cinstituted by buffer index part 4 and data part 5. TLB stores the correspondence table between logical addresses and actual addresses to index TLB 7 on a basis of given access address information and extracts corresponding actual page addresses and accesses each buffer memory by the address in the page in access address information and selects one of plural buffer memories 3 on a basis of information which segments storage space 1 in access address information.
COPYRIGHT: (C)1980,JPO&Japio
JP7956978A1978-06-301978-06-30Data processing systemPendingJPS558628A (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP7956978AJPS558628A (en)1978-06-301978-06-30Data processing system

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP7956978AJPS558628A (en)1978-06-301978-06-30Data processing system

Publications (1)

Publication NumberPublication Date
JPS558628Atrue JPS558628A (en)1980-01-22

Family

ID=13693626

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP7956978APendingJPS558628A (en)1978-06-301978-06-30Data processing system

Country Status (1)

CountryLink
JP (1)JPS558628A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS60112153A (en)*1983-11-221985-06-18Hitachi LtdControlling method of cache memory
JPS63208144A (en)*1987-02-251988-08-29Yokogawa Electric Corp cache memory controller
JPH0268640A (en)*1988-09-051990-03-08Pfu LtdCache memory
US6351788B1 (en)1996-10-302002-02-26Hitachi, Ltd.Data processor and data processing system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS60112153A (en)*1983-11-221985-06-18Hitachi LtdControlling method of cache memory
JPS63208144A (en)*1987-02-251988-08-29Yokogawa Electric Corp cache memory controller
JPH0268640A (en)*1988-09-051990-03-08Pfu LtdCache memory
US6351788B1 (en)1996-10-302002-02-26Hitachi, Ltd.Data processor and data processing system

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