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JPS5524482A - Mono-cyrstalline silicon - Google Patents

Mono-cyrstalline silicon

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Publication number
JPS5524482A
JPS5524482AJP9765478AJP9765478AJPS5524482AJP S5524482 AJPS5524482 AJP S5524482AJP 9765478 AJP9765478 AJP 9765478AJP 9765478 AJP9765478 AJP 9765478AJP S5524482 AJPS5524482 AJP S5524482A
Authority
JP
Japan
Prior art keywords
substrate
type
ions
layer
voltage value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9765478A
Other languages
Japanese (ja)
Inventor
Yasuo Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co LtdfiledCriticalNEC Corp
Priority to JP9765478ApriorityCriticalpatent/JPS5524482A/en
Publication of JPS5524482ApublicationCriticalpatent/JPS5524482A/en
Pendinglegal-statusCriticalCurrent

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Abstract

PURPOSE: For increasing withstand voltage value and decreasing current leakage, of a mesa structure, to use as IC substrate the Si layer epitaxially formed on the Si crystal substrate in which C ions are injected.
CONSTITUTION: α-SiC layer is formed on the surface of an N-type Si substrate by injecting the C ions having generated CH4 as source into said N-type Si substrate whose 100 faces are inclined in 50° in 100 directions with accelerating voltage and dose fixed at 150KV and 2×1016/cm2 respectively. Next, said substrate 1 is placed in the gaseous-phase epitaxial system employing SiCl4 and subjected to annealing in 100% H2 atmosphere at 1,150°C for one hour. Thereafter, N-type layer is formed in said system, Al is deposited on the both sides of said substrate 1, and ohmic junction is made by alloying method. Next, an IC element is made by providing mesa on the surface of said sustrate. Thereby, the withstand voltage value between the both sides of said substrate 1 comes above 500V, and leakage current is only 0.01μA or lower at 100V.
COPYRIGHT: (C)1980,JPO&Japio
JP9765478A1978-08-091978-08-09Mono-cyrstalline siliconPendingJPS5524482A (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP9765478AJPS5524482A (en)1978-08-091978-08-09Mono-cyrstalline silicon

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP9765478AJPS5524482A (en)1978-08-091978-08-09Mono-cyrstalline silicon

Publications (1)

Publication NumberPublication Date
JPS5524482Atrue JPS5524482A (en)1980-02-21

Family

ID=14198060

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP9765478APendingJPS5524482A (en)1978-08-091978-08-09Mono-cyrstalline silicon

Country Status (1)

CountryLink
JP (1)JPS5524482A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS56142626A (en)*1980-04-091981-11-07Toshiba CorpManufacture of semiconductor single crystal film
JPS61287115A (en)*1985-06-131986-12-17Hitachi Metals LtdManufacture of anisotropic magnet
US4966860A (en)*1983-12-231990-10-30Sharp Kabushiki KaishaProcess for producing a SiC semiconductor device
JPH07263267A (en)*1994-12-221995-10-13Hitachi Metals LtdManufacture of anisotropic magnet
US6303508B1 (en)1999-12-162001-10-16Philips Electronics North America CorporationSuperior silicon carbide integrated circuits and method of fabricating
US6407014B1 (en)1999-12-162002-06-18Philips Electronics North America CorporationMethod achieving higher inversion layer mobility in novel silicon carbide semiconductor devices
WO2009016794A1 (en)*2007-07-312009-02-05Shin-Etsu Handotai Co., Ltd.Epitaxial wafer manufacturing method and epitaxial wafer
JP2015035467A (en)*2013-08-082015-02-19株式会社Sumco Bonded wafer manufacturing method and bonded wafer

Cited By (9)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS56142626A (en)*1980-04-091981-11-07Toshiba CorpManufacture of semiconductor single crystal film
US4966860A (en)*1983-12-231990-10-30Sharp Kabushiki KaishaProcess for producing a SiC semiconductor device
JPS61287115A (en)*1985-06-131986-12-17Hitachi Metals LtdManufacture of anisotropic magnet
JPH07263267A (en)*1994-12-221995-10-13Hitachi Metals LtdManufacture of anisotropic magnet
US6303508B1 (en)1999-12-162001-10-16Philips Electronics North America CorporationSuperior silicon carbide integrated circuits and method of fabricating
US6407014B1 (en)1999-12-162002-06-18Philips Electronics North America CorporationMethod achieving higher inversion layer mobility in novel silicon carbide semiconductor devices
US6504184B2 (en)1999-12-162003-01-07Koninklijke Philips Electronics N.V.Superior silicon carbide integrated circuits and method of fabricating
WO2009016794A1 (en)*2007-07-312009-02-05Shin-Etsu Handotai Co., Ltd.Epitaxial wafer manufacturing method and epitaxial wafer
JP2015035467A (en)*2013-08-082015-02-19株式会社Sumco Bonded wafer manufacturing method and bonded wafer

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