JPS55157043A - Information processor - Google Patents

Abstract

PURPOSE: To enable to write in the data and check bit being uncorrectable error to memory units after simple production, by compulsively inverting at least 2 bits of check bits.

CONSTITUTION: A memory controller 6 includes a check bit production circuit 11 and inversion elements 12, 13. At least, two bits are inverted (by elements 12, 13) with a parity error signal 15 to a plurality of check bits produced from the circuit 11 from write-in data 14 to form the write-in data being uncorrectable error. Thus, by the write-in data and check bits formed, when the parity error signal is detected in the data from CPU1, the error of two bits or more is formed compulsively as uncorrectable error and this is written in the memory 7. Accordingly, in checking the data read out from the memory 7 and the check bits, if the said uncorrectable error is taken place, it can be detected as two-bit error.

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