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JPS55105332A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55105332A
JPS55105332AJP1294879AJP1294879AJPS55105332AJP S55105332 AJPS55105332 AJP S55105332AJP 1294879 AJP1294879 AJP 1294879AJP 1294879 AJP1294879 AJP 1294879AJP S55105332 AJPS55105332 AJP S55105332A
Authority
JP
Japan
Prior art keywords
layer
film
region
substrate
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1294879A
Other languages
Japanese (ja)
Inventor
Takeo Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co LtdfiledCriticalNEC Corp
Priority to JP1294879ApriorityCriticalpatent/JPS55105332A/en
Publication of JPS55105332ApublicationCriticalpatent/JPS55105332A/en
Pendinglegal-statusCriticalCurrent

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Abstract

PURPOSE: To make the opening area accurate and to obtain high density in forming an opening hole in an Si3N4 layer on a semiconductor layer by introducing P impurities in the layer on which opening hole is formed and making the layer to become PSG, thereafter removing it by using acidic solution.
CONSTITUTION: A thick field oxide film 34 is formed on the peripheral portion of a p-type Si substrate 31 via a p-type channel stopper region 32; a thin gate oxide film 30 is deposited on the substrate 31 surrounded by a film 34; and an n-type polycrystal lene layer 35, an Si3N4 layer 36, and an Si2O3 layer 37 are laminated and grown on the plane including the portions mentioned above. Then, etching is made, layers 47, 46, and 45 are remained only on the gate region, and an n-type source and drain region 43 is diffused and formed in the substrate 41 on both sides of the mask which is the layers 47, 46 and 45. Thereafter, a region 53 is covered by an SiO2 layer 54, a photoresist-pattern 58 is provided, P impurities are diffused, an Si3N4 film 66 is completely made to be PSG, planson washing is performed, the film 66 is removed and only a gate electrode 57 is remained.
COPYRIGHT: (C)1980,JPO&Japio
JP1294879A1979-02-071979-02-07Manufacture of semiconductor devicePendingJPS55105332A (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP1294879AJPS55105332A (en)1979-02-071979-02-07Manufacture of semiconductor device

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP1294879AJPS55105332A (en)1979-02-071979-02-07Manufacture of semiconductor device

Publications (1)

Publication NumberPublication Date
JPS55105332Atrue JPS55105332A (en)1980-08-12

Family

ID=11819495

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP1294879APendingJPS55105332A (en)1979-02-071979-02-07Manufacture of semiconductor device

Country Status (1)

CountryLink
JP (1)JPS55105332A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US4948757A (en)*1987-04-131990-08-14General Motors CorporationMethod for fabricating three-dimensional microstructures and a high-sensitivity integrated vibration sensor using such microstructures
US5780313A (en)*1985-02-141998-07-14Semiconductor Energy Laboratory Co., Ltd.Method of fabricating semiconductor device
US6177302B1 (en)1990-11-092001-01-23Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing a thin film transistor using multiple sputtering chambers

Cited By (8)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5780313A (en)*1985-02-141998-07-14Semiconductor Energy Laboratory Co., Ltd.Method of fabricating semiconductor device
US5976259A (en)*1985-02-141999-11-02Semiconductor Energy Laboratory Co., Ltd.Semiconductor device, manufacturing method, and system
US6113701A (en)*1985-02-142000-09-05Semiconductor Energy Laboratory Co., Ltd.Semiconductor device, manufacturing method, and system
US4948757A (en)*1987-04-131990-08-14General Motors CorporationMethod for fabricating three-dimensional microstructures and a high-sensitivity integrated vibration sensor using such microstructures
US6261877B1 (en)1990-09-112001-07-17Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing gate insulated field effect transistors
US6177302B1 (en)1990-11-092001-01-23Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing a thin film transistor using multiple sputtering chambers
US6566175B2 (en)1990-11-092003-05-20Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing gate insulated field effect transistors
US7507615B2 (en)1990-11-092009-03-24Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing gate insulated field effect transistors

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