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JPS5453929U - - Google Patents

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Publication number
JPS5453929U
JPS5453929UJP12626877UJP12626877UJPS5453929UJP S5453929 UJPS5453929 UJP S5453929UJP 12626877 UJP12626877 UJP 12626877UJP 12626877 UJP12626877 UJP 12626877UJP S5453929 UJPS5453929 UJP S5453929U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12626877U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filedfiledCritical
Priority to JP12626877UpriorityCriticalpatent/JPS5453929U/ja
Publication of JPS5453929UpublicationCriticalpatent/JPS5453929U/ja
Pendinglegal-statusCriticalCurrent

Links

JP12626877U1977-09-211977-09-21PendingJPS5453929U (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP12626877UJPS5453929U (en)1977-09-211977-09-21

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP12626877UJPS5453929U (en)1977-09-211977-09-21

Publications (1)

Publication NumberPublication Date
JPS5453929Utrue JPS5453929U (en)1979-04-14

Family

ID=29087937

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP12626877UPendingJPS5453929U (en)1977-09-211977-09-21

Country Status (1)

CountryLink
JP (1)JPS5453929U (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US7116577B2 (en)1997-08-012006-10-03Saifun Semiconductors LtdTwo bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US7221138B2 (en)2005-09-272007-05-22Saifun Semiconductors LtdMethod and apparatus for measuring charge pump output current
US7317633B2 (en)2004-07-062008-01-08Saifun Semiconductors LtdProtection of NROM devices from charge damage
US7352627B2 (en)2006-01-032008-04-01Saifon Semiconductors Ltd.Method, system, and circuit for operating a non-volatile memory array
US7369440B2 (en)2005-01-192008-05-06Saifun Semiconductors Ltd.Method, circuit and systems for erasing one or more non-volatile memory cells
US7420848B2 (en)2002-01-312008-09-02Saifun Semiconductors Ltd.Method, system, and circuit for operating a non-volatile memory array
US7457183B2 (en)2003-09-162008-11-25Saifun Semiconductors Ltd.Operating array cells with matched reference cells
US7466594B2 (en)2004-08-122008-12-16Saifun Semiconductors Ltd.Dynamic matching of signal path and reference path for sensing
US7512009B2 (en)2001-04-052009-03-31Saifun Semiconductors Ltd.Method for programming a reference cell
US7532529B2 (en)2004-03-292009-05-12Saifun Semiconductors Ltd.Apparatus and methods for multi-level sensing in a memory array
US7605579B2 (en)2006-09-182009-10-20Saifun Semiconductors Ltd.Measuring and controlling current consumption and output current of charge pumps
US7638850B2 (en)2004-10-142009-12-29Saifun Semiconductors Ltd.Non-volatile memory structure and method of fabrication
US7638835B2 (en)2006-02-282009-12-29Saifun Semiconductors Ltd.Double density NROM with nitride strips (DDNS)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US7116577B2 (en)1997-08-012006-10-03Saifun Semiconductors LtdTwo bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US7405969B2 (en)1997-08-012008-07-29Saifun Semiconductors Ltd.Non-volatile memory cell and non-volatile memory devices
US7512009B2 (en)2001-04-052009-03-31Saifun Semiconductors Ltd.Method for programming a reference cell
US7420848B2 (en)2002-01-312008-09-02Saifun Semiconductors Ltd.Method, system, and circuit for operating a non-volatile memory array
US7457183B2 (en)2003-09-162008-11-25Saifun Semiconductors Ltd.Operating array cells with matched reference cells
US7532529B2 (en)2004-03-292009-05-12Saifun Semiconductors Ltd.Apparatus and methods for multi-level sensing in a memory array
US7317633B2 (en)2004-07-062008-01-08Saifun Semiconductors LtdProtection of NROM devices from charge damage
US7466594B2 (en)2004-08-122008-12-16Saifun Semiconductors Ltd.Dynamic matching of signal path and reference path for sensing
US7638850B2 (en)2004-10-142009-12-29Saifun Semiconductors Ltd.Non-volatile memory structure and method of fabrication
US7468926B2 (en)2005-01-192008-12-23Saifun Semiconductors Ltd.Partial erase verify
US7369440B2 (en)2005-01-192008-05-06Saifun Semiconductors Ltd.Method, circuit and systems for erasing one or more non-volatile memory cells
US7221138B2 (en)2005-09-272007-05-22Saifun Semiconductors LtdMethod and apparatus for measuring charge pump output current
US7352627B2 (en)2006-01-032008-04-01Saifon Semiconductors Ltd.Method, system, and circuit for operating a non-volatile memory array
US7638835B2 (en)2006-02-282009-12-29Saifun Semiconductors Ltd.Double density NROM with nitride strips (DDNS)
US7605579B2 (en)2006-09-182009-10-20Saifun Semiconductors Ltd.Measuring and controlling current consumption and output current of charge pumps

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