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JPS54134947A - Multiprocessing control system - Google Patents

Multiprocessing control system

Info

Publication number
JPS54134947A
JPS54134947AJP4297778AJP4297778AJPS54134947AJP S54134947 AJPS54134947 AJP S54134947AJP 4297778 AJP4297778 AJP 4297778AJP 4297778 AJP4297778 AJP 4297778AJP S54134947 AJPS54134947 AJP S54134947A
Authority
JP
Japan
Prior art keywords
processors
address
instruction
common
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4297778A
Other languages
Japanese (ja)
Other versions
JPS5854422B2 (en
Inventor
Shuji Kikuchi
Tadashi Iwase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric CorpfiledCriticalMitsubishi Electric Corp
Priority to JP4297778ApriorityCriticalpatent/JPS5854422B2/en
Publication of JPS54134947ApublicationCriticalpatent/JPS54134947A/en
Publication of JPS5854422B2publicationCriticalpatent/JPS5854422B2/en
Expiredlegal-statusCriticalCurrent

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Abstract

PURPOSE: To make it possible to refer easily to the prefix area characteristic of each processor by holding a program control instruction capable of converting addresses in a data block used by several processors in common.
CONSTITUTION: Processors 1 and 11, equipped with address converting devices 5 and 51, use memory unit 9 in common. In the memory unit, data block 111 used by respective processors in common resides, where an instruction of a machine- language level is held which attains address-convertible program state control as to the operand address of an instruction. To execute the machine language-instruction, processors 1 and 11 convert the operand addresses by the address convertion information which is supplied unconditionally to each processor at the time of system programming, so that referring to prefix areas 8 and 81 characteristic of processors 1 and 11 will become possible.
COPYRIGHT: (C)1979,JPO&Japio
JP4297778A1978-04-121978-04-12 Control method for multiprocessing equipmentExpiredJPS5854422B2 (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP4297778AJPS5854422B2 (en)1978-04-121978-04-12 Control method for multiprocessing equipment

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP4297778AJPS5854422B2 (en)1978-04-121978-04-12 Control method for multiprocessing equipment

Publications (2)

Publication NumberPublication Date
JPS54134947Atrue JPS54134947A (en)1979-10-19
JPS5854422B2 JPS5854422B2 (en)1983-12-05

Family

ID=12651091

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP4297778AExpiredJPS5854422B2 (en)1978-04-121978-04-12 Control method for multiprocessing equipment

Country Status (1)

CountryLink
JP (1)JPS5854422B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS5955565A (en)*1982-09-241984-03-30Fujitsu LtdMulti-firmware system
JPS60176152A (en)*1984-02-231985-09-10Fujitsu LtdPrefix area access control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS5955565A (en)*1982-09-241984-03-30Fujitsu LtdMulti-firmware system
JPS60176152A (en)*1984-02-231985-09-10Fujitsu LtdPrefix area access control system

Also Published As

Publication numberPublication date
JPS5854422B2 (en)1983-12-05

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