【０００１】[0001]
【発明の属する技術分野】本発明は非放射性誘電体線路
に関し、例えばミリ波集積回路等に組み込まれて、高周
波信号のガイドとして用いられる非放射性誘電体線路に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-radiative dielectric line, and more particularly, to a non-radiative dielectric line incorporated in a millimeter wave integrated circuit and used as a guide for high-frequency signals.
【０００２】[0002]
【従来の技術】従来の非放射性（Non Radiative Dielec
tricで、以下、ＮＲＤという）誘電体線路は、図７に示
すように、誘電体線路１の上下に平行平板導体２、３を
配置して構成され、このようなＮＲＤ誘電体線路は、平
行平板導体２、３の間隔がλ／２以下のとき、波長がλ
より大きい高周波信号は遮断されて平行平板導体２、３
間の空間には侵入できない。そして、平行平板導体２、
３の間に誘電体線路１を挿入すると、その誘電体線路１
に沿って高周波信号が伝搬でき、その高周波信号からの
放射波は平行平板導体２、３の遮断効果によって抑制さ
れる。前記波長λは近似的に真空中を伝搬する高周波信
号（電磁波）の波長に等しい。尚、図７において、誘電
体線路１の理解を容易にするために、上側の平行平板導
体３の一部を切り欠いて記載した。2. Description of the Related Art Conventional non-radiative dielec
As shown in FIG. 7, the dielectric line is formed by arranging parallel plate conductors 2 and 3 above and below a dielectric line 1, and such an NRD dielectric line is When the interval between the plate conductors 2 and 3 is λ / 2 or less, the wavelength is λ.
Larger high-frequency signals are cut off and parallel plate conductors 2, 3
You cannot enter the space between them. And the parallel plate conductor 2,
3, the dielectric line 1 is inserted between the dielectric lines 1.
A high-frequency signal can be propagated along, and a radiation wave from the high-frequency signal is suppressed by the blocking effect of the parallel plate conductors 2 and 3. The wavelength λ is approximately equal to the wavelength of a high-frequency signal (electromagnetic wave) propagating in a vacuum. In FIG. 7, a part of the upper parallel plate conductor 3 is cut away to facilitate understanding of the dielectric line 1.
【０００３】そして、図８（ａ）、（ｂ）に示すよう
に、誘電体線路１の中途にダイオード等の半導体素子が
設けられ、ＮＲＤ誘電体線路に、信号の周波数変換、ス
イッチング、減衰、検出等の機能を付加させていた。Ｎ
ＲＤ誘電体線路に半導体素子を取り付けるには、図８
（ａ）に示すように、誘電体基板４の一主面上に、外部
への高周波信号の漏洩を防ぐチョークパターン５と高周
波信号を受信する一対のアンテナパターン６を形成し、
誘電体線路１内の高周波信号の伝搬路に位置する一対の
アンテナパターン６間に、ダイオードなどの半導体素子
７を配置し接続した構造となっている。図９に、図８
（ｂ）の平面図を示す。As shown in FIGS. 8 (a) and 8 (b), a semiconductor element such as a diode is provided in the middle of the dielectric line 1, and a frequency conversion, switching, attenuation, A function such as detection was added. N
To attach a semiconductor element to the RD dielectric line, FIG.
As shown in (a), a choke pattern 5 for preventing leakage of a high-frequency signal to the outside and a pair of antenna patterns 6 for receiving a high-frequency signal are formed on one main surface of a dielectric substrate 4,
A semiconductor element 7 such as a diode is arranged and connected between a pair of antenna patterns 6 located on a propagation path of a high-frequency signal in the dielectric line 1. FIG.
FIG. 4B shows a plan view.
【０００４】尚、図８（ｂ）において、符号８は半導体
素子７に駆動用のバイアス電圧を入力したり、信号を出
力するための入出力導線、符号９は平行平板導体２に形
成された貫通孔である。入出力導線８は、平行平板導体
２に電気的に導通しない状態で貫通孔９を挿通し、バイ
アス回路、増幅回路等の電子回路に接続される。In FIG. 8B, reference numeral 8 denotes an input / output conductor for inputting a driving bias voltage to the semiconductor element 7 and outputting a signal, and reference numeral 9 denotes a parallel plate conductor 2. It is a through hole. The input / output conductor 8 is inserted into the through-hole 9 in a state where it is not electrically connected to the parallel plate conductor 2 and is connected to an electronic circuit such as a bias circuit and an amplifier circuit.
【０００５】他のＮＲＤ誘電体線路として、ダイオード
実装パターン部を誘電体線路の断面に接着し、チョーク
パターン部を別基板上に形成して、チョークパターン部
を誘電体線路の両方又は片方の側面に貼付又は蒸着した
ものも提案されている（特開平８−８６０３号公報参
照）。As another NRD dielectric line, a diode mounting pattern portion is adhered to a cross section of the dielectric line, a choke pattern portion is formed on another substrate, and the choke pattern portion is formed on both or one side of the dielectric line. Has been proposed (see JP-A-8-8603).
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来の非放射性誘電体線路では、誘電体基板４に形成され
たチョークパターン５や半導体素子７が外部に露出して
おり、製造工程や使用中にチョークパターン５や半導体
素子７が脱落したり、チョークパターン５や半導体素子
７にダメージを受ける危険があった。However, in the above-described conventional non-radiative dielectric line, the choke pattern 5 and the semiconductor element 7 formed on the dielectric substrate 4 are exposed to the outside, so that during the manufacturing process or during use, There is a risk that the choke pattern 5 or the semiconductor element 7 may fall off or be damaged.
【０００７】また、図９に示したように、誘電体基板４
に搭載されたダイオードなどの半導体素子７の部分に誘
電体線路１が当接する状態となるため、半導体素子７の
厚みだけ誘電体基板４と誘電体線路１との間に空隙Ｌが
形成され、インピーダンスのマッチングが十分にとれ
ず、素子が機能する帯域幅が狭くなるという欠点があっ
た。また、誘電体基板４と誘電体線路１との接続が不安
定になるという欠点もあった。[0007] Further, as shown in FIG.
Since the dielectric line 1 comes into contact with a portion of the semiconductor element 7 such as a diode mounted on the semiconductor substrate 7, a gap L is formed between the dielectric substrate 4 and the dielectric line 1 by the thickness of the semiconductor element 7, There is a disadvantage that the impedance cannot be sufficiently matched and the bandwidth in which the element functions is narrowed. There is also a disadvantage that the connection between the dielectric substrate 4 and the dielectric line 1 becomes unstable.
【０００８】また、入出力導線８が誘電体基板４の端部
に取り付けられており、この入出力導線８が平行平板導
体２の貫通孔９を挿通し、信号を平行平板導体２、３の
外部に導いていた。しかしながら、このような接続構造
は製造工程が非常に煩雑で作業性が悪く、量産化を妨げ
ていた。更に、誘電体基板４は厚さが薄く長さが長いた
め、しかも、上記したように、半導体素子７の厚みだけ
誘電体基板４と誘電体線路１との間に空隙Ｌが形成され
ているので、正確に位置決めして固定するのが困難で、
製造工程や使用中に位置ずれが生じたり、破損する危険
性があった。An input / output conductor 8 is attached to an end of the dielectric substrate 4, and the input / output conductor 8 is inserted through the through hole 9 of the parallel plate conductor 2 to transmit signals to the parallel plate conductors 2 and 3. Led to the outside. However, such a connection structure has a very complicated manufacturing process and poor workability, which hinders mass production. Furthermore, since the dielectric substrate 4 is thin and long, the gap L is formed between the dielectric substrate 4 and the dielectric line 1 by the thickness of the semiconductor element 7 as described above. So it is difficult to position and fix accurately,
There was a risk of misalignment or breakage during the manufacturing process or during use.
【０００９】更に、チョークパターン部を誘電体線路の
両方又は片方の側面に貼付又は蒸着した従来例において
は、入出力導線から高周波信号が外部に漏れたり、誘電
体線路のチョークパターンを貼付した部分とそれ以外の
部分のインピーダンスが異なるため、インピーダンス不
整合による高周波信号の反射が起こるという問題点があ
った。Further, in the conventional example in which the choke pattern portion is attached or vapor-deposited on both or one side of the dielectric line, a high frequency signal leaks from the input / output conductor to the outside, or the portion where the choke pattern of the dielectric line is attached. There is a problem that high-frequency signals are reflected due to impedance mismatching because the impedance of the other part differs from that of the other parts.
【００１０】本発明は、チョークパターンや半導体素子
の破損を防止できるとともに、高周波信号の透過特性が
良好な帯域幅を拡大することができ、さらに製造が容易
で量産に適する非放射性誘電体線路を提供することを目
的とする。The present invention provides a non-radiative dielectric line which can prevent breakage of a choke pattern and a semiconductor element, can widen a bandwidth having good transmission characteristics of a high-frequency signal, is easy to manufacture, and is suitable for mass production. The purpose is to provide.
【００１１】[0011]
【課題を解決するための手段】本発明の非放射性誘電体
線路は、波長λの高周波信号を伝搬する誘電体線路と、
この誘電体線路を挟持する一対の平行平板導体とから構
成され、前記一対の平行平板導体の間隔が前記高周波信
号の波長λの１／２以下である非放射性誘電体線路にお
いて、前記誘電体線路途中に、一対のアンテナパターン
と、該アンテナパターン間に配置され電気的に接続され
る半導体素子と、前記一対のアンテナパターンにそれぞ
れ接続されるチョークパターンとを内蔵する誘電体基板
を介装してなるものである。A non-radiative dielectric line according to the present invention comprises: a dielectric line for transmitting a high-frequency signal having a wavelength λ;
A non-radiative dielectric line, comprising a pair of parallel plate conductors sandwiching the dielectric line, wherein a distance between the pair of parallel plate conductors is equal to or less than の of a wavelength λ of the high-frequency signal; On the way, a dielectric substrate including a pair of antenna patterns, a semiconductor element disposed between the antenna patterns and electrically connected thereto, and a choke pattern connected to the pair of antenna patterns, respectively, is interposed. It becomes.
【００１２】ここで、誘電体基板の表面に、チョークパ
ターンと電気的に接続された表面電極を形成し、該表面
電極に接続された導体が、平行平板導体に形成された貫
通孔を該平行平板導体と非導通状態で挿通していること
が望ましい。Here, a surface electrode electrically connected to the choke pattern is formed on the surface of the dielectric substrate, and the conductor connected to the surface electrode passes through the through hole formed in the parallel plate conductor. It is desirable to pass through the flat conductor in a non-conductive state.
【００１３】[0013]
【作用】従来においては、誘電体基板に搭載されたダイ
オード等の半導体素子に誘電体線路を当接し、誘電体線
路途中に誘電体基板を介装していたため、誘電体基板の
強度や安定性が悪く、製造または使用中に誘電体基板が
位置ずれしたり、半導体素子やアンテナパターン、チョ
ークパターンが破損していたが、本発明では、誘電体基
板に、アンテナパターン、半導体素子およびチョークパ
ターンを内蔵したため、これらの半導体素子やパターン
を製造工程や使用中に保護することができるとともに、
誘電体基板の強度が向上し、また誘電体線路が当接する
部分は誘電体基板の平坦な表面であり、安定した状態で
接続することができる。これにより、製造または使用中
に誘電体基板が位置ずれすることがなく、誘電体基板を
正確な位置に取り付けることができる。In the past, a dielectric line was brought into contact with a semiconductor element such as a diode mounted on a dielectric substrate, and the dielectric substrate was interposed in the middle of the dielectric line, so that the strength and stability of the dielectric substrate were increased. Poor, the dielectric substrate was displaced during manufacturing or use, or the semiconductor element, the antenna pattern, and the choke pattern were damaged.In the present invention, however, the antenna pattern, the semiconductor element, and the choke pattern were formed on the dielectric substrate. Built-in, these semiconductor elements and patterns can be protected during the manufacturing process and use,
The strength of the dielectric substrate is improved, and the portion where the dielectric line contacts is the flat surface of the dielectric substrate, so that the connection can be made in a stable state. Thereby, the dielectric substrate can be mounted at an accurate position without being displaced during manufacture or use.
【００１４】また、誘電体基板の平坦な表面に誘電体線
路が当接するため、誘電体基板と誘電体線路との間に空
隙が形成されることを防止することができ、誘電体基板
と誘電体線路のインピーダンスマッチングが取りやすく
なり、高周波信号の透過特性が良好な帯域幅を拡大する
ことができる。Further, since the dielectric line is in contact with the flat surface of the dielectric substrate, it is possible to prevent a gap from being formed between the dielectric substrate and the dielectric line, and to prevent the dielectric substrate from being formed with the dielectric substrate. The impedance matching of the body line can be easily performed, and the bandwidth in which the transmission characteristic of the high-frequency signal is good can be expanded.
【００１５】また、本発明では、誘電体基板の表面に、
チョークパターンと電気的に接続された表面電極を形成
し、該表面電極に接続された導体が、平行平板導体に形
成された貫通孔を該平行平板導体と非導通状態で挿通し
ているため、従来のように煩雑で不安定な導線の取り付
けや取り回し工程を省略することができ、信頼性が高
く、安価に量産することができる非放射性誘電体線路が
得られる。In the present invention, the surface of the dielectric substrate is
Since a surface electrode electrically connected to the choke pattern is formed, and the conductor connected to the surface electrode penetrates a through hole formed in the parallel plate conductor in a non-conductive state with the parallel plate conductor, A non-radiative dielectric line which is highly reliable and can be mass-produced at a low cost can be obtained because a complicated and unstable mounting and routing process of a conducting wire as in the conventional case can be omitted.
【００１６】[0016]
【発明の実施の形態】本発明の非放射性誘電体線路の基
本構成の斜視図を図１に示す。尚、図１において、誘電
体線路の理解を容易にするために、上側の平行平板導体
の記載は省略した。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a perspective view showing the basic structure of a non-radiative dielectric line according to the present invention. In FIG. 1, the illustration of the upper parallel plate conductor is omitted to facilitate understanding of the dielectric waveguide.
【００１７】図１において、符号１１は誘電体線路であ
り、符号１２は下側の平行平板導体、１３は誘電体基板
を示している。In FIG. 1, reference numeral 11 denotes a dielectric line, reference numeral 12 denotes a lower parallel plate conductor, and reference numeral 13 denotes a dielectric substrate.
【００１８】そして、誘電体基板１３は、図２に示すよ
うに、一対の誘電体板１４、１５により、一対のアンテ
ナパターン１７と、これらのアンテナパターン１７間に
配置された半導体素子１８と、一対のアンテナパターン
１７にそれぞれ接続された一対のチョークパターン１９
とを挟持して構成されている。誘電体板１４には、半導
体素子１８を収容するべく、半導体素子１８の形状に合
致した凹部２０が形成されている。この凹部２０の大き
さには特に制限はないが、非放射性誘電体線路の特性を
充分引き出し、半導体素子１８の保護効果を確保するた
めに、なるべく素子１８の大きさと近いものが望まし
い。As shown in FIG. 2, the dielectric substrate 13 is composed of a pair of dielectric patterns 14 and 15, a pair of antenna patterns 17, and a semiconductor element 18 arranged between these antenna patterns 17. A pair of choke patterns 19 respectively connected to the pair of antenna patterns 17
Are sandwiched between them. The dielectric plate 14 is formed with a concave portion 20 that matches the shape of the semiconductor element 18 to accommodate the semiconductor element 18. The size of the concave portion 20 is not particularly limited, but is preferably as close as possible to the size of the non-radiative dielectric line in order to sufficiently extract the characteristics of the non-radiative dielectric line and secure the protection effect of the semiconductor element 18.
【００１９】半導体素子１８の両側に形成されたチョー
クパターン１９には、それぞれ信号取出用の表面電極２
１が電気的に接続されており、これらの信号取出用の表
面電極２１は、図１および図３に示すように、誘電体基
板１３の上面に形成されている。The choke patterns 19 formed on both sides of the semiconductor element 18 have surface electrodes 2 for signal extraction, respectively.
1 are electrically connected, and the surface electrodes 21 for taking out these signals are formed on the upper surface of the dielectric substrate 13 as shown in FIGS.
【００２０】表面電極２１は、誘電体基板１３の上面に
チョークパターン１９を延長させて形成したり、別個の
電極を形成する等して形成すればよく、表面電極２１と
チョークパターン１９とを半田、導電性接着剤等を用い
て接続する。The surface electrode 21 may be formed by extending the choke pattern 19 on the upper surface of the dielectric substrate 13 or by forming a separate electrode. The surface electrode 21 and the choke pattern 19 are soldered. , Using a conductive adhesive or the like.
【００２１】これらの表面電極２１には導体２３が接続
され、導体２３が、上側の平行平板導体２４に形成され
た貫通孔２５を該平行平板導体２４と非導通状態で挿通
している。このような導体２３は、バイアス回路、増幅
回路等の他の電子回路に接続される。このような構成に
よれば生産性が高く量産に適している。この場合、必要
に応じ、貫通孔２５の内部を樹脂等の絶縁物質等で充填
する、貫通孔２５の内壁に絶縁物質等をコーティングす
る、又は導体２３を絶縁チューブで被覆してもよい。A conductor 23 is connected to these surface electrodes 21, and the conductor 23 passes through the through hole 25 formed in the upper parallel plate conductor 24 in a non-conductive state with the parallel plate conductor 24. Such a conductor 23 is connected to another electronic circuit such as a bias circuit and an amplifier circuit. According to such a configuration, productivity is high and suitable for mass production. In this case, if necessary, the inside of the through hole 25 may be filled with an insulating material such as resin, the inner wall of the through hole 25 may be coated with an insulating material, or the conductor 23 may be covered with an insulating tube.
【００２２】本発明において、誘電体線路１１はテフロ
ン等の低損失樹脂材料、コージェライト等の低誘電率セ
ラミック材料から成るのが好ましく、これらは低損失で
加工が容易であり、量産に適している。また、誘電体線
路１１は一組の平行平板導体に複数設けても構わない。In the present invention, the dielectric line 11 is preferably made of a low-loss resin material such as Teflon or a low-dielectric ceramic material such as cordierite, which is low-loss, easy to process, and suitable for mass production. I have. Further, a plurality of dielectric lines 11 may be provided on a set of parallel plate conductors.
【００２３】前記半導体素子１８としては、高周波半導
体ダイオード、ガンダイオード、インパットダイオー
ド、可変容量ダイオード、ショットキーダイオード、バ
ラクタダイオード、ＰＩＮダイオード等を使用でき、こ
れらのダイオードに限らず、半導体素子１８がインダク
タ、キャパシタ、トランジスタ等の機能を有するもので
もよい。また、半導体素子１８は、誘電体線路１１の中
途であればどこにあってもよい。The semiconductor element 18 may be a high-frequency semiconductor diode, a Gunn diode, an input diode, a variable capacitance diode, a Schottky diode, a varactor diode, a PIN diode, or the like. The semiconductor element 18 is not limited to these diodes. It may have a function such as an inductor, a capacitor, or a transistor. Further, the semiconductor element 18 may be located anywhere in the dielectric line 11.
【００２４】前記平行平板導体１２は、高い電気伝導度
及び加工性の点で、Ｃｕ、Ａｌ、Ｆｅ、ＳＵＳ（ステン
レス）、Ａｇ、Ａｕ、Ｐｔ等の導体板、あるいはこられ
の導体層を表面に形成した絶縁板でもよい。The parallel plate conductor 12 is made of a conductor plate of Cu, Al, Fe, SUS (stainless steel), Ag, Au, Pt, or the like, or a conductor layer made of such a conductor, in view of high electric conductivity and workability. May be used.
【００２５】また、アンテナパターン１７とチョークパ
ターン１９は、高い電気伝導度を有するＡｕ、Ｃｕ、Ａ
ｌ等の材料が好ましい。The antenna pattern 17 and the choke pattern 19 are made of Au, Cu, A having high electric conductivity.
Materials such as 1 are preferred.
【００２６】本発明のチョークパターン１９は蒸着法等
で成膜するか、チョークパターン１９の形状に成形した
薄い金属板を張り付けて構成する。このチョークパター
ン１９は、基本的に１／４波長チョークパターンとする
ことにより高周波信号を阻止するインダクタ（チョーク
コイル）と等価なものとなり、高周波信号は外部へ漏洩
しない。また、このチョークパターン１９は、上記と同
様の効果が得られるものであれば、１／４波長チョーク
パターン以外のパターンでも構わない。The chalk pattern 19 of the present invention is formed by forming a film by a vapor deposition method or the like, or by attaching a thin metal plate formed in the shape of the chalk pattern 19. The choke pattern 19 is basically equivalent to an inductor (choke coil) that blocks a high-frequency signal by forming a quarter-wave choke pattern, and the high-frequency signal does not leak to the outside. The choke pattern 19 may be a pattern other than the quarter-wave choke pattern as long as the same effect as described above can be obtained.
【００２７】以上のように構成された非放射性誘電体線
路では、アンテナパターン１７、半導体素子１８、チョ
ークパターン１９を内蔵する誘電体基板１３を、誘電体
線路１１途中に介装したため、チョークパターン１９等
の素子を製造工程や使用中のダメージから保護すること
ができる。In the non-radiative dielectric line constructed as described above, the dielectric substrate 13 containing the antenna pattern 17, the semiconductor element 18, and the choke pattern 19 is interposed in the dielectric line 11, so that the choke pattern 19 Can be protected from damage during the manufacturing process and during use.
【００２８】また、本発明では、誘電体板１４、１５に
より、アンテナパターン１７、半導体素子１８およびチ
ョークパターン１９を挟持して誘電体基板１３を構成し
たため、誘電体基板１３の強度が向上し、また誘電体線
路１１が当接する部分は誘電体基板１３の平坦な表面で
あり、安定した状態で接続することができる。これによ
り、製造または使用中に誘電体基板１３が位置ずれする
ことがなく、誘電体基板１３を正確な位置に取り付ける
ことができる。In the present invention, since the dielectric substrate 13 is formed by sandwiching the antenna pattern 17, the semiconductor element 18 and the choke pattern 19 between the dielectric plates 14 and 15, the strength of the dielectric substrate 13 is improved. The portion where the dielectric line 11 contacts is the flat surface of the dielectric substrate 13 and can be connected in a stable state. This allows the dielectric substrate 13 to be mounted at an accurate position without displacement of the dielectric substrate 13 during manufacture or use.
【００２９】また、誘電体基板１３の平坦な表面に誘電
体線路１１が当接するため、誘電体基板１３と誘電体線
路１１との間に空隙が形成されることを防止でき、誘電
体基板１３と誘電体線路１１のインピーダンスマッチン
グが取りやすくなり、高周波信号の透過特性が良好な帯
域幅を拡大することができる。Further, since the dielectric line 11 abuts on the flat surface of the dielectric substrate 13, it is possible to prevent a gap from being formed between the dielectric substrate 13 and the dielectric line 11. And the dielectric line 11 can be easily impedance-matched, and the bandwidth in which the high-frequency signal transmission characteristics are favorable can be expanded.
【００３０】また、本発明では、誘電体基板１３の表面
に、チョークパターン１９と電気的に接続された表面電
極２１を形成し、該表面電極２１に接続された導体２３
が、平行平板導体１２に形成された貫通孔２５を該平行
平板導体１２と非導通状態で挿通しているため、従来の
ように煩雑で不安定な導線の取り付けや取り回し工程を
省略することができ、信頼性が高く、安価に量産するこ
とができる非放射性誘電体線路が得られる。According to the present invention, a surface electrode 21 electrically connected to the choke pattern 19 is formed on the surface of the dielectric substrate 13, and a conductor 23 connected to the surface electrode 21 is formed.
However, since the through-hole 25 formed in the parallel plate conductor 12 is inserted through the parallel plate conductor 12 in a non-conductive state, it is possible to omit a complicated and unstable mounting and routing step of the conductor as in the related art. Thus, a non-radiative dielectric line having high reliability and mass production at low cost can be obtained.
【００３１】尚、本発明は上記の実施形態に限定される
ものではなく、本発明の要旨を逸脱しない範囲内で種々
の変更は何等差し支えない。It should be noted that the present invention is not limited to the above embodiment, and various changes may be made without departing from the scope of the present invention.
【００３２】また、外部への電磁波の漏洩による損失を
考慮しなくても良い場合や、外部にチョーク回路を設け
た場合は、図６に示すようにチョークパターンを省略す
ることもできる。つまり、誘電体基板１３は、誘電体板
１４、１５により、アンテナパターン１７、半導体素子
１８を挟持して構成されている。Further, when it is not necessary to consider the loss due to the leakage of the electromagnetic wave to the outside, or when a choke circuit is provided outside, the choke pattern can be omitted as shown in FIG. That is, the dielectric substrate 13 is configured by sandwiching the antenna pattern 17 and the semiconductor element 18 between the dielectric plates 14 and 15.
【００３３】さらに、本発明では、図２のように、例え
ば一方の誘電体板１５のアンテナパターン１７上に半導
体素子１８を取り付けた後、他方の誘電体板１４を半導
体素子１８を挟み込むように接着するが、この接着は充
分な接着強度が保てるものならばどのような方法でも良
い。Further, in the present invention, as shown in FIG. 2, for example, after the semiconductor element 18 is mounted on the antenna pattern 17 of one dielectric plate 15, the other dielectric plate 14 is sandwiched by the semiconductor element 18. Adhesion may be performed by any method as long as sufficient adhesion strength can be maintained.
【００３４】[0034]
【実施例】図１のＮＲＤ誘電体線路を以下のようにして
作製した。Ｃｕから成り、１００×１００×８ｍｍの２
枚の平行平板導体１２、２４を用意した。EXAMPLE The NRD dielectric line shown in FIG. 1 was manufactured as follows. Made of Cu, 100 × 100 × 8mm2
The parallel plate conductors 12 and 24 were prepared.
【００３５】次に、誘電体板１４、１５の材料として厚
さ０．３ｍｍのテフロンシートを用い、図２に示すよう
に誘電体基板１３を形成した。つまり、先ず、誘電体板
１５にアンテナパターン１７、チョークパターン１９を
金を蒸着して形成した。また、これらと同時にチョーク
パターン１９に接続する表面電極２１を、誘電体板１５
の上面に形成した。Next, as shown in FIG. 2, a dielectric substrate 13 was formed using a Teflon sheet having a thickness of 0.3 mm as a material for the dielectric plates 14 and 15. That is, first, the antenna pattern 17 and the choke pattern 19 were formed on the dielectric plate 15 by depositing gold. At the same time, the surface electrode 21 connected to the choke pattern 19 is connected to the dielectric plate 15.
Was formed on the upper surface.
【００３６】半導体素子１８として高周波用のビームリ
ード型のＰＩＮダイオードを使用し、誘電体板１５のア
ンテナパターン１７の間に導電性接着剤を用いて接着し
た。A high frequency beam lead type PIN diode was used as the semiconductor element 18 and bonded between the antenna patterns 17 of the dielectric plate 15 using a conductive adhesive.
【００３７】他方の誘電体板１４にはこのダイオードに
合わせた大きさの凹部２０を作成し、ダイオードを取り
付けた誘電体板１５に接着剤によって張り付けた。A recess 20 having a size corresponding to the diode was formed in the other dielectric plate 14 and attached to the dielectric plate 15 on which the diode was mounted with an adhesive.
【００３８】この後、コージェライトから成り、高さ
２．２５ｍｍ×巾１ｍｍの誘電体線路１１を下側の平行
平板導体１２上に配置するとともに、誘電体基板１３
を、誘電体線路１１がチョークパターン１９の中央部を
横切るように誘電体線路１１の途中に介装し、接着し
た。Thereafter, a dielectric line 11 made of cordierite and having a height of 2.25 mm × a width of 1 mm is arranged on the lower parallel plate conductor 12 and a dielectric substrate 13 is formed.
Was interposed in the middle of the dielectric line 11 so that the dielectric line 11 crosses the center of the choke pattern 19, and was bonded.
【００３９】そして、図４に示すように、誘電体板１５
の上面に形成された表面電極２１にテフロンチューブで
被覆した導体２３を接続し、上側の平行平板導体２４
に、表面電極２１に対応するように貫通孔２５を形成
し、導体２３を平行平板導体２４の貫通孔２５を挿通せ
しめた。Then, as shown in FIG.
A conductor 23 covered with a Teflon tube is connected to a surface electrode 21 formed on the upper surface of the
Then, a through hole 25 was formed so as to correspond to the surface electrode 21, and the conductor 23 was inserted through the through hole 25 of the parallel plate conductor 24.
【００４０】一方、本発明者等は、図８の従来品を、コ
ーディライトから成る誘電体線路及び誘電体基板、Ａｕ
から成るチョークパターン及びアンテナパターン、ビー
ムリード型ＰＩＮダイオードを用いて作製し、ミリ波
（数１０〜数１００ＧＨｚ帯）透過特性について、上記
本発明のものと比較したグラフを図５に示す。このグラ
フより、本発明の非放射性誘電体線路では、高周波信号
の透過特性が良好な帯域幅を従来品よりも拡大できるこ
とが判る。On the other hand, the present inventors changed the conventional product shown in FIG. 8 to a dielectric line made of cordierite, a dielectric substrate, and Au.
FIG. 5 is a graph showing the transmission characteristics of a millimeter wave (several tens to several hundreds of GHz band) produced by using a choke pattern and an antenna pattern formed of a beam lead type PIN diode and compared with those of the present invention. From this graph, it can be seen that in the non-radiative dielectric line of the present invention, the bandwidth in which the high-frequency signal transmission characteristics are good can be expanded as compared with the conventional product.
【００４１】[0041]
【発明の効果】本発明の非放射性誘電体導波路では、誘
電体基板に、アンテナパターン、半導体素子およびチョ
ークパターンを内蔵したため、これらの半導体素子やパ
ターンを製造工程や使用中に保護することができるとと
もに、誘電体基板の強度が向上し、また誘電体線路が当
接する部分は誘電体基板の平坦な表面であり、安定した
状態で接続することができる。これにより、製造または
使用中に誘電体基板が位置ずれすることがなく、誘電体
基板を正確な位置に取り付けることができる。According to the non-radiative dielectric waveguide of the present invention, since the antenna substrate, the semiconductor element and the choke pattern are built in the dielectric substrate, these semiconductor elements and patterns can be protected during the manufacturing process and during use. In addition to this, the strength of the dielectric substrate is improved, and the portion where the dielectric line contacts is the flat surface of the dielectric substrate, so that the connection can be made in a stable state. Thereby, the dielectric substrate can be mounted at an accurate position without being displaced during manufacture or use.
【００４２】また、誘電体基板の平坦な表面に誘電体線
路が当接するため、誘電体基板と誘電体線路との間に空
隙が形成されることを防止することができ、誘電体基板
と誘電体線路のインピーダンスマッチングが取りやすく
なり、高周波信号の透過特性が良好な帯域幅を拡大する
ことができる。Further, since the dielectric line abuts on the flat surface of the dielectric substrate, it is possible to prevent a gap from being formed between the dielectric substrate and the dielectric line, and to prevent the dielectric substrate from being in contact with the dielectric substrate. The impedance matching of the body line can be easily performed, and the bandwidth in which the transmission characteristic of the high-frequency signal is good can be expanded.
【図１】本発明の非放射性誘電体線路を示す斜視図であ
る。FIG. 1 is a perspective view showing a non-radiative dielectric line of the present invention.
【図２】図１の誘電体基板の構成を示す分解斜視図であ
る。FIG. 2 is an exploded perspective view showing the configuration of the dielectric substrate of FIG.
【図３】図１の非放射性誘電体線路の平面図である。FIG. 3 is a plan view of the non-radiative dielectric line of FIG. 1;
【図４】誘電体基板の表面電極に接続された導体が、上
側の平行平板導体の貫通孔を挿通している状態を示す断
面図である。FIG. 4 is a cross-sectional view showing a state where a conductor connected to a surface electrode of a dielectric substrate is inserted through a through hole of an upper parallel plate conductor.
【図５】非放射性誘電体線路のミリ波（数１０〜数１０
０ＧＨｚ帯）透過特性を示すグラフである。FIG. 5 shows millimeter waves (numbers 10 to 10) of a nonradiative dielectric line.
9 is a graph showing transmission characteristics (0 GHz band).
【図６】チョークパターンを形成しない場合の誘電体基
板を示す斜視図である。FIG. 6 is a perspective view showing a dielectric substrate when a choke pattern is not formed.
【図７】従来の非放射性誘電体線路を示す斜視図であ
る。FIG. 7 is a perspective view showing a conventional non-radiative dielectric line.
【図８】従来の非放射性誘電体線路を示す斜視図であ
る。FIG. 8 is a perspective view showing a conventional non-radiative dielectric line.
【図９】図８の非放射性誘電体線路の平面図である。FIG. 9 is a plan view of the non-radiative dielectric waveguide of FIG. 8;
１１・・・誘電体線路 １２・・・下側の平行平板導体 １３・・・誘電体基板 １４、１５・・・誘電体板 １７・・・アンテナパターン １８・・・半導体素子 １９・・・チョークパターン ２０・・・凹部 ２１・・・表面電極 ２３・・導体 ２４・・・上側の平行平板導体 ２５・・・貫通孔 DESCRIPTION OF SYMBOLS 11 ... Dielectric line 12 ... Lower parallel plate conductor 13 ... Dielectric substrate 14, 15 ... Dielectric plate 17 ... Antenna pattern 18 ... Semiconductor element 19 ... Choke Pattern 20: recess 21: surface electrode 23: conductor 24: upper parallel plate conductor 25: through hole
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22617397AJP3762058B2 (en) | 1997-08-22 | 1997-08-22 | Non-radiative dielectric line |
| US09/104,089US6094106A (en) | 1997-06-25 | 1998-06-24 | Non-radiative dielectric waveguide module |
| DE19828488ADE19828488B4 (en) | 1997-06-25 | 1998-06-25 | Module with a radiation-free dielectric waveguide |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22617397AJP3762058B2 (en) | 1997-08-22 | 1997-08-22 | Non-radiative dielectric line |
| Publication Number | Publication Date |
|---|---|
| JPH1168418Atrue JPH1168418A (en) | 1999-03-09 |
| JP3762058B2 JP3762058B2 (en) | 2006-03-29 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22617397AExpired - Fee RelatedJP3762058B2 (en) | 1997-06-25 | 1997-08-22 | Non-radiative dielectric line |
| Country | Link |
|---|---|
| JP (1) | JP3762058B2 (en) |
| Publication number | Publication date |
|---|---|
| JP3762058B2 (en) | 2006-03-29 |
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