【０００１】[0001]
【発明の属する技術分野】本発明は、ゲート絶縁膜を介
し半導体層上方にゲート配線層を有するトップゲート型
の薄膜トランジスタ装置及び薄膜トランジスタ装置の製
造方法並びにトップゲート型の薄膜トランジスタ装置を
駆動素子とするアクティブマトリクス型液晶表示装置に
関する。The present invention relates to a top gate type thin film transistor device having a gate wiring layer above a semiconductor layer via a gate insulating film, a method of manufacturing the thin film transistor device, and an active device using the top gate type thin film transistor device as a driving element. The present invention relates to a matrix type liquid crystal display device.
【０００２】[0002]
【従来の技術】半導体材料としてポリシリコンを用いた
薄膜トランジスタ装置（以下ＴＦＴと称する。）は、移
動度が数１０〜数１００cm2／Ｖｓと高い事から、アク
ティブマトリクス液晶表示装置の画素部の駆動素子や回
路部駆動素子として用いられる。そして画素部の駆動素
子として一般に用いられるトップゲート型のｎ型のポリ
シリコンＴＦＴに在っては、ＴＦＴがオフ状態の時にリ
ーク電流を生じてしまうため、ソース及びドレイン間に
かかる電界を緩和する様、チャネル層と高濃度の不純物
を有するドレイン領域との間に、微量に不純物を添加し
た低濃度不純物（以下ＬＤＤと称する。）領域を設け
て、リーク電流の低減を図っている。2. Description of the Related Art As a semiconductor material (hereinafter referred to as TFT.) Thin film transistor device using the polysilicon, since it is as high as several tens to several hundreds 100 cm2 / Vs mobility, the driving of the pixel portion of the active matrix liquid crystal display device It is used as an element or a circuit section driving element. In a top gate type n-type polysilicon TFT generally used as a driving element of a pixel portion, a leak current occurs when the TFT is in an off state, so that an electric field applied between a source and a drain is reduced. As described above, a low-concentration impurity (hereinafter, referred to as LDD) region to which a small amount of impurity is added is provided between the channel layer and the drain region having a high concentration of impurity to reduce leakage current.
【０００３】この様なＬＤＤ領域を有するＴＦＴは、従
来、図５に示すように製造されていた。即ち、 図５（イ）に示す様にガラス基板１上に酸化シリコン
（ＳｉＯ2）からなるアンダーコート膜２を成膜した
後、、アモルファスシリコン膜を積層し、レーザアニー
ルにより、アモルファスシリコン膜をポリシリコン膜に
結晶化し、マトリクス状にパターニングしポリシリコン
膜からなる半導体層３を形成する。A TFT having such an LDD region has been conventionally manufactured as shown in FIG. That is, as shown in FIG. 5A, after forming an undercoat film 2 made of silicon oxide (SiO2 ) on a glass substrate 1, an amorphous silicon film is laminated, and the amorphous silicon film is formed by laser annealing. The semiconductor layer 3 made of a polysilicon film is formed by crystallization into a polysilicon film and patterning in a matrix.
【０００４】図５（ロ）に示す様にゲート絶縁膜４、
ゲート配線６を形成し、低ドーズにてリン（Ｐ+）イオ
ンをドーピングし半導体層３にチャネル領域３−１、Ｌ
ＤＤ領域３−２を形成する。[0004] As shown in FIG.
A gate wiring 6 is formed, and phosphorus (P+ ) ions are doped at a low dose, and a channel region 3-1 and an L
The DD region 3-2 is formed.
【０００５】図５（ハ）に示す様にレジストマスク７
を形成し、高ドーズにてリン（Ｐ+）イオンをドーピン
グし、半導体層３にｎ+のソース・ドレイン領域３−３
を形成する。[0005] As shown in FIG.
Is formed, and phosphorus (P+ ) ions are doped at a high dose, and n+ source / drain regions 3-3 are formed in the semiconductor layer 3.
To form
【０００６】図５（ニ）に示す様にマスク７を除去
し、層間絶縁膜８を形成する。[0006] As shown in FIG. 5 D, the mask 7 is removed, and an interlayer insulating film 8 is formed.
【０００７】図５（ホ）に示す様にコンタクトホール
１０ａ、１０ｂを形成し、ソース電極１２、ドレイン電
極１３を形成し、ＬＤＤ領域を有するＴＦＴ１４装置を
完成していた。As shown in FIG. 5E, contact holes 10a and 10b are formed, a source electrode 12 and a drain electrode 13 are formed, and a TFT device having an LDD region is completed.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら上記従来
のＴＦＴにあっては、レジストマスクを用いてＬＤＤ領
域を形成することから、レジストマスク形成時のパター
ンの合わせずれ、及びゲート配線のサイドエッチング量
のばらつきにより、ＬＤＤ領域の長さを１〜５μｍの範
囲内でしか制御できず、１μｍ以下の範囲での微細な長
さ制御が不可能であり、ＬＤＤ領域の長さのばらつきが
大きくなり、ひいてはＴＦＴの特性にばらつきを生じる
一方、ＬＤＤ領域の長さが長くなるとＴＦＴは直列に抵
抗を有する状況となり、移動度の低下を招き、液晶表示
装置にあっては画面が部分的にしか表示されず、表示品
位が著しく低下されてしまい特に大型のアクティブマト
リクス型液晶表示装置への適用が不能になる等の問題を
生じていた。However, in the above-mentioned conventional TFT, since the LDD region is formed using the resist mask, the misalignment of the pattern when forming the resist mask and the side etching amount of the gate wiring are reduced. Due to the variation, the length of the LDD region can be controlled only within the range of 1 to 5 μm, and it is impossible to finely control the length within the range of 1 μm or less, and the variation in the length of the LDD region becomes large. While the characteristics of the TFT vary, while the length of the LDD region is increased, the TFT has a resistance in series, which causes a decrease in mobility, and in a liquid crystal display device, the screen is only partially displayed. In addition, there has been a problem that the display quality is remarkably deteriorated, and application to a large active matrix type liquid crystal display device becomes impossible.
【０００９】そこで本発明は上記課題を除去するもの
で、ＬＤＤ領域長の微細な制御が可能であり、安定した
特性を有すると共に、移動度が高く大型アクティブマト
リクス液晶表示装置にあっても良好な表示を得られる薄
膜トランジスタ装置及び薄膜トランジスタ装置の製造方
法並びに液晶表示装置を提供することを目的とする。Accordingly, the present invention has been made to solve the above problems, and enables fine control of the length of the LDD region, has stable characteristics, has high mobility, and is suitable for a large active matrix liquid crystal display device. It is an object to provide a thin film transistor device capable of obtaining a display, a method for manufacturing the thin film transistor device, and a liquid crystal display device.
【００１０】[0010]
【課題を解決するための手段】本発明は上記課題を解決
するため、絶縁性基板と、この絶縁性基板上に形成され
るポリシリコンからなるチャネル領域と、低濃度不純物
領域を介して前記チャネル領域を挾み前記ポリシリコン
を低抵抗化して成るソース・ドレイン領域と、ゲート絶
縁膜を介し前記チャネル領域上に形成され前記チャネル
領域側の第１層の断面が順テーパ形状であり表面側の第
２層の断面が逆テーパ形状の２層構造を有するゲート配
線層と、層間絶縁膜を介し前記ソース・ドレイン領域に
接続されるソース・ドレイン配線層とを設けるものであ
る。In order to solve the above-mentioned problems, the present invention provides an insulating substrate, a channel region made of polysilicon formed on the insulating substrate, and the channel through a low-concentration impurity region. A cross section of a source / drain region formed by lowering the resistance of the polysilicon with the region interposed therebetween and a first layer formed on the channel region with a gate insulating film interposed therebetween has a forward tapered shape, and A gate wiring layer having a two-layer structure in which the second layer has a reverse tapered cross section, and a source / drain wiring layer connected to the source / drain region via an interlayer insulating film are provided.
【００１１】又本発明は上記課題を解決するため、絶縁
性基板上にポリシリコン層及びゲート絶縁膜を形成する
工程と、前記ゲート絶縁膜上に第１のゲート金属膜を成
膜する工程と、前記第１のゲート金属膜上に第２のゲー
ト金属膜を成膜する工程と、前記第１のゲート金属膜の
断面を順テーパ形状に加工すると共に前記第２のゲート
金属膜の断面を逆テーパ形状に加工し２層構造のゲート
配線層を形成する工程と、前記ゲート配線層をマスクに
して前記ポリシリコン層にイオンドーピングし低濃度不
純物領域及びソース・ドレイン領域を同時に形成する工
程とを実施するものである。According to another aspect of the present invention, there is provided a method of forming a polysilicon layer and a gate insulating film on an insulating substrate, and forming a first gate metal film on the gate insulating film. Forming a second gate metal film on the first gate metal film, processing the cross section of the first gate metal film into a forward tapered shape, and forming a cross section of the second gate metal film on the first gate metal film. Forming a gate wiring layer having a two-layer structure by processing into a reverse taper shape; and ion-doping the polysilicon layer using the gate wiring layer as a mask to simultaneously form low-concentration impurity regions and source / drain regions. Is implemented.
【００１２】又本発明は上記課題を解決するため、第１
の絶縁性基板と、この第１の絶縁性基板上にマトリクス
状に配列される画素電極と、前記第１の絶縁性基板上に
形成されるポリシリコンからなるチャネル領域及び、低
濃度不純物領域を介して前記チャネル領域を挾み前記ポ
リシリコンを低抵抗化して成るソース・ドレイン領域並
びに、ゲート絶縁膜を介し前記チャネル領域上に形成さ
れ前記チャネル領域側の第１層の断面が順テーパ形状で
あり表面側の第２層の断面が逆テーパ形状の２層構造を
有するゲート配線層更に、層間絶縁膜を介し前記ソース
・ドレイン領域に接続されるソース・ドレイン配線層を
有し前記画素電極を駆動する薄膜トランジスタ装置とを
有するアレイ基板と、第２の絶縁基板と、この第２の絶
縁基板上に形成される対向電極とを有し、前記アレイ基
板に対向して配置される対向基板と、前記アレイ基板及
び前記対向基板間に封入される液晶組成物とを設けるも
のである。Further, the present invention provides a first method for solving the above problems.
An insulating substrate, pixel electrodes arranged in a matrix on the first insulating substrate, a channel region made of polysilicon formed on the first insulating substrate, and a low-concentration impurity region. A source / drain region formed by lowering the resistance of the polysilicon with the channel region interposed therebetween, and a first layer formed on the channel region with a gate insulating film interposed therebetween has a forward tapered cross section. A gate wiring layer having a two-layer structure in which the cross section of the second layer on the front surface side has an inverted taper shape; An array substrate having a thin film transistor device to be driven; a second insulating substrate; and a counter electrode formed on the second insulating substrate, and arranged to face the array substrate. A counter substrate which is intended to provide a liquid crystal composition sealed between the array substrate and the counter substrate.
【００１３】上記構成により、所望の長さのＬＤＤを容
易に得る事ができ、薄膜トランジスタの移動度の低下を
生じる事無くかつ特性の安定化を図り、表示品位の良好
な液晶表示装置を得るものである。According to the above structure, an LDD having a desired length can be easily obtained, a characteristic of the thin film transistor can be stabilized without lowering the mobility of the thin film transistor, and a liquid crystal display device with good display quality can be obtained. It is.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態を図１
乃至図３を参照して説明する。１６は、アクティブマト
リクス型の液晶表示装置であり、駆動素子としてポリシ
リコンの半導体層を有するトップゲート型のＴＦＴ１７
を用いるアレイ基板１８及び対向基板１９の間に、配向
膜２０ａ、２０ｂを介して液晶組成物２１を保持すると
共に偏光板２２ａ、２０ｂを有している。FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIGS. Reference numeral 16 denotes an active matrix type liquid crystal display device, which is a top gate type TFT 17 having a polysilicon semiconductor layer as a driving element.
The liquid crystal composition 21 is held between the array substrate 18 and the counter substrate 19 using the alignment films 20a and 20b via the alignment films 20a and 20b, and the substrate has polarizing plates 22a and 20b.
【００１５】ここでアレイ基板１８の第１の絶縁基板で
あるガラス基板２３上の、酸化シリコン（ＳｉＯ2）か
らなるアンダーコート層２４上には、ポリシリコンから
なるチャネル領域２６−１、低ドーズのリン（Ｐ+）イ
オンがドーピングされるＬＤＤ領域２６−２、高ドース
のリン（Ｐ+）イオンがドーピングされるソース領域２
６−３、ドレイン領域２６−４を有するｎ型の半導体層
２６がパターン形成され、この半導体層２６上にはゲー
ト絶縁膜２７を介し第１のゲート金属膜である第１層２
８ａの断面が３０度の順テーパ形状であり第２のゲート
金属膜である第２層２８ｂの断面が３０度の逆テーパ形
状の２層構造を有するモリブデン−タングステン合金
（以下ＭｏＷと略称する。）からなるゲート配線層２８
が形成されてなるＴＦＴ１７が設けられ、又ゲート配線
層２８と同一面上には、補助容量線３０が形成されてい
る。Here, a channel region 26-1 made of polysilicon and a low dose are formed on an undercoat layer 24 made of silicon oxide (SiO2 ) on a glass substrate 23 which is a first insulating substrate of the array substrate 18. of phosphorus (P+) LDD region 26-2 which ions are doped, the source region 2 higher doses of phosphorus (P+) ions are doped
6-3, an n-type semiconductor layer 26 having a drain region 26-4 is patterned and formed on the semiconductor layer 26 via a gate insulating film 27 as a first layer 2 which is a first gate metal film.
A molybdenum-tungsten alloy (hereinafter abbreviated as MoW) having a two-layer structure in which the cross section of 8a has a forward tapered shape of 30 degrees and the second layer 28b as a second gate metal film has a reverse tapered shape of 30 degrees in cross section. ) Gate wiring layer 28
Are formed, and an auxiliary capacitance line 30 is formed on the same surface as the gate wiring layer 28.
【００１６】更に層間絶縁膜３１を介し画素電極３２が
形成され、層間絶縁膜３１上には信号線と一体のドレイ
ン電極３３、ソース領域２６−３及び画素電極３２を接
続するソース電極３４が形成され、コンタクトホール３
３ａ、３４ａを介しそれぞれドレイン領域２６−４、ソ
ース領域２６−３に接続されている。又３６は保護膜で
ある。Further, a pixel electrode 32 is formed via an interlayer insulating film 31. On the interlayer insulating film 31, a drain electrode 33 integrated with a signal line, a source region 26-3 and a source electrode 34 connecting the pixel electrode 32 are formed. Contact hole 3
They are connected to the drain region 26-4 and the source region 26-3 via 3a and 34a, respectively. Reference numeral 36 denotes a protective film.
【００１７】一方対向基板１９は、第２の絶縁基板であ
るガラス基板３７の全面に対向電極３８及び保護膜４０
を有し、アレイ基板１８との間に液晶組成物２１を封入
し、液晶表示装置１６を構成している。On the other hand, the opposing substrate 19 has an opposing electrode 38 and a protective film 40 all over a glass substrate 37 which is a second insulating substrate.
And the liquid crystal composition 21 is sealed between the liquid crystal composition 21 and the array substrate 18 to constitute the liquid crystal display device 16.
【００１８】次にアレイ基板１８上のＴＦＴ１７の製造
工程について述べる。Next, a manufacturing process of the TFT 17 on the array substrate 18 will be described.
【００１９】図３（イ）に示す様に先ずガラス基板２
３上に酸化シリコン膜（ＳｉＯ2）からなるアンダーコ
ート層２４、アモルファスシリコン膜４１を順次積層
し、レーザアニールによりアモルファスシリコン膜４１
をポリシリコン膜に結晶化する。First, as shown in FIG.
An undercoat layer 24 made of a silicon oxide film (SiO2 ) and an amorphous silicon film 41 are sequentially laminated on the substrate 3, and the amorphous silicon film 41 is formed by laser annealing.
Is crystallized into a polysilicon film.
【００２０】図３（ロ）に示す様に結晶化されたポリ
シリコン膜からなる半導体層２６をマトリクス状にパタ
ーニングする。As shown in FIG. 3B, the semiconductor layer 26 made of a crystallized polysilicon film is patterned in a matrix.
【００２１】図３（ハ）に示す様にゲート絶縁膜２７
を１００ｎｍ形成した後、スパッタリングによりＭｏＷ
にてゲート配線層２８の第１層２８ａを５０ｎｍ形成
し、一度大気にさらす。As shown in FIG. 3C, the gate insulating film 27 is formed.
Is formed to a thickness of 100 nm, and then MoW is formed by sputtering.
The first layer 28a of the gate wiring layer 28 is formed to a thickness of 50 nm and is once exposed to the atmosphere.
【００２２】図３（ニ）に示す様にスパッタリングに
よりＭｏＷにてゲート配線層２８の第２層２８ｂを３５
０ｎｍ形成した後、等方性ドライエッチングにより、第
１層２８ａをゲート絶縁膜２７との界面での配線幅ａが
５μｍ、第２層２８ｂとの界面での配線幅ｂが４．８μ
ｍの順テーパ状に加工し、第２層２８ｂを層間絶縁膜３
１との界面での配線幅ｃが６．２μｍの逆テーパ状に加
工してｃ＞ａ＞ｂとし、ＬＤＤ領域２６−２に対応する
領域においては第１層２８ａ及び第２層２８ｂによるゲ
ート配線層２８の合計層厚が２００ｎｍ以下となる様に
加工されている。この後、ゲート配線層２８をマスクに
して、半導体層２６のＬＤＤ領域２６−２、ソース領域
２６−３及びドレイン領域２６−４に同時に、自己活性
化条件を加速電圧５０ＫｅＶ、キャリア濃度５Ｅ１６／
cm2とし、リン（Ｐ＋）イオン・ドーピングを自己整合
的に行う。As shown in FIG. 3D, the second layer 28b of the gate wiring layer 28 is
After the formation of 0 nm, the wiring width a at the interface with the gate insulating film 27 is 5 μm and the wiring width b at the interface with the second layer 28b is 4.8 μm by isotropic dry etching.
m, and the second layer 28b is formed into an interlayer insulating film 3
In the region corresponding to the LDD region 26-2, the gate is formed by the first layer 28a and the second layer 28b in a reverse tapered shape having a wiring width c of 6.2 μm at the interface with the first layer 28a. The wiring layer 28 is processed so that the total layer thickness becomes 200 nm or less. After that, using the gate wiring layer 28 as a mask, the self-activation conditions are simultaneously applied to the LDD region 26-2, the source region 26-3, and the drain region 26-4 of the semiconductor layer 26 at an acceleration voltage of 50 KeV and a carrier concentration of 5E16 /
cm2 and phosphorus (P +) ion doping is performed in a self-aligned manner.
【００２３】図３（ホ）に示す様に、層間絶縁膜３１
を形成する。As shown in FIG. 3E, the interlayer insulating film 31
To form
【００２４】図３（ヘ）に示す様に、コンタクトホー
ル３３ａ、３４ａを形成する。As shown in FIG. 3F, contact holes 33a and 34a are formed.
【００２５】図３（ト）に示す様にソース電極３１、
ドレイン電極３２を形成し、ＴＦＴ１６を完成する。As shown in FIG. 3G, the source electrode 31,
The drain electrode 32 is formed, and the TFT 16 is completed.
【００２６】即ち、製造工程において、リン（Ｐ＋）
イオンの場合、加速電圧５０ＫｅＶでドーピングを行う
と、ＭｏＷのゲート配線層厚が２００ｎｍ以下に加工さ
れる領域にあっては、イオンがゲート配線層２８を突き
抜ける事から、半導体層２６のＬＤＤ領域２６−２にゲ
ート配線層２８を突き抜けたリン（Ｐ＋）イオンが打ち
込まれ、１度のイオン・ドーピングにてＬＤＤ領域２６
−２とソース領域２６−３及びドレイン領域２６−４と
が自動的に形成される事となる。That is, in the manufacturing process, phosphorus (P+ )
In the case of doping ions at an acceleration voltage of 50 KeV in the region where the gate wiring layer thickness of MoW is processed to 200 nm or less, the ions penetrate through the gate wiring layer 28, so that the LDD region 26 of the semiconductor layer 26 is formed. 2 is implanted with phosphorus (P +) ions penetrating the gate wiring layer 28, and the LDD region 26 is formed by one ion doping.
-2, the source region 26-3, and the drain region 26-4 are automatically formed.
【００２７】この様な製造工程にて形成されたＴＦＴ１
７の移動度及びしきい値電圧の面内ばらつきを１００点
測定した所、従来の製造工程にて形成されたＴＦＴの移
動度が２０〜１００cm2／Ｖｓ、しきい値電圧が１〜６
Ｖといずれもばらつきが大きかったのに比し、移動度は
１１０〜１３０cm2／Ｖｓと高く且つばらつきも非常に
小さく、しきい値電圧も２〜４Ｖと非常にばらつきが小
さく安定した特性を得られた。Ｂｉａｓ Ｔｅｍｐｅｒ
ａｔｕｒｅ Ｓｔｒｅｓｓ（以下ＢＴＳと略称する。）
試験では、ＴＦＴ１７のゲート−ソース間０Ｖバイア
ス、ドレイン−ソース間２０Ｖバイアス、９０℃、１０
０００秒の条件で前後の移動度、しきい値電圧を比較し
た所、１００個測定でいずれも移動度、しきい値電圧の
シフトは見られ無かった。又、液晶表示装置１６にあっ
ては、画面上に非表示部分が現れる事が無く、良好な表
示画像を得られた。The TFT 1 formed in such a manufacturing process
When 100 in-plane variations in the mobility and threshold voltage of the TFT No.7 were measured, the mobility of the TFT formed in the conventional manufacturing process was 20 to 100 cm2 / Vs, and the threshold voltage was 1 to 6
As compared with the case where both V and V have large variations, the mobility is as high as 110 to 130 cm2 / Vs, the variation is very small, and the threshold voltage is 2 to 4 V. Was done. Bias Temper
atsure Stress (hereinafter abbreviated as BTS)
In the test, the TFT 17 has a gate-source 0 V bias, a drain-source 20 V bias, 90 ° C., 10 ° C.
When the mobility and the threshold voltage before and after the condition of 000 seconds were compared, no shift of the mobility and the threshold voltage was observed in any of the 100 measurement. Further, in the liquid crystal display device 16, no non-display portion appeared on the screen, and a good display image was obtained.
【００２８】この様に構成すれば、ゲート配線層２８の
第１層２８ａ及び第２層２８ｂの、所望のＬＤＤ領域に
相当する部分を、夫々順テーパ状及び逆テーパ状に形成
し、ドーピング時、テーバ状部分にあっては、リン（Ｐ
＋）イオンのドーピング濃度を低下することにより、レ
ジストマスクを用いる事無く、１回のドーピング工程に
てＬＤＤ領域２６−２と、ソース領域２６−３及びドレ
イン領域２６−４とを同時に自己整合的にイオン・ドー
ピングでき、製造工程数を低減できる。これと共に、レ
ジストマスクの合わせずれ及びゲート配線層のサイドエ
ッチング量のばらつきにより従来生じていたＬＤＤ長の
ばらつきを生じることもなく、従来に比しＬＤＤ長をよ
り微細に制御可能であり所望のＬＤＤ長を容易に得ら
れ、ＴＦＴ１７は高移動度を得られると共に、移動度や
しきい値電圧のばらつきを生じる事無く安定した特性を
得られる。又この様に高移動度且つ特性の安定したなＴ
ＦＴ１７を用いた液晶表示装置１６は画面に非表示部分
を生じる事が無く良好な表示品位を得られ、大型のアク
ティブマトリクス型液晶表示装置への適用も可能とな
る。According to this structure, portions corresponding to desired LDD regions of the first layer 28a and the second layer 28b of the gate wiring layer 28 are formed in a forward tapered shape and a reverse tapered shape, respectively. , The tapered portion, phosphorus (P
+ ) By lowering the ion doping concentration, the LDD region 26-2 and the source region 26-3 and the drain region 26-4 can be simultaneously self-aligned in one doping step without using a resist mask. And the number of manufacturing steps can be reduced. At the same time, the LDD length can be controlled more finely than before, without causing the variation in the LDD length which has conventionally occurred due to the misalignment of the resist mask and the variation in the side etching amount of the gate wiring layer. The length can be easily obtained, and the TFT 17 can obtain high mobility, and can obtain stable characteristics without variations in mobility and threshold voltage. In addition, the high mobility and stable characteristics of T
The liquid crystal display device 16 using the FT 17 can obtain a good display quality without causing a non-display portion on a screen, and can be applied to a large active matrix liquid crystal display device.
【００２９】更にゲート配線層２８を２層構造とし、第
１層２８ａ及び２８ｂを夫々にテーパ形成する事によ
り、ＬＤＤ長の制御がより容易となる。Furthermore, the gate wiring layer 28 has a two-layer structure, and the first layers 28a and 28b are each tapered, so that the LDD length can be more easily controlled.
【００３０】尚本発明は上記実施の形態に限られるもの
でなく、その趣旨を変えない範囲での変更は可能であっ
て、例えば、テーパの角度は限定されず、実験から、順
テーパ及び逆テーパのいずれにおいても２０度〜５０度
の範囲で制御可能であるし、ゲート配線層の第１層のゲ
ート絶縁膜との界面での配線幅ａと、第２層の層間絶縁
膜との界面での配線幅ｃとの差（ｃ−ａ）も任意である
が、（ｃ−ａ）が２μｍより大きくなるとＴＦＴの移動
度が小さくなると共に加工性が悪くなる一方、ゲート−
ソース間０Ｖバイアス、ドレイン−ソース間２０Ｖバイ
アス、９０℃、１００００秒の条件でのＢＴＳ試験にお
いて、図４に示す様に、（ｃ−ａ）が０．２μｍ以上で
あれば、しきい値電圧シフトを生じないことから、０．
２μ≦（ａ−ｂ）≦２μｍである事がより好ましい。The present invention is not limited to the above embodiment, but can be changed without departing from the spirit of the present invention. For example, the taper angle is not limited. The taper can be controlled within the range of 20 to 50 degrees, and the width of the gate wiring layer at the interface with the first layer of the gate insulating film and the interface with the second layer of the interlayer insulating film can be controlled. The difference (c−a) from the wiring width c is arbitrary, but if (c−a) is larger than 2 μm, the mobility of the TFT decreases and the workability deteriorates.
In the BTS test under the conditions of 0V bias between source, 20V bias between drain and source, 90 ° C. and 10,000 seconds, as shown in FIG. 4, if (ca) is 0.2 μm or more, the threshold voltage Since no shift occurs, 0.
It is more preferable that 2 μ ≦ (ab) ≦ 2 μm.
【００３１】尚、ゲート配線層の第１層及び第２層の層
厚は、トータルとしてイオン・ドーピング時にチャネル
領域へのイオンの侵入をブロックできる範囲である一
方、工業的観点からは極力薄い方が望ましいが、ＴＦＴ
の特性に応じて設定される（ｃ−ａ）の値に従って決定
され、例えば、ゲート配線層の電極材料としてＭｏＷを
用い、フッ素（Ｆ）系のガスを用いたドライエッチング
にて形成する場合、テーパ角度を３０度の条件でエッチ
ングするとして、（ｃ−ａ）の値を１．２μｍとしよう
とすると、第１層の層厚５０ｎｍ、第２層の層厚３５０
ｎｍとすれば良い。一般的には第１層の層厚を薄くする
一方、第１層及び第２層の層厚差が２００ｎｍ以下では
ＬＤＤ長が小さく成り過ぎる半面、層厚差が５００ｎｍ
以上では逆テーパ部を層間絶縁膜にてい被覆するのが難
しくなる事から、層厚差は、２００〜５００ｎｍ程度と
するのがより好ましい。The thickness of the first layer and the second layer of the gate wiring layer is within a range capable of blocking intrusion of ions into the channel region at the time of ion doping, but is as thin as possible from an industrial viewpoint. Is desirable, but TFT
Is determined according to the value of (ca) set in accordance with the characteristics of, for example, when the gate wiring layer is formed by dry etching using fluorine (F) -based gas using MoW as an electrode material, Assuming that the etching is performed under the condition that the taper angle is 30 degrees and the value of (ca) is set to 1.2 μm, the thickness of the first layer is 50 nm and the thickness of the second layer is 350 nm.
nm. Generally, while the thickness of the first layer is reduced, if the thickness difference between the first layer and the second layer is 200 nm or less, the LDD length is too small, but the thickness difference is 500 nm.
Above, the reverse taper portion is covered with the interlayer insulating film, which makes it difficult to cover. Therefore, the difference in layer thickness is more preferably about 200 to 500 nm.
【００３２】又、半導体層にイオン・ドーピングする際
の自己活性化条件等も、ＬＤＤ領域及びソース・ドレイ
ン領域を同時に形成できるよう、ゲート配線層のテーバ
部分をイオンが透過できる範囲であれば任意である。The conditions for self-activation when doping the semiconductor layer with ions are not limited as long as ions can pass through the tapered portion of the gate wiring layer so that the LDD region and the source / drain regions can be formed simultaneously. It is.
【００３３】[0033]
【発明の効果】以上説明したように本発明によれば、ト
ップゲートｎ型のＴＦＴにおいて、２層構造を有するゲ
ート配線層の第１層を順テーパ形状とし、第２層を逆テ
ーパ形状とすることにより、半導体層上に、レジストマ
スクを用いる事無く１回のドーピング工程にて、ＬＤＤ
領域及び、ソース・ドレイン領域を同時に自己整合的に
イオン・ドーピングでき、製造工程数の低減を図れると
共に、ＬＤＤ長のばらつきを生じることもなく、従来に
比しＬＤＤ長をより微細に制御可能であり所望のＬＤＤ
長を容易に得られ、移動度の低下やばらつき、あるいは
しきい値電圧のばらつきの無い、特性の安定したＴＦＴ
を容易に得られる。更にこの様に高移動度且つ安定した
特性を有するＴＦＴを液晶表示装置の駆動素子として用
いる事により、液晶表示装置にあっては良好な表示品位
を得られ、大型のアクティブマトリクス型液晶表示装置
への適用も可能となる。As described above, according to the present invention, in a top gate n-type TFT, the first layer of the gate wiring layer having a two-layer structure has a forward tapered shape, and the second layer has an inverted tapered shape. By doing so, the LDD can be performed on the semiconductor layer in one doping step without using a resist mask.
The region and the source / drain regions can be simultaneously ion-doped in a self-aligned manner, so that the number of manufacturing steps can be reduced, and the LDD length can be more finely controlled as compared with the related art without causing variations in the LDD length. The desired LDD
TFTs with stable characteristics that can easily obtain a length and have no decrease or variation in mobility or variation in threshold voltage
Is easily obtained. Further, by using a TFT having such high mobility and stable characteristics as a driving element of a liquid crystal display device, a good display quality can be obtained in the liquid crystal display device, and a large active matrix liquid crystal display device can be obtained. Can also be applied.
【図１】本発明の実施の形態の液晶表示装置を示す概略
断面図である。FIG. 1 is a schematic sectional view showing a liquid crystal display device according to an embodiment of the present invention.
【図２】本発明の実施の形態のＴＦＴを示す概略断面図
である。FIG. 2 is a schematic sectional view showing a TFT according to an embodiment of the present invention.
【図３】本発明の実施の形態のＴＦＴの製造工程を示
し、（イ）はそのアモルファスシリコン膜の結晶化時、
（ロ）はポリシリコン膜のパターニング時、（ハ）は第
１層形成時、（ニ）はテーパ形成後のゲート配線層を用
いたイオン・ドーピング時、（ホ）は層間絶縁膜形成
時、（ヘ）はコンタクトホール形成時、（ト）はソース
電極、ドレイン電極形成時を示す概略説明図である。FIG. 3 shows a manufacturing process of the TFT according to the embodiment of the present invention.
(B) at the time of patterning the polysilicon film, (c) at the time of forming the first layer, (d) at the time of ion doping using the gate wiring layer after taper formation, (e) at the time of forming the interlayer insulating film, (F) is a schematic explanatory view showing the time of forming a contact hole, and (g) is a schematic explanatory view showing the time of forming a source electrode and a drain electrode.
【図４】本発明によるＴＦＴのゲート配線層の（ｃ−
ａ）の値に対するしきい値電圧シフト量を示すグラフで
ある。FIG. 4 shows (c-
5 is a graph showing a threshold voltage shift amount with respect to the value of a).
【図５】従来のＴＦＴの製造工程を示し、（イ）はその
ポリシリコン膜のパターニング時、（ロ）はＬＤＤ領域
形成時、（ハ）はソース・ドレイン領域形成時を示す概
略説明図である。FIG. 5 is a schematic explanatory view showing a conventional TFT manufacturing process, in which (a) shows the patterning of the polysilicon film, (b) shows the LDD region formation, and (c) shows the source / drain region formation. is there.
１６…液晶表示装置 １７…ＴＦＴ １８…アレイ基板 １９…対向基板 ２１…液晶組成物 ２６…半導体層 ２６−１…チャネル領域 ２６−２…ＬＤＤ領域 ２６−３…ソース領域 ２６−４…ドレイン領域 ２８…ゲート配線層 ２８ａ…第１層 ２８ｂ…第２層 ３２…画素電極 ３３…ドレイン電極 ３４…ソース電極 Reference Signs List 16 liquid crystal display device 17 TFT 18 array substrate 19 counter substrate 21 liquid crystal composition 26 semiconductor layer 26-1 channel region 26-2 LDD region 26-3 source region 26-4 drain region 28 ... Gate wiring layer 28a First layer 28b Second layer 32 Pixel electrode 33 Drain electrode 34 Source electrode
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9037805AJPH10233511A (en) | 1997-02-21 | 1997-02-21 | Thin film transistor device, method of manufacturing thin film transistor device, and liquid crystal display device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9037805AJPH10233511A (en) | 1997-02-21 | 1997-02-21 | Thin film transistor device, method of manufacturing thin film transistor device, and liquid crystal display device |
| Publication Number | Publication Date |
|---|---|
| JPH10233511Atrue JPH10233511A (en) | 1998-09-02 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9037805APendingJPH10233511A (en) | 1997-02-21 | 1997-02-21 | Thin film transistor device, method of manufacturing thin film transistor device, and liquid crystal display device |
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| JP (1) | JPH10233511A (en) |
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