【０００１】[0001]
【発明の属する技術分野】本発明は、電子部品の能動素
子面を基板の電極面に向け、上記電子部品の上記能動素
子面に形成されたはんだバンプを上記基板の上記電極に
直接接続するフリップチップ接続をなす電子部品実装方
法および電子部品実装装置に関する。The present invention relates to a flip for directly connecting an active element surface of an electronic component to an electrode surface of a substrate and directly connecting a solder bump formed on the active element surface of the electronic component to the electrode of the substrate. The present invention relates to an electronic component mounting method and an electronic component mounting device for making a chip connection.
【０００２】[0002]
【従来の技術】半導体チップなどの電子部品を基板に実
装するのにあたって、従来、図５（Ａ）に示すような、
いわゆるフリップチップ接続方法が用いられる。これ
は、電子部品である、たとえば半導体チップａの電極ｂ
に、突起状に形成されるはんだバンプｃが設けられてい
る。2. Description of the Related Art In mounting an electronic component such as a semiconductor chip on a substrate, conventionally, as shown in FIG.
A so-called flip-chip connection method is used. This is an electronic component, for example, an electrode b of a semiconductor chip a.
Is provided with a solder bump c formed in a projection shape.
【０００３】このようなはんだバンプｃ付きの半導体チ
ップａが基板Ｄ上に搭載される。すなわち、基板Ｄに形
成される電極ｅに半導体チップａの電極ｂに設けられる
はんだバンプｃが載る。そして、リフロを行うことによ
り、はんだバンプｃを介して半導体チップａと基板電極
ｅとの接続が行なわれるものである。A semiconductor chip a having such a solder bump c is mounted on a substrate D. That is, the solder bump c provided on the electrode b of the semiconductor chip a is placed on the electrode e formed on the substrate D. Then, by performing the reflow, the connection between the semiconductor chip a and the substrate electrode e is performed via the solder bump c.
【０００４】[0004]
【発明が解決しようとする課題】このような基板Ｄと半
導体チップａとの接続をはんだバンプｃのみを介して行
うフリップチップ実装をなした電子製品では、その電子
製品の動作時に、半導体チップａの発熱で、基板Ｄと半
導体チップａの熱膨張の差にともないはんだバンプｃが
熱応力を受ける。In an electronic product mounted by flip-chip in which the connection between the substrate D and the semiconductor chip a is performed only through the solder bump c, the semiconductor chip a , The solder bump c receives thermal stress due to the difference in thermal expansion between the substrate D and the semiconductor chip a.
【０００５】ところが上記はんだバンプｃは、接続時に
はんだバンプ素材が表面張力によって、その周面が丸く
膨出する。いわゆる太鼓状になり、半導体チップａと基
板Ｄに形成される電極ｂ，ｅとはんだバンプｃ周面との
なす接触角Ｒａが、同図（Ｂ）に示すように大きくな
る。However, the peripheral surface of the solder bump c bulges out due to the surface tension of the solder bump material during connection. It becomes a so-called drum shape, and the contact angle Ra between the semiconductor chip a, the electrodes b and e formed on the substrate D, and the peripheral surface of the solder bump c increases as shown in FIG.
【０００６】それにともなって、動作時の発熱によりは
んだバンプｃの接触角Ｒａの部分に熱応力が集中し、上
記はんだバンプｃが受ける熱応力が大きくなってしま
う。電子製品の動作ごとにこの状態が繰返されることに
なり、よってはんだバンプｃにおける熱疲労が原因とな
り、破断に至る恐れがあり、信頼性に乏しいという問題
がある。Accordingly, heat stress is concentrated on the portion of the solder bump c at the contact angle Ra due to heat generated during operation, and the thermal stress applied to the solder bump c increases. This state is repeated for each operation of the electronic product, and therefore, there is a problem that the solder bump c may be broken due to thermal fatigue, resulting in poor reliability.
【０００７】本発明は、上述した事情に鑑みてなされた
ものであり、その目的とするところは、電子部品の能動
素子面を基板の電極面に向け、電子部品の能動素子面に
形成されたはんだバンプを基板の電極に接続するフリッ
プチップ接続をなすものにおいて、半導体チップと基板
に形成される電極とはんだバンプ周面とのなす接触角を
小さくして、動作時にはんだバンプの受ける熱応力の低
減を図り、よって信頼性の向上を得られる電子部品実装
方法および電子部品実装装置を提供しようとするもので
ある。The present invention has been made in view of the above circumstances, and an object of the present invention is to form an active element surface of an electronic component with the active element surface of the electronic component facing the electrode surface of the substrate. In the flip-chip connection that connects the solder bumps to the electrodes on the substrate, the contact angle between the semiconductor chip and the electrodes formed on the substrate and the peripheral surface of the solder bumps is reduced to reduce the thermal stress applied to the solder bumps during operation. It is an object of the present invention to provide an electronic component mounting method and an electronic component mounting device that can reduce the number of components and thereby improve the reliability.
【０００８】[0008]
【課題を解決するための手段】上記目的を満足するた
め、第１の発明における電子部品実装方法は、請求項１
として、電子部品の能動素子面を基板の電極面に向け、
上記電子部品の上記能動素子面に形成されたはんだバン
プを上記基板の上記電極に接続するフリップチップ接続
をなす電子部品実装方法において、基板をその電極面を
下方に向けるとともに電子部品の能動素子面を上方に向
けて互いに対向位置させる工程と、この工程のあとに、
上記基板のみを支持し、上記電子部品を上記基板に押し
上げ、はんだバンプを上記電極に接触させてリフロをな
し、このリフロ中にはんだバンプを介して電子部品を基
板に吊り下げ、電子部品の自重によってはんだバンプを
引き伸ばす工程とを具備したことを特徴とする。In order to satisfy the above-mentioned object, an electronic component mounting method according to a first aspect of the present invention is described in claim 1.
As the active element surface of the electronic component faces the electrode surface of the substrate,
An electronic component mounting method for making a flip-chip connection by connecting a solder bump formed on the active element surface of the electronic component to the electrode of the substrate, wherein the substrate has its electrode surface facing downward and the active element surface of the electronic component is , Facing upwards, and after this step,
Only the substrate is supported, the electronic component is pushed up to the substrate, the solder bumps are brought into contact with the electrodes to perform reflow, the electronic components are suspended on the substrate via the solder bumps during the reflow, and the weight of the electronic component is reduced. And elongating the solder bumps.
【０００９】上記目的を満足するため、第２の発明にお
ける電子部品実装方法は、請求項２として、電子部品の
能動素子面を基板の電極面に向け、上記電子部品の能動
素子面に形成されたはんだバンプを上記基板の上記電極
に接続するフリップチップ接続をなす電子部品実装方法
において、基板をその電極面を下方に向けるとともに電
子部品の能動素子面を上方に向けて互いに対向位置させ
る工程と、この工程のあとに、上記基板のみを支持し、
上記電子部品を押し下げてはんだバンプを上記電極に接
触させてリフロをなす第１のリフロ工程と、上記はんだ
バンプを介して接続される上記基板と上記電子部品を上
下反転する工程と、上記基板のみを支持してリフロをな
し、このリフロ中に上記はんだバンプを介して電子部品
を基板に吊り下げ、電子部品の自重によってはんだバン
プを引き伸ばす第２のリフロ工程とを具備したことを特
徴とする。According to a second aspect of the present invention, there is provided a method of mounting an electronic component, wherein the active element surface of the electronic component is formed on the active element surface of the electronic component with the active element surface facing the electrode surface of the substrate. In the electronic component mounting method of making a flip-chip connection connecting the solder bumps to the electrodes of the substrate, a step of facing the substrate with its electrode surface facing downward and the active element surface of the electronic component facing upward, , After this step, support only the substrate,
A first reflow process in which the electronic component is pressed down to bring the solder bumps into contact with the electrodes to perform reflow, a process in which the substrate and the electronic component connected via the solder bumps are turned upside down, And a second reflow process in which the electronic component is suspended from the substrate via the solder bumps during the reflow, and the solder bump is stretched by the weight of the electronic component.
【００１０】上記目的を満足するため、第３の発明にお
ける電子部品実装装置は、請求項３として、電子部品の
能動素子面を基板の電極面に向け、上記電子部品の上記
能動素子面に形成されたはんだバンプを上記基板の上記
電極に接続するフリップチップ接続をなす電子部品実装
装置において、上記基板をその電極面を下方に向けて保
持する基板保持機構と、上記電子部品を基板の下部に対
向配置させ、その能動素子面を上方に向け、上記電子部
品を押し上げて上記はんだバンプを上記電極に接触させ
る電子部品保持機構とを具備し、この電子部品保持機構
は、上記電極に接触したはんだパンプのリフロをなす間
は上記電子部品から離間することを特徴とする。According to a third aspect of the present invention, there is provided an electronic component mounting apparatus according to a third aspect of the present invention, wherein an active element surface of an electronic component faces an electrode surface of a substrate and is formed on the active element surface of the electronic component. An electronic component mounting apparatus that performs flip-chip connection that connects the solder bumps to the electrodes of the substrate, a substrate holding mechanism that holds the substrate with its electrode surface facing downward, and that the electronic component is mounted on a lower portion of the substrate. And an electronic component holding mechanism that pushes up the electronic component to bring the solder bump into contact with the electrode, wherein the electronic component holding mechanism includes a solder contacting the electrode. The pump is separated from the electronic component during the reflow of the pump.
【００１１】上記目的を満足するため、第４の発明にお
ける電子部品実装装置は、請求項４として、電子部品の
能動素子面を基板の電極面に向け、上記電子部品の能動
素子面に形成されたはんだバンプを上記基板の上記電極
に直接接続するフリップチップ接続をなす電子部品実装
装置において、基板をその電極面を上方に向けて支持す
る基板支持台と、この基板支持台上に載置され基板に対
して、電子部品の能動素子面を上記基板に向けて搬送
し、電子部品に形成されるはんだバンプを上記基板電極
に接触させるように駆動する電子部品搬送機構と、上記
はんだバンプを介して接続される上記基板と上記電子部
品を上下反転し基板を保持する基板保持機構と、上記電
子部品を基板の下部に対向配置させ、その能動素子面を
上方に向け、上記電子部品を押し上げて上記はんだバン
プを上記電極に接触させる電子部品保持機構とを具備
し、この電子部品保持機構は、上記電極に接触したはん
だパンプのリフロをなす間は上記電子部品から離間する
ことを特徴とする。According to a fourth aspect of the present invention, there is provided an electronic component mounting apparatus formed on the active element surface of the electronic component with the active element surface of the electronic component facing the electrode surface of the substrate. An electronic component mounting apparatus that performs flip-chip connection by directly connecting the solder bumps to the electrodes of the substrate, a substrate support that supports the substrate with its electrode surface facing upward, and mounted on the substrate support. An electronic component transport mechanism that transports the active element surface of the electronic component toward the substrate with respect to the substrate and drives a solder bump formed on the electronic component to contact the substrate electrode, and via the solder bump A board holding mechanism for holding the board by turning the board and the electronic component upside down and connecting the electronic component to a lower portion of the board with the active element surface facing upward; An electronic component holding mechanism for pushing up the component and bringing the solder bump into contact with the electrode, wherein the electronic component holding mechanism separates from the electronic component while performing reflow of the solder pump in contact with the electrode. Features.
【００１２】上記目的を満足するため、第５の発明にお
ける電子部品実装方法および電子部品実装装置は、請求
項５として、請求項１ないし請求項４記載の上記はんだ
バンプは、低融点金属であり、フリップチップ接続後の
上記基板と上記電子部品とのギャップが、上記電子部品
の電極および基板の電極の所定の一辺よりも大であるこ
とを特徴とする。According to a fifth aspect of the present invention, there is provided an electronic component mounting method and an electronic component mounting apparatus according to the fifth aspect, wherein the solder bump according to any one of the first to fourth aspects is a low melting point metal. The gap between the substrate and the electronic component after flip-chip connection is larger than a predetermined side of an electrode of the electronic component and a predetermined side of an electrode of the substrate.
【００１３】上記のような請求項１ないし請求項５記載
の発明にもとづく課題を解決する手段を備えることによ
り、半導体チップと基板に形成される電極とはんだバン
プ周面とのなす接触角を小さくして、動作時にはんだバ
ンプの受ける熱応力の低減を図れる。By providing the means for solving the problems based on the inventions according to the first to fifth aspects, the contact angle between the electrode formed on the semiconductor chip and the substrate and the peripheral surface of the solder bump can be reduced. Thus, the thermal stress applied to the solder bump during operation can be reduced.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照して説明する。図１に、電子部品である半導体チ
ップ１を能動素子面を下向きにしたはんだバンプ２を介
して基板３の電極４に直接接続するフリップチップ接続
をなした状態を示す。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a state in which a semiconductor chip 1 as an electronic component is flip-chip connected to be directly connected to an electrode 4 of a substrate 3 via a solder bump 2 with an active element surface facing downward.
【００１５】後述するように、はんだバンプ２は、半導
体チップ１と基板３の電極５，４に対する接触角が小さ
くなるように形成される。図２（Ａ），（Ｂ）に、半導
体チップ１を基板３に実装する工程を示す。As will be described later, the solder bumps 2 are formed so that the contact angle between the semiconductor chip 1 and the electrodes 3 of the substrate 3 becomes small. FIGS. 2A and 2B show a process of mounting the semiconductor chip 1 on the substrate 3.
【００１６】はじめに、同図（Ａ）に示すように、基板
３を基板保持機構６に保持する。上記基板３は、この基
板３に形成される電極４を下方に向けられており、少な
くとも半導体チップ１が接続される部位は保持されな
い。First, the substrate 3 is held by the substrate holding mechanism 6 as shown in FIG. The substrate 3 faces the electrode 4 formed on the substrate 3 downward, and at least a portion to which the semiconductor chip 1 is connected is not held.
【００１７】半導体チップ１は、電子部品保持機構７に
保持される。上記半導体チップ１は基板３に対して、こ
の下部に位置するとともに能動素子面である電極５面を
上方に向け、互いに対向配置される。The semiconductor chip 1 is held by an electronic component holding mechanism 7. The semiconductor chips 1 are located below the substrate 3 and opposed to each other with the electrodes 5 as active element surfaces facing upward.
【００１８】半導体チップ１の電極５にはすでにはんだ
バンプ２が設けられている。そして、それぞれのはんだ
バンプ２が接続すべき基板３の電極に正しく対向する、
正確な位置合わせがなされていることは言うまでもな
い。The solder bumps 2 are already provided on the electrodes 5 of the semiconductor chip 1. Then, each solder bump 2 correctly faces an electrode of the substrate 3 to be connected,
Needless to say, accurate alignment is performed.
【００１９】電子部品保持機構７は半導体チップ１を押
し上げてはんだバンプ２を上記基板電極４に接触させ、
そのまま半導体チップ１を保持する。そして、この状態
で基板３と半導体チップ１の双方を同時にリフロする。The electronic component holding mechanism 7 pushes up the semiconductor chip 1 to bring the solder bumps 2 into contact with the substrate electrodes 4,
The semiconductor chip 1 is held as it is. Then, in this state, both the substrate 3 and the semiconductor chip 1 are simultaneously reflowed.
【００２０】つぎに、同図（Ｂ）に示すように、はんだ
バンプ２が溶融し始めるタイミングをとって、上記電子
部品保持機構７は所定寸法だけ降下し、その位置を保持
する。これにより、溶融しているはんだバンプ２に対し
て半導体チップ１の自重がかかる。半導体チップ１の自
重に応じてはんだバンプ２に表面張力が作用し、電子部
品保持機構７が半導体チップ１から離間しても、半導体
チップ１は基板３から脱落することがない。Next, as shown in FIG. 2B, at the timing when the solder bumps 2 begin to melt, the electronic component holding mechanism 7 descends by a predetermined dimension and holds its position. As a result, the weight of the semiconductor chip 1 is applied to the molten solder bump 2. The surface tension acts on the solder bumps 2 according to the weight of the semiconductor chip 1, and the semiconductor chip 1 does not fall off the substrate 3 even when the electronic component holding mechanism 7 is separated from the semiconductor chip 1.
【００２１】所定時間が経過するとリフロの終了とな
り、はんだバンプ２は硬化する。したがって、はんだバ
ンプ２を介して半導体チップ１と基板電極４との接続が
行なわれる。When a predetermined time has elapsed, reflow is completed, and the solder bumps 2 are hardened. Therefore, connection between semiconductor chip 1 and substrate electrode 4 is performed via solder bump 2.
【００２２】なお、上述したように、リフロ中にはんだ
バンプ２に半導体チップ１の自重がかかるところから、
はんだバンプ２に表面張力が作用して、これは引き伸ば
された状態で硬化する。As described above, the weight of the semiconductor chip 1 is applied to the solder bumps 2 during reflow.
The surface tension acts on the solder bumps 2, which are hardened in a stretched state.
【００２３】すなわち、図４（Ａ）に示すように、上記
はんだバンプ２は、低融点金属であり、フリップチップ
接続後のはんだバンプ２の高さである上記基板電極４と
上記半導体チップ電極５とのギャップ（間隔寸法）ｌａ
が、図５に示すように、正方形をなす基板電極４および
半導体チップ電極５の一辺寸法ｌｂよりも大（ｌａ＞ｌ
ｂ）となる。That is, as shown in FIG. 4A, the solder bump 2 is made of a low-melting metal, and the substrate electrode 4 and the semiconductor chip electrode 5 have the height of the solder bump 2 after flip-chip connection. Gap (interval dimension) la
However, as shown in FIG. 5, larger than one side dimension lb (la> l) of the square substrate electrode 4 and the semiconductor chip electrode 5 as shown in FIG.
b).
【００２４】なお、図６に示すように、上記基板電極４
および半導体チップ電極５が長方形をなす場合がある。
このときの長辺をｙ，短辺をｘとすると、ｌａ＞ｙの関
係となる。Note that, as shown in FIG.
In some cases, the semiconductor chip electrode 5 has a rectangular shape.
If the long side is y and the short side is x at this time, the relationship is la> y.
【００２５】この状態で、各電極４，５に対するはんだ
バンプ２の接触角Ｒｂが、従来の接触角Ｒａよりも小
（Ｒｂ＜Ｒａ）となる。したがって、このようなフリッ
プチップ実装をなした電子製品では、その電子製品の動
作時に、半導体チップ１の発熱で、基板３と半導体チッ
プ１の熱膨張の差にともないはんだバンプ２が熱応力を
受けるが、接触角Ｒｂが小であるので、はんだバンプ２
が受ける熱応力の集中が緩和され、小さくてすむ。In this state, the contact angle Rb of the solder bump 2 with respect to each of the electrodes 4 and 5 is smaller than the conventional contact angle Ra (Rb <Ra). Therefore, in an electronic product mounted in such a flip-chip manner, during operation of the electronic product, heat generated by the semiconductor chip 1 causes the solder bumps 2 to receive thermal stress due to a difference in thermal expansion between the substrate 3 and the semiconductor chip 1. However, since the contact angle Rb is small, the solder bump 2
The concentration of thermal stress applied to the substrate is alleviated, and the size is reduced.
【００２６】電子製品の動作ごとにこの状態が繰返され
るが、はんだバンプ２における熱疲労が原因となって破
断に至るような不具合を低減できる。図４（Ｂ）は、半
導体チップ１の自重の差により、基板電極４と半導体チ
ップ電極５とのギャップ（間隔寸法）ｌｃが、基板電極
４および半導体チップ電極５の一辺寸法ｌｂよりも大
（ｌｃ＞ｌｂ）となることは勿論、同図（Ａ）の電極相
互４，５間のギャップｌａよりも大（ｌｃ＞ｌａ＞ｌ
ｂ）となる。This state is repeated for each operation of the electronic product. However, it is possible to reduce defects such as breakage due to thermal fatigue of the solder bumps 2. FIG. 4B shows that the gap (interval dimension) lc between the substrate electrode 4 and the semiconductor chip electrode 5 is larger than one side dimension lb of the substrate electrode 4 and the semiconductor chip electrode 5 due to the difference in the weight of the semiconductor chip 1 (FIG. 4B). lc> lb), of course, larger than the gap la between the electrodes 4 and 5 (lc>la> l) in FIG.
b).
【００２７】したがって、はんだバンプ２の形状がほぼ
逆太鼓状（いわば、鼓状）となり、各電極４，５に対す
るはんだバンプ２の接触角Ｒｃが従来の接触角Ｒａより
も小（Ｒｃ＜Ｒａ）となる。はんだバンプ２が受ける熱
応力の集中がさらに緩和されて小さくてすみ、はんだバ
ンプ２における熱疲労が原因となって破断に至るような
不具合がない。Therefore, the shape of the solder bump 2 is substantially inverted drum-shaped (so-called drum-shaped), and the contact angle Rc of the solder bump 2 with respect to each of the electrodes 4 and 5 is smaller than the conventional contact angle Ra (Rc <Ra). Becomes The concentration of the thermal stress applied to the solder bumps 2 is further reduced, and the solder bumps 2 can be small, and there is no problem that the solder bumps 2 are broken due to thermal fatigue.
【００２８】図３（Ａ）〜（Ｄ）は、第２の実施の形態
を示したものである。はじめの工程として、同図（Ａ）
では、基板支持台８で基板１を支持する。基板１に設け
られる電極４面は上方に向けられる。一方、電子部品で
ある半導体チップ１は、電子部品搬送機構である吸着ノ
ズル９に吸着保持されて基板３の上方部位にあり、その
能動素子面は下方に向けられる。FIGS. 3A to 3D show a second embodiment. As the first step, FIG.
Then, the substrate 1 is supported by the substrate support 8. The surface of the electrode 4 provided on the substrate 1 is directed upward. On the other hand, the semiconductor chip 1 as an electronic component is sucked and held by a suction nozzle 9 as an electronic component transport mechanism and is located above the substrate 3, and its active element surface faces downward.
【００２９】そして、同図（Ｂ）に示すように、上記半
導体チップ１は押し下げられ、既にこの電極５面に形成
されるはんだバンプ２を基板電極４に接触させる。そし
てこの状態を保持したままリフロ（第１のリフロ工程）
が行われる。これにより、上記はんだバンプ２は溶融
し、このはんだバンプ２を介して基板電極４と半導体チ
ップ電極５が接続される。Then, as shown in FIG. 1B, the semiconductor chip 1 is pushed down, and the solder bumps 2 already formed on the surfaces of the electrodes 5 are brought into contact with the substrate electrodes 4. Then, while maintaining this state, reflow (first reflow step)
Is performed. Thereby, the solder bump 2 is melted, and the substrate electrode 4 and the semiconductor chip electrode 5 are connected via the solder bump 2.
【００３０】第１のリフロ工程の終了後の、同図（Ｂ）
から同図（Ｃ）に至る間に、上記基板３と上記半導体チ
ップ１とが上下反転させられる。したがって、半導体チ
ップ１の能動素子面が上方に向けられ、基板３の電極４
面は下方に向けられる。FIG. 4B after the completion of the first reflow step.
The substrate 3 and the semiconductor chip 1 are turned upside down from FIG. Therefore, the active element surface of the semiconductor chip 1 is directed upward, and the electrode 4
The face is turned downward.
【００３１】同図（Ｃ）に示すように、基板３は基板保
持機構６で支持され、半導体チップ１は電子部品保持機
構７で保持される。そして、電子部品保持機構７は半導
体チップ１を押し上げて、はんだバンプ２を基板電極４
に押し付けた状態とし、そのままリフロ（第２のリフロ
工程）が行われる。As shown in FIG. 1C, the substrate 3 is supported by a substrate holding mechanism 6, and the semiconductor chip 1 is held by an electronic component holding mechanism 7. Then, the electronic component holding mechanism 7 pushes up the semiconductor chip 1 and attaches the solder bump 2 to the substrate electrode 4.
And the reflow (second reflow step) is performed as it is.
【００３２】この第２のリフロ工程中に、電子部品保持
機構７ははんだバンプ２が溶融したことにもとづいて所
定寸法だけ降下し、その位置を保持する。これにより、
溶融しているはんだバンプ２に対して半導体チップ１の
自重がかかり、この半導体チップ１の自重に応じてはん
だバンプ２に表面張力が作用し、基板３から脱落するこ
とがない。During the second reflow process, the electronic component holding mechanism 7 is lowered by a predetermined size based on the fact that the solder bump 2 is melted, and holds the position. This allows
The weight of the semiconductor chip 1 is applied to the molten solder bump 2, and the surface tension acts on the solder bump 2 according to the weight of the semiconductor chip 1, so that the semiconductor chip 1 does not fall off the substrate 3.
【００３３】所定時間が経過してリフロが終了し、はん
だバンプ２は硬化する。したがって、はんだバンプ２を
介して半導体チップ１と基板電極４との接続が行なわれ
る。ここでも、上記はんだバンプ２を介して半導体チッ
プ１を基板３に対して吊り下げ、半導体チップ１の自重
によってはんだバンプ２を引き伸ばすこととなり、先に
図４（Ａ），（Ｂ）に示したようにはんだバンプ２と各
電極４，５との接触角Ｒｂ，Ｒｃがごく小さくなる。そ
の結果、はんだバンプ２におけるせん断歪みが小さくな
り、熱応力自体も小さくなり、はんだバンプ２が受ける
熱応力の集中が緩和され、破断に至るまでの寿命が延び
る。After a predetermined time has elapsed, the reflow is completed, and the solder bump 2 is hardened. Therefore, connection between semiconductor chip 1 and substrate electrode 4 is performed via solder bump 2. Also in this case, the semiconductor chip 1 is hung from the substrate 3 via the solder bumps 2, and the solder bumps 2 are stretched by the weight of the semiconductor chip 1, as shown in FIGS. 4A and 4B. As described above, the contact angles Rb and Rc between the solder bump 2 and each of the electrodes 4 and 5 become extremely small. As a result, the shear strain in the solder bump 2 is reduced, the thermal stress itself is reduced, the concentration of the thermal stress applied to the solder bump 2 is relaxed, and the life until fracture is extended.
【００３４】[0034]
【発明の効果】以上述べたように、請求項１の発明によ
れば、基板電極面を下方に向け電子部品の能動素子面を
上方に向けて互いに対向位置させる工程と、基板のみを
支持し、電子部品を基板に押し上げ、はんだバンプを電
極に接触させてリフロをなし、リフロ中にはんだバンプ
を介して電子部品を基板に吊り下げ、電子部品の自重に
よってはんだバンプを引き伸ばす工程とを具備した電子
部品実装方法である。As described above, according to the first aspect of the present invention, the step of facing the substrate with the electrode surface facing downward and the active element surface of the electronic component facing upward, and supporting only the substrate. Pushing up the electronic component to the substrate, making the solder bumps contact the electrodes to form a reflow, suspending the electronic component to the substrate via the solder bumps during the reflow, and stretching the solder bumps by the weight of the electronic component. This is an electronic component mounting method.
【００３５】請求項２の発明によれば、基板電極面を下
方に向け電子部品の能動素子面を上方に向けて互いに対
向位置させる工程と、基板のみ支持し、電子部品を押し
下げてはんだバンプを電極に接触させてリフロをなす第
１のリフロ工程と、はんだバンプを介して接続される基
板と電子部品を上下反転する工程と、基板のみを支持し
てリフロをなし、このリフロ中にはんだバンプを介して
電子部品を基板に吊り下げ、電子部品の自重によっては
んだバンプを引き伸ばす第２のリフロ工程とを具備した
ことを特徴とする電子部品実装方法である。According to the second aspect of the present invention, the step of facing the substrate with the electrode surface facing downward and the active element surface of the electronic component facing upward, and supporting only the substrate and pushing down the electronic component to reduce the solder bumps. A first reflow process of making reflow by contacting the electrodes, a process of inverting a substrate and an electronic component which are connected via solder bumps, and a process of reflowing by supporting only the substrate; A second reflow step of suspending the electronic component from the substrate via the substrate and stretching the solder bumps by the weight of the electronic component.
【００３６】請求項３の発明によれば、基板の電極面を
下方に向けて保持する基板保持機構と、電子部品を基板
の下部に対向配置させ、その能動素子面を上方に向け、
電子部品を押し上げてはんだバンプを電極に接触させ、
はんだパンプのリフロをなす間は電子部品から離間する
電子部品保持機構とを具備したことを特徴とする電子部
品実装装置である。According to the third aspect of the present invention, a substrate holding mechanism for holding the electrode surface of the substrate downward, and an electronic component disposed opposite to the lower portion of the substrate, with its active element surface facing upward,
Push up the electronic components to bring the solder bumps into contact with the electrodes,
An electronic component mounting apparatus comprising: an electronic component holding mechanism that separates from an electronic component during reflow of a solder pump.
【００３７】請求項４の発明によれば、基板の電極面を
上方に向けて支持する基板支持台、基板支持台上に載置
され基板に対し電子部品の能動素子面を基板に向けて搬
送し、電子部品のはんだバンプを基板電極に接触させる
ように駆動する電子部品搬送機構、基板と電子部品を上
下反転し基板を保持する基板保持機構、電子部品を基板
の下部に対向配置しかつ能動素子面を上方に向け、電子
部品を押し上げてはんだバンプを電極に接触させる電子
部品保持機構とを具備し、電子部品保持機構は、電極に
接触したはんだパンプのリフロをなす間は電子部品から
離間することを特徴とする電子部品実装装置である。According to the fourth aspect of the present invention, a substrate support for supporting the electrode surface of the substrate upward, and the active element surface of the electronic component mounted on the substrate support and transported toward the substrate with respect to the substrate. An electronic component transport mechanism that drives the solder bumps of the electronic components to contact the substrate electrodes, a substrate holding mechanism that turns the substrate and the electronic components upside down to hold the substrate, An electronic component holding mechanism that pushes up the electronic component and pushes up the electronic component to bring the solder bumps into contact with the electrodes.The electronic component holding mechanism is separated from the electronic components while reflowing the solder pump in contact with the electrodes. An electronic component mounting apparatus characterized in that:
【００３８】請求項５の発明によれば、はんだバンプは
低融点金属であり、フリップチップ接続後の基板と電子
部品とのギャップが、電子部品の電極および基板の電極
の一辺よりも大である。According to the fifth aspect of the present invention, the solder bump is made of a low melting point metal, and the gap between the substrate and the electronic component after flip-chip connection is larger than the electrode of the electronic component and one side of the electrode of the substrate. .
【００３９】したがって、請求項１ないし請求項５の発
明によれば、電子部品と基板に形成される電極とはんだ
バンプ周面とのなす接触角が小さくなり、動作時にはん
だバンプの受ける熱応力の低減を図り、よって信頼性の
向上を得られるなどの効果を奏する。Therefore, according to the first to fifth aspects of the present invention, the contact angle between the electrode formed on the electronic component and the substrate and the peripheral surface of the solder bump is reduced, and the thermal stress applied to the solder bump during operation is reduced. This has the effect of reducing the number of components, thereby improving the reliability.
【図１】本発明の実施の形態の、電子部品（半導体チッ
プ）をフリップチップ実装した基板の縦断面図。FIG. 1 is a longitudinal sectional view of a substrate on which an electronic component (semiconductor chip) is flip-chip mounted according to an embodiment of the present invention.
【図２】（Ａ），（Ｂ）は、同実施の形態の、電子部品
（半導体チップ）をフリップチップ実装する工程を順に
説明する図。FIGS. 2A and 2B are diagrams sequentially illustrating steps of flip-chip mounting an electronic component (semiconductor chip) according to the embodiment;
【図３】（Ａ）ないし（Ｄ）は、他の実施の形態の、電
子部品（半導体チップ）をフリップチップ実装する工程
を順に説明する図。FIGS. 3A to 3D are diagrams sequentially explaining steps of flip-chip mounting an electronic component (semiconductor chip) according to another embodiment; FIGS.
【図４】（Ａ），（Ｂ）は、はんだバンプの形態を示す
図。FIGS. 4A and 4B are diagrams showing a form of a solder bump.
【図５】基板における基板電極と半導体チップ電極の平
面図。FIG. 5 is a plan view of a substrate electrode and a semiconductor chip electrode on the substrate.
【図６】基板における基板電極と半導体チップ電極の他
の形態の平面図。FIG. 6 is a plan view of another embodiment of the substrate electrode and the semiconductor chip electrode on the substrate.
【図７】（Ａ）は、従来の形態の、電子部品（半導体チ
ップ）をフリップチップ実装した基板の縦断面図。
（Ｂ）は、はんだバンプの形態を示す図。FIG. 7 (A) is a longitudinal sectional view of a conventional board on which electronic components (semiconductor chips) are flip-chip mounted.
(B) is a diagram showing a form of a solder bump.
３…基板、 ４…（基板）電極、 １…電子部品（半導体チップ）、 ５…（半導体チップ）電極、 ２…はんだバンプ、 ６…基板保持機構、 ７…電子部品保持機構。 ８…基板支持台、 ９…電子部品搬送機構（吸着ノズル）。 3 ... substrate, 4 ... (substrate) electrode, 1 ... electronic component (semiconductor chip), 5 ... (semiconductor chip) electrode, 2 ... solder bump, 6 ... substrate holding mechanism, 7 ... electronic component holding mechanism. 8: substrate support stand, 9: electronic component transport mechanism (suction nozzle).
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2775097AJPH10223693A (en) | 1997-02-12 | 1997-02-12 | Electronic component mounting method and electronic component mounting device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2775097AJPH10223693A (en) | 1997-02-12 | 1997-02-12 | Electronic component mounting method and electronic component mounting device |
| Publication Number | Publication Date |
|---|---|
| JPH10223693Atrue JPH10223693A (en) | 1998-08-21 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2775097APendingJPH10223693A (en) | 1997-02-12 | 1997-02-12 | Electronic component mounting method and electronic component mounting device |
| Country | Link |
|---|---|
| JP (1) | JPH10223693A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227271A (en)* | 2007-03-14 | 2008-09-25 | Fujitsu Ltd | Electronic device and electronic component mounting method |
| US8104666B1 (en)* | 2010-09-01 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal compressive bonding with separate die-attach and reflow processes |
| US8177862B2 (en) | 2010-10-08 | 2012-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd | Thermal compressive bond head |
| US8381965B2 (en) | 2010-07-22 | 2013-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal compress bonding |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227271A (en)* | 2007-03-14 | 2008-09-25 | Fujitsu Ltd | Electronic device and electronic component mounting method |
| US8381965B2 (en) | 2010-07-22 | 2013-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal compress bonding |
| US8556158B2 (en) | 2010-07-22 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal compress bonding |
| US8104666B1 (en)* | 2010-09-01 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal compressive bonding with separate die-attach and reflow processes |
| CN102386114A (en)* | 2010-09-01 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Die Bonding Method |
| US8317077B2 (en) | 2010-09-01 | 2012-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal compressive bonding with separate die-attach and reflow processes |
| US8177862B2 (en) | 2010-10-08 | 2012-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd | Thermal compressive bond head |
| Publication | Publication Date | Title |
|---|---|---|
| CN102386114B (en) | Die Bonding Method | |
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