【０００１】[0001]
【発明の属する技術分野】本発明は、マトリクス表示方
式の交流（ＡＣ）型のプラズマディスプレイパネル（Ｐ
ＤＰ）の駆動方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix display type alternating current (AC) type plasma display panel (P).
DP).
【０００２】[0002]
【従来の技術】近年、表示装置の大型化に伴い、薄型の
表示装置が要求され、各種の薄型の表示装置が提供され
ている。その１つにＡＣＰＤＰが知られている。かかる
ＡＣＰＤＰは、列電極及び列電極と直交し一対にて１行
（１走査ライン）を構成する行電極を備えており、これ
ら列電極及び行電極対各々は放電空間に対して誘電体層
で覆われており、列電極及び行電極対の各交点に放電セ
ルが形成されている。2. Description of the Related Art In recent years, as display devices have become larger, thinner display devices have been required, and various thin display devices have been provided. ACPDP is known as one of them. Such an ACPDP includes a column electrode and a row electrode which is orthogonal to the column electrode and constitutes one row (one scanning line) in a pair. Each of the column electrode and the row electrode pair is a dielectric layer with respect to the discharge space. A discharge cell is formed at each intersection of a column electrode and a row electrode pair.
【０００３】図４は、係るＡＣＰＤＰの従来の各種駆動
パルスの印加タイミングを示す図である。同図におい
て、まず、負極性のリセットパルスＲＰx を全ての行電
極Ｘ1〜Ｘn に印加すると同時に、正極性のリセットパ
ルスＲＰy を全ての行電極Ｙ1〜Ｙn の各々に印加す
る。かかるリセットパルスの印加により、全ての放電セ
ルに放電が生じ、荷電粒子が発生し、放電終了後各放電
セルに壁電荷が蓄積形成される（一斉リセット期間）。FIG. 4 is a diagram showing the timing of applying various driving pulses of the conventional ACPDP. In the figure, first, a reset pulse RPx of a negative polarity is applied to all the row electrodes X1 to Xn, and at the same time, a reset pulse RPy of a positive polarity is applied to all of the row electrodes Y1 to Yn. By the application of such a reset pulse, discharge occurs in all the discharge cells, charged particles are generated, and after the discharge is completed, wall charges are accumulated and formed in each discharge cell (simultaneous reset period).
【０００４】次に、各行毎の画素データに対応した画素
データパルスＤＰ1 〜ＤＰn を順次、列電極Ａ1 〜Ａm
に印加する。この画素データパルスＤＰ1 〜ＤＰn 各々
の印加タイミングに同期して走査パルス（選択消去パル
ス）ＳＰを行電極Ｙ1 〜Ｙn へ順次印加して行く。この
際、かかる画素データパルスＤＰ、及び走査パルスＳＰ
が各々列電極及び行電極に同時に印加された放電セル
（消灯画素）にのみ放電が生じ上記一斉リセット期間に
て形成された壁電荷が消去される。Next, pixel data pulses DP1 to DPn corresponding to pixel data of each row are sequentially applied to column electrodes A1 to Am.
Is applied. A scanning pulse (selection erasing pulse) SP is sequentially applied to the row electrodes Y1 to Yn in synchronization with the application timing of each of the pixel data pulses DP1 to DPn. At this time, the pixel data pulse DP and the scanning pulse SP
Discharge occurs only in the discharge cells (light-off pixels) that are simultaneously applied to the column electrodes and the row electrodes, respectively, and the wall charges formed during the simultaneous reset period are erased.
【０００５】一方、走査パルスＳＰが印加されたものの
画素データパルスＤＰが印加されない放電セル（点灯画
素）では上記の如き放電は生じないので上記一斉リセッ
ト期間にて形成された壁電荷はそのまま残留する。この
ように各放電セルの壁電荷は、画素データに応じて選択
的に消去され、点灯画素及び消灯画素が選択される（ア
ドレス期間）。On the other hand, in a discharge cell (lighting pixel) to which the scanning pulse SP is applied but the pixel data pulse DP is not applied, the above-described discharge does not occur, and thus the wall charges formed during the simultaneous reset period remain as they are. . As described above, the wall charges of each discharge cell are selectively erased according to the pixel data, and the lit pixel and the unlit pixel are selected (address period).
【０００６】次に、正極性の放電維持パルスＩＰx を行
電極Ｘ1 〜Ｘn の各々に印加するとともに放電維持パル
スＩＰx の印加タイミングとはずれたタイミングにて正
極性の放電維持パルスＩＰy を行電極Ｙ1 〜Ｙn の各々
に印加する。このように放電維持パルスＩＰx 、ＩＰy
を交互に行電極対に印加され、壁電荷が残留している放
電セル（点灯画素）は放電発光を繰り返す一方壁電荷が
消滅した放電セル（消灯画素）は放電発光しない（維持
放電期間）。Next, a positive sustaining pulse IPx is applied to each of the row electrodes X1 to Xn, and a positive sustaining pulse IPy is applied to the row electrodes Y1 to Xn at a timing different from the application timing of the sustaining pulse IPx. Yn. Thus, the sustaining pulses IPx, IPy
Are alternately applied to the row electrode pairs, and discharge cells (lighted pixels) in which wall charges remain repeat discharge light emission, while discharge cells (light-off pixels) in which wall charges have disappeared do not discharge light emission (sustain discharge period).
【０００７】次に、全ての行電極Ｘ1 〜Ｘn に一斉に消
去パルスＥＰを印加して全放電セルの壁電荷を消去する
（壁電荷消去期間）。以上のように、一斉リセット期
間、アドレス期間、維持放電期間、壁電荷消去期間を１
つの表示サイクルとして、これを繰り返し行うことによ
り、画像表示が行われる。Next, an erase pulse EP is simultaneously applied to all the row electrodes X1 to Xn to erase the wall charges of all the discharge cells (wall charge erase period). As described above, the simultaneous reset period, the address period, the sustain discharge period, and the wall charge erase period
By repeating this as one display cycle, an image is displayed.
【０００８】[0008]
【発明が解決しようとする課題】ところで、上述のＰＤ
Ｐでは、行電極を透明電極としているため、抵抗率が大
きい。そこで、維持電極の導電性を補うために金属電極
からなるバス電極を積層して配線抵抗を低減している。
しかしながら、ＰＤＰが大型化していくと、金属電極の
配線長が長くなるため、バス電極自体の配線抵抗も無視
できなくなる。By the way, the above-mentioned PD
In P, since the row electrode is a transparent electrode, the resistivity is large. Therefore, in order to supplement the conductivity of the sustain electrode, bus electrodes made of metal electrodes are stacked to reduce wiring resistance.
However, as the size of the PDP increases, the wiring length of the metal electrode increases, so that the wiring resistance of the bus electrode itself cannot be ignored.
【０００９】一方、各放電セルに流れる電流は、時間的
に一定ではなく、駆動パルスが印加されてから例えば数
１００ナノｓｅｃ程度で最大になりその後数１００ナノ
ｓｅｃ程度経過するとほぼ流れなくなる。表示のための
維持放電期間において、放電維持パルスのパルス間隔は
数マイクロｓｅｃ程度であるため、１つの行電極対上の
選択された放電セルがほぼ同時に放電し、選択された放
電セルにおいてほぼ同時に電流が流れる。On the other hand, the current flowing in each discharge cell is not constant in time, but becomes maximum at, for example, about several hundred nanoseconds after the drive pulse is applied, and substantially stops flowing when about several hundred nanoseconds elapse thereafter. In the sustain discharge period for display, the pulse interval of the sustain pulse is about several microseconds, so that the selected discharge cells on one row electrode pair discharge almost simultaneously, and the selected discharge cells almost simultaneously discharge. Electric current flows.
【００１０】このため、１つの行電極対の電流の最大値
は、各セルに流れる電流の最大値を加算したものとな
り、結果的に、１つの行電極対に瞬間的に大きな電流が
流れる。したがって、行電極の配線抵抗により、大きな
電圧降下が生じて表示特性を悪化させることになる。Therefore, the maximum value of the current of one row electrode pair is the sum of the maximum values of the current flowing through each cell. As a result, a large current flows instantaneously through one row electrode pair. Therefore, a large voltage drop occurs due to the wiring resistance of the row electrode, and the display characteristics are deteriorated.
【００１１】本発明は、上記の問題を解決するためにな
されたものであり、維持放電時に流れる電流を抑制し表
示特性を向上させることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to suppress a current flowing during sustain discharge and improve display characteristics.
【００１２】[0012]
【課題を解決するための手段】請求項１記載の発明は、
複数の行電極対と、行電極対に交差して配列された複数
の列電極とを有し、行電極対に走査パルスを印加すると
ともに列電極に画素データパルスを印加して画素データ
に応じて点灯及び消灯画素を選択するアドレス期間と、
行電極対に交互に放電維持パルスを印加して点灯及び消
灯画素を維持する維持放電期間とを用いて表示を行うプ
ラズマディスプレイパネルの駆動方法であって、維持放
電期間において放電維持パルスの印加開始から所定期間
の間に印加される放電維持パルスの電圧に比して所定期
間終了後に印加される放電維持パルスの電圧を低くする
ことを特徴とする。According to the first aspect of the present invention,
It has a plurality of row electrode pairs and a plurality of column electrodes arranged crossing the row electrode pairs, and applies a scan pulse to the row electrode pairs and applies a pixel data pulse to the column electrodes to respond to pixel data. Address period for selecting the light-on and light-off pixels by
A method of driving a plasma display panel that performs display using a sustain discharge period in which a sustaining period is maintained by applying a sustaining pulse alternately to a row electrode pair to maintain a turned-on and a light-off pixel. The voltage of the sustaining pulse applied after the end of the predetermined period is lower than the voltage of the sustaining pulse applied during the predetermined period from.
【００１３】また、請求項２記載の発明は、請求項１記
載のプラズマディスプレイパネルの駆動方法において、
行電極対は、表示面側の基板の内面に配置された透明電
極とそれに積層された金属電極とで構成され、誘電体層
で被覆されているとともに列電極は、表示面側の基板と
放電空間を介して対向配置された背面側の基板の内面に
配置され、蛍光体層で被覆されていることを特徴とす
る。According to a second aspect of the present invention, in the method for driving a plasma display panel according to the first aspect,
The row electrode pair is composed of a transparent electrode disposed on the inner surface of the substrate on the display surface side and a metal electrode laminated thereon, and is covered with a dielectric layer. It is disposed on the inner surface of the rear substrate opposed to the substrate via a space, and is covered with a phosphor layer.
【００１４】[0014]
【作用】本発明は以上のように構成したので、維持放電
期間において、放電維持パルスの印加開始から所定期間
ａの間に印加される放電維持パルスの電圧Ｖｓ1 に比し
て所定期間ａの終了後の所定期間ｂに印加される放電維
持パルスの電圧Ｖｓ2 をステップ状に低くすることによ
って、各行電極に流れる電流を抑制することができ、し
たがって、各行電極の配線抵抗による電圧降下が少なく
なり、各行電極における画素セルの輝度ムラが少なくな
る。この結果プラズマディスプレイパネルの表示特性が
向上する。Since the present invention is constructed as described above, the end of the predetermined period a in the sustain discharge period is shorter than the voltage Vs1 of the sustaining pulse applied during the predetermined period a from the start of the application of the sustaining pulse. By lowering the voltage Vs2 of the sustaining pulse applied in the subsequent predetermined period b in a step-like manner, it is possible to suppress the current flowing through each row electrode, and thus reduce the voltage drop due to the wiring resistance of each row electrode, The luminance unevenness of the pixel cell in each row electrode is reduced. As a result, the display characteristics of the plasma display panel are improved.
【００１５】[0015]
【発明の実施の形態】図１は、本発明の一実施形態にお
けるプラズマディスプレイパネルの駆動方法で駆動され
る３電極構造の反射型ＡＣＰＤＰの構造を示す図であ
る。同図に示されるように、ＰＤＰ１１は、放電空間７
を介して対向配置された一対のガラス基板１、２の表示
面側のガラス基板１の内面に互いに平行に隣接配置され
た一対の行電極（維持電極）Ｘ、Ｙ、行電極Ｘ、Ｙを覆
う壁電荷形成用の誘電体層５、誘電体層５を覆うＭｇＯ
からなる保護層６がそれぞれ設けられている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a structure of a three-electrode reflective ACDP which is driven by a driving method of a plasma display panel according to an embodiment of the present invention. As shown in FIG.
A pair of row electrodes (sustain electrodes) X, Y and row electrodes X, Y arranged adjacent to each other in parallel with each other on the inner surface of the glass substrate 1 on the display surface side of the pair of glass substrates 1, 2 opposed to each other via Dielectric layer 5 for covering wall charge, MgO covering dielectric layer 5
Are provided respectively.
【００１６】尚、行電極Ｘ、Ｙは、それぞれ幅の広い帯
状の透明導電膜からなる透明電極４とその導電性を補う
ために積層された幅の狭い帯状の金属膜からなるバス電
極（金属電極）３とから構成されている。The row electrodes X and Y are each composed of a transparent electrode 4 made of a wide band-shaped transparent conductive film and a bus electrode made of a narrow band-shaped metal film laminated to supplement the conductivity. Electrodes 3).
【００１７】一方、背面側のガラス基板２の内面上に行
電極Ｘ、Ｙと交差する方向に設けられ、放電空間７を区
画する障壁１０、各障壁１０間のガラス基板２上に行電
極Ｘ、Ｙと交差する方向に配列された列電極（アドレス
電極）Ａ、及び各列電極、障壁１０の側面を覆う所定の
発光色の蛍光体層８がそれぞれ設けられている。そし
て、放電空間７にはネオンに少量のキセノンを混合した
放電ガスが封入されている。上記の列電極及び行電極対
の各交点において放電セル（画素）が形成される。On the other hand, barriers 10 are provided on the inner surface of the glass substrate 2 on the rear side in a direction intersecting the row electrodes X and Y, and partition the discharge space 7. , Y, and column electrodes (address electrodes) A arranged in a direction intersecting with each other, and a phosphor layer 8 of a predetermined emission color that covers each column electrode and the side surface of the barrier 10 is provided. The discharge space 7 is filled with a discharge gas obtained by mixing a small amount of xenon with neon. A discharge cell (pixel) is formed at each intersection of the above-mentioned column electrode and row electrode pair.
【００１８】次に図１のＰＤＰ１１を使用して行われる
本発明によるプラズマディスプレイパネルの駆動方法の
実施形態を図２に基づいて以下に説明する。図２は、本
発明の駆動方法の第一の実施形態にてパネル駆動を行う
際にＰＤＰ１１に印加される各種駆動パルスの印加タイ
ミングを示す図である。Next, an embodiment of a method of driving a plasma display panel according to the present invention, which is performed using the PDP 11 of FIG. 1, will be described with reference to FIG. FIG. 2 is a diagram showing application timings of various drive pulses applied to the PDP 11 when performing panel driving in the first embodiment of the driving method of the present invention.
【００１９】図２において、ＰＤＰ１１を駆動するに
は、先ず、立ち上がり時間の長い（長時定数）パルス負
電圧の第１リセットパルスＲＰx1を全ての行電極Ｘ1 〜
Ｘn に印加すると同時に、負電圧の場合と同様に正電圧
の第１リセットパルスＲＰy を行電極Ｙ1 〜Ｙn の各々
に印加する。各行電極対間に印加された電位−ＶP1と電
位＋ＶP2とにて生成される電位差が放電開始電圧を越え
ると、ＰＤＰ１１の全ての行電極対間に放電が励起され
て、ＰＤＰ１１の放電セル即ち全画素セルに対応する放
電空間７内に荷電粒子が発生する。In FIG. 2, in order to drive the PDP 11, first, a first reset pulse RPx1 of a negative voltage having a long rising time (long time constant) is applied to all the row electrodes X1 to X1.
Simultaneously with the application to Xn, a first reset pulse RPy of a positive voltage is applied to each of the row electrodes Y1 to Yn as in the case of the negative voltage. When the potential difference generated between the potential -VP1 and the potential + VP2 applied between each row electrode pair exceeds the discharge starting voltage, discharge is excited between all the row electrode pairs of the PDP 11, and the discharge cells of the PDP 11, ie, all Charged particles are generated in the discharge space 7 corresponding to the pixel cell.
【００２０】このリセットパルスは、列電極に比して微
弱なものにしているので、全画素セルに対応する放電空
間内の壁電荷が不均一になるため、行電極Ｘ1 〜Ｘn に
印加される第１リセットパルスＲＰx1の次の瞬間に正電
圧の第２リセットパルスＲＰx2を挿入している。Since the reset pulse is weaker than the column electrodes, the wall charges in the discharge spaces corresponding to all the pixel cells become non-uniform, and are applied to the row electrodes X1 to Xn. At the next moment after the first reset pulse RPx1, the second reset pulse RPx2 of positive voltage is inserted.
【００２１】この第２リセットパルスＲＰx2に用いる電
圧は、第１リセットパルスＲＰy とほぼ同一の大きさの
電圧（略＋１６５Ｖ）としている。第２リセットパルス
ＲＰx2の印加による放電の終息後、全画素セルの誘電体
層５には一様に所定量の壁電荷が形成される（一斉リセ
ット期間）。The voltage used for the second reset pulse RPx2 is the same voltage (approximately +165 V) as the first reset pulse RPy. After the end of the discharge due to the application of the second reset pulse RPx2, a predetermined amount of wall charges is uniformly formed on the dielectric layers 5 of all the pixel cells (simultaneous reset period).
【００２２】次に、各行毎との画素データに対応した正
電圧の画素データパルスＤＰ1 〜ＤＰn を順次、列電極
Ａ1 〜Ａm に印加する。この際、上記画素データパルス
ＤＰ1 〜ＤＰn の各印加タイミングに同期して、小なる
パルス幅の走査パルスＳＰを行電極Ｙ1 〜Ｙn へ順次印
加する。また、かかる走査パルスＳＰを各行電極Ｙ1〜
Ｙn の各々に印加する直前に、図２にて示されるが如き
正電圧のプライミングパルスＰＰを行電極Ｙ1 〜Ｙn 各
々に印加する。Next, pixel data pulses DP1 to DPn of positive voltage corresponding to pixel data for each row are sequentially applied to the column electrodes A1 to Am. At this time, a scanning pulse SP having a small pulse width is sequentially applied to the row electrodes Y1 to Yn in synchronization with the application timings of the pixel data pulses DP1 to DPn. The scanning pulse SP is applied to each of the row electrodes Y1 to Y1.
Immediately before application to each of Yn, a priming pulse PP of a positive voltage as shown in FIG. 2 is applied to each of the row electrodes Y1 to Yn.
【００２３】かかるプライミングパルスＰＰの印加によ
り、上記一斉リセットにて得られて時間経過とともに減
少してしまったプライミング粒子が、放電空間７内に再
形成される。よって、放電空間７内に所望量のプライミ
ング粒子が存在する内に、上記走査パルスＳＰの印加に
よる画素データ書き込みが試されるのである。By the application of the priming pulse PP, the priming particles obtained by the simultaneous reset and reduced with the passage of time are re-formed in the discharge space 7. Therefore, while the desired amount of the priming particles is present in the discharge space 7, the pixel data writing by applying the scanning pulse SP is tried.
【００２４】例えば、画素データの内容が論理「０」で
ある場合には、走査パルスＳＰとともに画素データパル
スＤＰが同時に印加されるので、画素セル内部に形成さ
れている壁電荷は消滅する。For example, when the content of the pixel data is logic "0", the pixel data pulse DP is applied simultaneously with the scan pulse SP, so that the wall charges formed inside the pixel cell disappear.
【００２５】一方、画素データの内容が論理「１」であ
る場合には、走査パルスＳＰのみが印加されるので放電
が生じず、その画素セル内部に形成されている壁電荷は
そのまま保持される。つまり、かかる走査パルスＳＰと
は、画素セル内に形成されている壁電荷を画素データに
応じて選択的に消去せしめるためのトリガとなる選択消
去パルスとも言えるのである。このように、各画素セル
の壁電荷は、画素データに応じて選択的に消去され、点
灯画素及び消灯画素が選択される（アドレス期間）。On the other hand, when the content of the pixel data is logic "1", only the scan pulse SP is applied, so that no discharge occurs, and the wall charges formed inside the pixel cell are held as they are. . That is, the scanning pulse SP can be said to be a selective erasing pulse which is a trigger for selectively erasing wall charges formed in the pixel cell according to the pixel data. As described above, the wall charge of each pixel cell is selectively erased according to the pixel data, and the lit pixel and the unlit pixel are selected (address period).
【００２６】次に、正電圧の維持パルスＩＰx を行電極
Ｘ1 〜Ｘn の夫々に印加する。次に、かかる放電維持パ
ルスＩＰx の印加タイミングとはずれたタイミングに
て、正電圧の放電維持パルスＩＰy を行電極Ｙ1 〜Ｙn
の夫々に印加する。かかる放電維持パルスが連続して行
電極Ｘi 、Ｙi に交互に印加されている期間にわたり、
上記壁電荷が残留したままとなっている画素セルのみが
放電発光を維持する（維持放電期間）。Next, a sustain pulse IPx of a positive voltage is applied to each of the row electrodes X1 to Xn. Next, at a timing different from the application timing of the sustaining pulse IPx, a positive sustaining pulse IPy is applied to the row electrodes Y1 to Yn.
Is applied to each of them. Over a period in which such a sustaining pulse is continuously applied to the row electrodes Xi and Yi alternately,
Only the pixel cells in which the wall charges remain remain sustaining discharge light emission (sustain discharge period).
【００２７】尚、この維持放電期間において、最初に、
即ち第１番目に行電極に印加される放電維持パルスＩＰ
x （図中ＩＰx1で表示している）のパルス幅は、その後
に印加される放電維持パルスのパルス幅に比して長く設
定している。これにより、維持放電期間の開始時に生じ
ている各行でのプライミング粒子数のバラツキによる影
響を軽減している。In this sustain discharge period, first,
That is, the first sustaining pulse IP applied to the row electrode
The pulse width of x (indicated by IPx1 in the figure) is set longer than the pulse width of the sustaining pulse applied thereafter. Thus, the influence of the variation in the number of priming particles in each row, which occurs at the start of the sustain discharge period, is reduced.
【００２８】また、維持放電期間において各行電極に印
加される放電維持パルスＩＰx は、各行電極において、
それぞれ放電維持パルスの印加開始から所定期間ａの間
に印加される放電維持パルスの電圧の大きさをＶｓ1 と
し、所定期間ａの終了から維持放電期間の終了までの所
定期間ｂに印加される放電維持パルスの電圧Ｖｓ2 はＶ
ｓ1 よりも低く設定される。The sustaining pulse IPx applied to each row electrode during the sustaining discharge period is applied to each row electrode.
The magnitude of the voltage of the sustaining pulse applied during the predetermined period a from the start of the application of the sustaining pulse is Vs1, and the discharge applied during the predetermined period b from the end of the predetermined period a to the end of the sustaining period. The voltage Vs2 of the sustain pulse is V
It is set lower than s1.
【００２９】このことにより、維持放電期間中では、各
行電極における各セルに流れる電流の最大値を加算して
得られる電流の最大値は従来に比べて小さくなり、各行
電極に流れる電流は抑制される。したがって、各行電極
の各画素セルにおける電圧降下が少なくなるので各画素
セルの輝度ムラが少ない。As a result, during the sustain discharge period, the maximum value of the current obtained by adding the maximum value of the current flowing through each cell in each row electrode is smaller than that of the prior art, and the current flowing through each row electrode is suppressed. You. Accordingly, the voltage drop in each pixel cell of each row electrode is reduced, and the luminance unevenness of each pixel cell is reduced.
【００３０】また、上述のように、各行電極を流れる電
流の最大値が従来に比べて小さくなることで、維持放電
期間におけるＰＤＰの消費電力が減り、電磁波ノイズの
発生も少なくなる。また、放電維持に必要な電圧を低く
抑えることができる。Further, as described above, since the maximum value of the current flowing through each row electrode is smaller than in the prior art, the power consumption of the PDP during the sustain discharge period is reduced, and the generation of electromagnetic wave noise is also reduced. Further, the voltage required for maintaining the discharge can be kept low.
【００３１】次に、消去パルスＥＰを行電極Ｘ1 〜Ｘn
の夫々に印加することにより、行電極Ｘ1 〜Ｘn 及びＹ
1 〜Ｙn 上に形成された壁電荷を消滅させ、点灯及び消
灯画素での壁電荷の状態を略均一にする（壁電荷消去期
間）。Next, the erase pulse EP is applied to the row electrodes X1 to Xn.
To the row electrodes X1 to Xn and Y
The wall charges formed on 1 to Yn are eliminated, and the state of the wall charges in the lit and unlit pixels is made substantially uniform (wall charge erasing period).
【００３２】以上の如く、かかるプラズマディスプレイ
パネルの駆動方法においては、維持放電期間において、
放電維持パルスの印加開始から所定期間ａの間に印加さ
れる放電維持パルスの電圧Ｖｓ1 に比して所定期間ａの
終了後の所定期間ｂに印加される放電維持パルスの電圧
Ｖｓ2 をステップ状に低くすることによって、各行電極
に流れる電流を抑制することができ、したがって、各行
電極の配線抵抗による電圧降下が少なくなり、各行電極
における画素セルの輝度ムラが少なくなる。この結果プ
ラズマディスプレイパネルの表示特性が向上する。As described above, in such a method of driving a plasma display panel, in the sustain discharge period,
The voltage Vs2 of the sustaining pulse applied during the predetermined period b after the end of the predetermined period a is stepped compared to the voltage Vs1 of the sustaining pulse applied during the predetermined period a from the start of the application of the sustaining pulse. By lowering the current, the current flowing through each row electrode can be suppressed, so that the voltage drop due to the wiring resistance of each row electrode is reduced, and the luminance unevenness of the pixel cell in each row electrode is reduced. As a result, the display characteristics of the plasma display panel are improved.
【００３３】なお、上記実施形態においては、維持放電
期間において各行電極に印加される放電維持パルスを２
つの異なる電圧値（Ｖｓ1 及びＶｓ2 ）で設定し、各行
電極において、それぞれ放電維持パルスの印加開始から
所定期間ａの間に印加される放電維持パルスの電圧の大
きさをＶｓ1 とし、所定期間ａの終了から維持放電期間
の終了までの所定期間ｂに印加される放電維持パルスを
Ｖｓ1 よりも低い電圧Ｖｓ2 とする２段階で設定した
が、かかる構成に限定されるものではない。In the above embodiment, the sustaining pulse applied to each row electrode during the sustaining discharge period is 2 pulses.
Two different voltage values (Vs1 and Vs2) are set, and in each row electrode, the magnitude of the voltage of the sustaining pulse applied during the predetermined period a from the start of the application of the sustaining pulse is set to Vs1. Although the sustaining pulse applied during the predetermined period b from the end to the end of the sustaining discharge period is set to two levels in which the voltage Vs2 is lower than Vs1, it is not limited to such a configuration.
【００３４】即ち、図３に示すように、維持放電期間に
おいて印加される放電維持パルスは、放電維持パルスの
印加開始から所定期間ａの間に印加される放電維持パル
スの電圧Ｖｓ1 に比して所定期間ａの終了後に順次印加
される放電維持パルスの電圧を徐々に低く設定し、維持
放電期間の最後に各電極に印加する電圧がＶｓ1 よりも
低い値のＶｓ2 になるように設定しても良い。図３は、
本発明の駆動方法の第二の実施形態にてパネル駆動を行
う際にＰＤＰ１１に印加される各種駆動パルスの印加タ
イミングを示す図である。That is, as shown in FIG. 3, the sustaining pulse applied during the sustaining discharge period is compared with the voltage Vs1 of the sustaining pulse applied during the predetermined period a from the start of the application of the sustaining pulse. The voltage of the sustaining pulse applied sequentially after the end of the predetermined period a may be set to gradually lower, and the voltage applied to each electrode at the end of the sustaining period may be set to Vs2 lower than Vs1. good. FIG.
FIG. 9 is a diagram illustrating application timings of various drive pulses applied to the PDP 11 when performing panel driving in the second embodiment of the driving method of the present invention.
【００３５】[0035]
【発明の効果】本発明は以上のように構成したため、維
持放電期間において、放電維持パルスの印加開始から所
定期間ａの間に印加される放電維持パルスの電圧Ｖｓ1
に比して所定期間ａの終了後の所定期間ｂに印加される
放電維持パルスの電圧Ｖｓ2 をステップ状に低くするこ
とによって、各行電極に流れる電流を抑制することがで
き、したがって、各行電極の配線抵抗による電圧降下が
少なくなり、各行電極における画素セルの輝度ムラが少
なくなる。この結果プラズマディスプレイパネルの表示
特性が向上する。According to the present invention, the voltage Vs1 of the sustaining pulse applied during the predetermined period "a" from the start of the application of the sustaining pulse during the sustaining discharge period.
By lowering the voltage Vs2 of the sustaining pulse applied in the predetermined period b after the predetermined period a has ended in a step-like manner, the current flowing through each row electrode can be suppressed. The voltage drop due to the wiring resistance is reduced, and the luminance unevenness of the pixel cell in each row electrode is reduced. As a result, the display characteristics of the plasma display panel are improved.
【図１】本発明の一実施形態におけるプラズマディスプ
レイパネルの駆動方法で駆動される３電極構造の反射型
ＡＣＰＤＰの構造を示す図である。FIG. 1 is a diagram illustrating a structure of a reflective ACDP with a three-electrode structure driven by a method of driving a plasma display panel according to an embodiment of the present invention.
【図２】本発明の駆動方法の第一の実施形態にてパネル
駆動を行う際にＰＤＰに印加される各種駆動パルスの印
加タイミングを示す図である。FIG. 2 is a diagram showing application timings of various driving pulses applied to a PDP when performing panel driving in the first embodiment of the driving method of the present invention.
【図３】本発明の駆動方法の第二の実施形態にてパネル
駆動を行う際にＰＤＰに印加される各種駆動パルスの印
加タイミングを示す図である。FIG. 3 is a diagram showing application timings of various drive pulses applied to a PDP when performing panel driving in a second embodiment of the driving method of the present invention.
【図４】ＡＣＰＤＰの従来の各種駆動パルスの印加タイ
ミングを示す図である。FIG. 4 is a diagram showing application timings of various conventional drive pulses of an ACPDP.
１、２・・・・ガラス基板 ３・・・・・・バス電極 ４・・・・・・透明電極 ５・・・・・・誘電体層 ６・・・・・・保護層 ７・・・・・・放電空間 ８・・・・・・蛍光体層 １０・・・・・障壁 １１・・・・・ＰＤＰ 1, 2, glass substrate 3 bus electrode 4 transparent electrode 5 dielectric layer 6 protective layer 7 ... Discharge space 8 ... Phosphor layer 10 ... Barrier 11 ... PDP
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8354002AJPH10177363A (en) | 1996-12-18 | 1996-12-18 | Plasma display panel drive method |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8354002AJPH10177363A (en) | 1996-12-18 | 1996-12-18 | Plasma display panel drive method |
| Publication Number | Publication Date |
|---|---|
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8354002APendingJPH10177363A (en) | 1996-12-18 | 1996-12-18 | Plasma display panel drive method |
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