【０００１】[0001]
【発明の属する技術分野】本発明は、画像信号の信号処
理回路に係り、特に、飛び越し走査系の画像信号を順次
走査系の画像信号に変換するＩＰ変換や、複数方式の画
像信号を画像表示部の所定フォ−マットの画像信号に変
換するフォ−マット変換に好適な、画像信号のＩＰ変換
およびフォ−マット変換の信号処理回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for an image signal, and more particularly to an IP conversion for converting an image signal of an interlaced scanning system into an image signal of a sequential scanning system and an image display of an image signal of a plurality of systems. The present invention relates to a signal processing circuit for performing IP conversion and format conversion of an image signal, which is suitable for format conversion for converting an image signal into a predetermined format image signal.
【０００２】[0002]
【従来の技術】近年、マルチメディア社会の進展によ
り、画像信号に関しては、取り扱う画像の種類や形態が
飛躍的に増加し、多様化の方向に進捗している。また、
画像を表示するディスプレイに関しても、ＣＲＴの他
に、ＬＣＤ、ＰＤＰなどの平面ディスプレイが多く使用
されるようになってきた。このため、今後のマルチメデ
ィア対応の情報端末機器では、多種多様な画像ソ−スを
受信して表示する機能を備えることが必須になる。2. Description of the Related Art In recent years, with the progress of the multimedia society, the types and forms of images to be handled have been dramatically increased and image signals have been diversified. Also,
Regarding displays for displaying images, flat displays such as LCDs and PDPs have been increasingly used in addition to CRTs. For this reason, it is indispensable for information terminals compatible with multimedia in the future to have a function of receiving and displaying various image sources.
【０００３】この機能を実現する代表的な方法として
は、表示系で対処する方法と、信号処理で対処する方法
とが知られている。As a typical method of realizing this function, a method of coping with a display system and a method of coping with signal processing are known.
【０００４】前者の方法は、表示部の偏向系の動作範囲
を広く設定し、入力画像の信号フォ−マットと合致した
形態で走査を行って画像を表示するもので、マルチスキ
ャン方式として実用化されている。これは、表示部がＣ
ＲＴの場合には比較的低コストで実現でき有効な方法で
あるが、順次走査で表示画素数が一定のＬＣＤやＰＤＰ
などの平面ディスプレイでは適用が困難という問題があ
る。In the former method, the operating range of the deflection system of the display unit is set wide, and scanning is performed in a form conforming to the signal format of an input image to display an image. Have been. This is because the display is C
In the case of RT, it is an effective method that can be realized at a relatively low cost.
However, there is a problem that it is difficult to apply the present invention to a flat display such as the above.
【０００５】後者の方法は、入力画像信号に対してＩＰ
変換やフォ−マット変換の信号処理を行い、表示部のフ
ォ−マットの信号に変換して画像を表示する。このた
め、ＣＲＴに限らず、ＬＣＤやＰＤＰなどの平面ディス
プレイにも柔軟に対応できる。従って、今後予想される
入力ソ−スやディスプレイの多様化への対処には、極め
て有効な方法である。ただ、ＩＰ変換やフォ−マット変
換では、飛び越し〜順次の走査変換、フレ−ムレ−ト変
換、画面のサイズ縮小拡大変換などの信号処理に、膨大
な容量のメモリが必要になる。また、信号処理に伴い画
質が劣化する可能性もある。このため、高品質な画質を
維持し、信号処理に使用するメモリの容量が少なく、低
コストで実現できる信号処理回路を実現することが、重
要な課題になっている。[0005] The latter method uses an IP image signal for an input image signal.
It performs signal processing for conversion and format conversion, converts the signal into a signal in the format of the display unit, and displays an image. For this reason, it is possible to flexibly cope with not only CRTs but also flat displays such as LCDs and PDPs. Therefore, it is an extremely effective method for coping with the diversification of input sources and displays expected in the future. However, in IP conversion and format conversion, an enormous capacity of memory is required for signal processing such as interlace-to-sequential scan conversion, frame rate conversion, and screen size reduction / enlargement conversion. Further, there is a possibility that the image quality is degraded with the signal processing. Therefore, it is important to realize a signal processing circuit that maintains high quality image quality, has a small memory capacity for signal processing, and can be implemented at low cost.
【０００６】[0006]
【発明が解決しようとする課題】本発明は、上記の課題
に鑑みてなされたもので、使用するメモリの容量が極め
て少なく、低コスト化に適し、かつ、高品質な画質で画
像信号のＩＰ変換やフォ−マット変換を行う、信号処理
回路を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has an extremely small memory capacity, is suitable for cost reduction, and has a high quality image signal IP. It is an object of the present invention to provide a signal processing circuit for performing conversion and format conversion.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するた
め、本発明においては以下に述べる技術的手段を採用す
る。In order to achieve the above object, the present invention employs the following technical means.
【０００８】画像信号のＩＰ変換では、輝度信号に対し
ては、サブナイキスト標本化の信号処理で標本点の数を
1/2に削減し、この信号系列をメモリに記憶する。そし
て、メモリから読み出した信号系列を復号処理で元の標
本点数の輝度信号に再生し、この輝度信号をもとに動き
適応型の補間処理で補間走査線の信号を生成する。ま
た、動きの情報は、サブナイキスト標本化した信号系列
の１フレ−ム間の差分信号成分で検出する。この技術的
手段で、従来の方法に較べてメモリの容量を1/2と大幅
に削減することができる。なお、サブナイキスト標本化
の信号処理では、輝度信号高域の斜め成分が削られる
が、この成分は視覚の特性も劣っているため、画質の劣
化はほとんど検知できない程度に抑圧できる。[0008] In the IP conversion of an image signal, the number of sampling points is determined for a luminance signal by signal processing of sub-Nyquist sampling.
The signal sequence is reduced to 1/2, and this signal sequence is stored in the memory. Then, the signal sequence read from the memory is reproduced into a luminance signal of the original number of sample points by decoding processing, and a signal of an interpolation scanning line is generated by motion adaptive interpolation processing based on the luminance signal. The motion information is detected as a difference signal component between one frame of the signal sequence sampled by sub-Nyquist. With this technical measure, the capacity of the memory can be significantly reduced by half compared with the conventional method. In the signal processing of the sub-Nyquist sampling, an oblique component in a high-range luminance signal is removed. However, since this component has poor visual characteristics, deterioration in image quality can be suppressed to such an extent that it is hardly detectable.
【０００９】画像信号のフォ−マット変換では、飛び越
し走査系の画像信号はＩＰ変換で順次走査系の画像信号
に変換し、順次走査系の信号でフォ−マット変換のため
の水平、垂直方向の拡大縮小などの信号処理を行う。周
知の如く、順次走査系と飛び越し走査系とでは、順次走
査系の方がフィルタ設計などの自由度が大きい。よっ
て、この技術的手段で、フォ−マット変換の信号処理が
より理想に近い特性で実現できる。そして、信号処理に
伴う画質劣化を大幅に抑圧することができる。In the format conversion of an image signal, an image signal of an interlaced scanning system is converted into an image signal of a progressive scanning system by an IP conversion, and the signals of the progressive scanning system are used in the horizontal and vertical directions for format conversion. Performs signal processing such as scaling. As is well known, between the progressive scanning system and the interlaced scanning system, the progressive scanning system has a greater degree of freedom in filter design and the like. Therefore, by this technical means, signal processing of format conversion can be realized with more ideal characteristics. And image quality deterioration accompanying signal processing can be suppressed significantly.
【００１０】また、フォ−マット変換の信号処理では、
垂直スケ−リングの信号処理に先立って、水平スケ−リ
ングの信号処理を実行する。さらに、垂直スケ−リング
では、メモリの動作制御で、縮小拡大の信号処理の他
に、ＴＶ信号の方式変換（例えば、ＰＡＬ−ＮＴＳＣ変
換）のためのフレ−ムレ−ト変換や、ＰＡＬフィ−ルド
倍速変換や、２画面表示やＰＩＰ表示などのマルチ画面
の同期整合などの信号処理も併せて行う。この技術的手
段で、フォ−マット変換での信号処理に必要なメモリ容
量は、従来の方法（方式変換、縮小拡大、同期整合など
の信号処理をそれぞれ縦続的に行う）の数分の一と大幅
に削減でき、１フィ−ルド程度（数メガビット）の容量
で実現できる。In the signal processing of the format conversion,
Prior to signal processing for vertical scaling, signal processing for horizontal scaling is executed. Further, in vertical scaling, in addition to signal processing for reduction / enlargement in operation control of a memory, frame rate conversion for TV signal format conversion (for example, PAL-NTSC conversion) and PAL field conversion. It also performs signal processing such as double speed conversion and multi-screen synchronization matching such as two-screen display and PIP display. With this technical means, the memory capacity required for signal processing in format conversion is a fraction of that of the conventional method (each of which performs signal processing such as system conversion, reduction / enlargement, and synchronization matching in cascade). It can be greatly reduced and can be realized with a capacity of about one field (several megabits).
【００１１】さらに、水平、垂直スケ−リングの回路構
成は、複数画素あるいは複数ラインの画素に係数値を乗
算する演算部と、メモリ部と、複数個数のスイッチの組
み合わせで構成し、該スイッチを選択制御して信号を切
り換え、縮小機能や、拡大機能や、スル−の機能を実現
する。そして、演算部では、２点線形補間の特性の演算
を実行する。この技術的手段で、信号処理に必要な回路
規模を大幅に低減できる。Further, the circuit configuration of horizontal and vertical scaling includes a combination of an arithmetic unit for multiplying a plurality of pixels or pixels on a plurality of lines by a coefficient value, a memory unit, and a plurality of switches, and the switches are constituted by a plurality of switches. The signal is switched by performing selective control to realize a reduction function, an enlargement function, and a through function. Then, the calculation unit performs calculation of the characteristics of the two-point linear interpolation. With this technical means, the circuit scale required for signal processing can be significantly reduced.
【００１２】また、順次走査系の信号を２系列の信号に
分割し、この２系列の信号に対して、フォ−マット変換
のための水平、垂直スケ−リングの信号処理を１／２の
動作速度で実行する。この技術的手段で、極めて高速動
作が要求される超高精細ディスプレイなどへのフォ−マ
ット変換信号処理を、１系列の場合と同程度のメモリ容
量で行うことができる。Further, the signal of the progressive scanning system is divided into two series of signals, and the horizontal and vertical scaling signal processing for format conversion is performed on the two series of signals in half. Run at speed. With this technical means, it is possible to perform format conversion signal processing for an ultra-high-definition display or the like, which requires extremely high-speed operation, with the same memory capacity as in the case of one series.
【００１３】また、フォ−マット変換の信号処理を行っ
た画像信号に対して、最後に色空間変換や逆γ変換など
の画質改善処理を実行する。一般に、この画質改善処理
出力では１０ビット／画素程度の精度が必要である。こ
の技術的手段で、水平、垂直スケ−リングまでの信号処
理は８ビット／画素で行えるため、メモリ容量の削減
や、回路規模の低減ができる。Finally, image quality improvement processing such as color space conversion and inverse γ conversion is performed on the image signal that has been subjected to the format conversion signal processing. Generally, the output of the image quality improvement processing requires an accuracy of about 10 bits / pixel. With this technical means, signal processing up to horizontal and vertical scaling can be performed with 8 bits / pixel, so that the memory capacity can be reduced and the circuit size can be reduced.
【００１４】そして、入力画像信号は、輝度信号と２つ
の色差信号とからなる４：２：２系、あるいは４：２：
０系のコンポ−ネント信号を採用する。この技術的手段
で、多様なソ−ス信号（例えば、現行ＴＶ信号、ＨＤＴ
Ｖ信号、ＥＤＴＶ信号、パソコン画像、パッケ−ジ系画
像など）が一元的に処理でき、また、２つの色差信号の
信号処理を、４：２：２系では輝度信号と同程度、４：
２：０系では輝度信号の１／２のメモリ容量で行うこと
ができる。The input image signal is a 4: 2: 2 system composed of a luminance signal and two color difference signals, or 4: 2:
0-component signal is used. With this technical means, various source signals (eg, current TV signals, HDT
V signal, EDTV signal, personal computer image, package image, etc.), and the signal processing of the two color difference signals is about the same as the luminance signal in the 4: 2: 2 system.
In the 2: 0 system, the operation can be performed with half the memory capacity of the luminance signal.
【００１５】以上に述べた技術的手段の採用により、高
品質な画質を維持して、メモリ容量が極めて少なく、低
コスト化に適した画像信号のＩＰ変換およびフォ−マッ
ト変換の信号処理回路を実現することができる。By adopting the technical means described above, a signal processing circuit for IP conversion and format conversion of an image signal, which maintains a high quality image, has a very small memory capacity, and is suitable for cost reduction. Can be realized.
【００１６】[0016]
【発明の実施の形態】本発明における画像信号のＩＰ変
換の信号処理回路の第１の実施例について、図１に示す
ブロック構成図で説明する。同図の１はプリフィルタ、
２はダウンサンプル部、３はアップサンプル部、４はポ
ストフィルタ、５は１Ｈ遅延、６,８は加算部、７は動
き係数加重部、９は１フィ−ルド遅延、１０は減算部、
１１は動き検出部、１２はＭＡＸ選択部、１３はα加重
部である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a signal processing circuit for IP conversion of an image signal according to the present invention will be described with reference to a block diagram shown in FIG. 1 in the figure is a pre-filter,
2 is a down-sampling section, 3 is an up-sampling section, 4 is a post filter, 5 is a 1H delay, 6 and 8 are addition sections, 7 is a motion coefficient weighting section, 9 is a 1-field delay, 10 is a subtraction section,
11 is a motion detecting unit, 12 is a MAX selecting unit, and 13 is an α weighting unit.
【００１７】飛び越し走査系の画像信号の輝度信号Y
は、プリフィルタ１に入力し、サブナイキスト標本化で
折り返し歪となる水平垂直の高域成分を除去する。ダウ
ンサンプル部２は、標本点の2:1のサブサンプリング処
理を行い、サブナイキスト標本化した信号系列を生成す
る。すなわち、図２(a)に示す標本点系列の信号に対
し、水平方向、垂直方向でそれぞれ標本点の1/2の間引
きを行い、(b)に示す標本点からなるサブナイキスト標
本化の信号系列を生成する。The luminance signal Y of the image signal of the interlaced scanning system
Is input to the pre-filter 1 and removes horizontal and vertical high-frequency components that are aliasing distortions in sub-Nyquist sampling. The down-sampling unit 2 performs a 2: 1 sub-sampling process on the sampling points to generate a signal sequence that is sub-Nyquist-sampled. In other words, the signal of the sample point series shown in FIG. 2A is thinned out by half of the sample points in the horizontal and vertical directions, respectively, and the signal of the sub-Nyquist sampling consisting of the sample points shown in FIG. Generate a series.
【００１８】アップサンプル部３は、標本点の2:1のア
ップサンプリング処理を行う。そして、サブナイキスト
標本化で抜けた標本点（図２(b)の・で示す点）には零
の信号を挿入し、図２(a)の標本点構造の信号系列を生
成する。ポストフィルタ４は、サブナイキスト標本化で
抜けた標本点の信号を、近傍の標本点の信号で補間する
信号処理を行い、入力と同じ標本点構造の輝度信号を再
生する。この信号の一方は、伝送走査線信号系列の輝度
信号YMとして出力する。The up-sampling section 3 performs a 2: 1 up-sampling process on the sample points. Then, a zero signal is inserted into the sampling points (points indicated by in FIG. 2 (b)) that have passed through the sub-Nyquist sampling, and a signal sequence having the sampling point structure shown in FIG. 2 (a) is generated. The post filter 4 performs signal processing for interpolating the signal of the sample point that has been dropped by the sub-Nyquist sampling with the signal of the nearby sample point, and reproduces the luminance signal having the same sample point structure as the input. One of these signals is output as a luminance signal YM of a transmission scanning line signal sequence.
【００１９】一方、この信号と、１Ｈ遅延５で１ライン
期間遅延させた信号は、加算部６で信号加算と係数値1/
2の加重を行い、フィ−ルド内補間による動画像に適し
た補間信号を生成する。On the other hand, this signal and the signal delayed for one line period by the 1H delay 5 are added by the adder 6 to the signal addition and the coefficient value 1 /.
A weight of 2 is applied to generate an interpolation signal suitable for a moving image by intra-field interpolation.
【００２０】また、メモリ部９で１フィ−ルド期間相当
(263H)遅延させたサブナイキスト標本化の信号系列は、
アップサンプル部３、ポストフィルタ４で復号処理を行
い、１フィ−ルド前の輝度信号を再生し、フィ−ルド間
補間の静止画像に適した補間信号を生成する。Also, the memory unit 9 corresponds to one field period.
(263H) The signal sequence of the delayed sub-Nyquist sampling is
The decoding processing is performed by the up-sampling unit 3 and the post filter 4, and the luminance signal one field before is reproduced to generate an interpolation signal suitable for a still image of the inter-field interpolation.
【００２１】更に、メモリ部９で１フィ−ルド期間相当
(262H)遅延させた１フレ−ム前のサブナイキスト標本化
の信号系列と、現フレ−ムのサブナイキスト標本化の信
号系列は、減算部１０で減算演算を行い、１フレ−ム間
の差分信号を検出する。動き検出部１１は、この差分信
号の絶対値の大小に応じて、0から1までの値の動き情報
係数を設定する。動きの検出漏れを回避するため、ＭＡ
Ｘ選択部１２で、１フィ−ルド前の動きの情報も使用し
て、最終的な動き係数Kを設定する。すなわち、α加重
部１３で係数α(0<α<1)を加重した信号をメモリ部９で
１フィ−ルド期間相当(262H)遅延させた信号、更に１Ｈ
遅延５で１ライン期間遅延させた信号(ト−タル263Hの
遅延)と、動き情報係数の間で、最大値を検出し、この
最大値を最終的な動き係数K(0≦K≦1,静止時:K=0)とし
て出力する。Further, the memory section 9 corresponds to one field period.
(262H) The subtraction unit 10 performs a subtraction operation on the delayed sub-Nyquist sampled signal sequence one frame before and the current frame sub-Nyquist sampled signal sequence. Detect the difference signal. The motion detection unit 11 sets a motion information coefficient having a value from 0 to 1 according to the magnitude of the absolute value of the difference signal. MA to avoid motion detection omission
The X selector 12 sets the final motion coefficient K using the information of the motion one field before. That is, the signal obtained by delaying the signal obtained by weighting the coefficient α (0 <α <1) by the α weighting unit 13 by one field period (262H) in the memory unit 9 and further by 1H
A maximum value is detected between the signal (total 263H delay) delayed by one line period by the delay 5 and the motion information coefficient, and this maximum value is determined as the final motion coefficient K (0 ≦ K ≦ 1, When stationary: K = 0) is output.
【００２２】動き係数加重部７−１と７−２は、それぞ
れ係数値K、1-Kを加重し、加算部８で両者の信号を加算
して、補間走査線信号系列の輝度信号YIを生成する。The motion coefficient weighting sections 7-1 and 7-2 weight the coefficient values K and 1-K, respectively, add the two signals in the addition section 8, and generate the luminance signal YI of the interpolation scanning line signal sequence. Generate.
【００２３】飛び越し走査系の画像信号の色差信号Cに
対しては、フィ−ルド内補間で補間信号を生成する。す
なわち、信号Cを伝送走査線信号系列の色差信号CMとし
て出力するとともに、この信号と、１Ｈ遅延５で１ライ
ン期間遅延させた信号を、加算部６で信号加算と係数値
1/2の加重を行い、補間走査線信号系列の色差信号CIを
生成する。For the color difference signal C of the interlaced scanning image signal, an interpolation signal is generated by intra-field interpolation. That is, the signal C is output as the color difference signal CM of the transmission scanning line signal sequence, and this signal and the signal delayed by one line period by the 1H delay 5 are added by the adder 6 to signal addition and coefficient value.
A weight of 1/2 is applied to generate a color difference signal CI of the interpolated scanning line signal sequence.
【００２４】プリフィルタ、ポストフィルタの一構成例
を図３に示す。同図(a)はフィルタのインパルス応答特
性で、水平方向、垂直方向ともに３タップの３ｘ３の２
次元フィルタである。なお、プリフィルタはこの数値に
1/16、ポストフィルタは1/8を掛けたものがタップ係数
となる。このフィルタは、同図(b)に示す構成で実現で
きる。１Ｈ遅延１４と係数加重部１５と加算部１６との
組み合わせで垂直ＨＰＦを実現し、１画素遅延部１７と
係数加重部１８と加算部１９との組み合わせで水平ＨＰ
Ｆを実現し、この縦続接続で、水平・垂直周波数の高域
成分を抽出する。そして、減算部２１で、遅延部２０で
時間遅延を調整した信号からこの高域成分を減算し、そ
の出力に、インパルス応答特性が同図(a)の信号を得
る。FIG. 3 shows a configuration example of the pre-filter and the post-filter. FIG. 7A shows the impulse response characteristics of the filter, which is a 3 × 3 2 × 3 tap in both the horizontal and vertical directions.
It is a dimensional filter. Note that the pre-filter is
1/16, the post filter multiplied by 1/8 is the tap coefficient. This filter can be realized by the configuration shown in FIG. A vertical HPF is realized by a combination of a 1H delay 14, a coefficient weighting unit 15, and an addition unit 16, and a horizontal HPF is realized by a combination of a one-pixel delay unit 17, a coefficient weighting unit 18, and an addition unit 19.
F is realized, and high-frequency components of horizontal and vertical frequencies are extracted by this cascade connection. Then, the subtraction section 21 subtracts the high frequency component from the signal whose time delay has been adjusted by the delay section 20, and obtains a signal whose impulse response characteristic is as shown in FIG.
【００２５】以上に述べた如く、本実施例ではメモリ部
にはサブナイキスト標本化した信号系列を記憶する。こ
のため、従来の方法に較べてメモリの容量を1/2に削減
したＩＰ変換の信号処理回路が実現でき、コスト低減に
顕著な効果が得られる。As described above, in the present embodiment, the sub-Nyquist-sampled signal sequence is stored in the memory unit. For this reason, a signal processing circuit for IP conversion in which the memory capacity is reduced by half compared with the conventional method can be realized, and a remarkable effect in cost reduction can be obtained.
【００２６】次に、本発明における画像信号のＩＰ変換
の信号処理回路の第２の実施例について、図４に示すブ
ロック構成図で説明する。同図の１はプリフィルタ、２
はダウンサンプル部、３はアップサンプル部、４はポス
トフィルタ、５は１Ｈ遅延、６,８は加算部、７は動き
係数加重部、９は１フィ−ルド遅延、１０は減算部、１
１は動き検出部、１２はＭＡＸ選択部、１３はα加重
部、２２は遅延部である。Next, a second embodiment of a signal processing circuit for IP conversion of an image signal according to the present invention will be described with reference to a block diagram shown in FIG. 1 is a prefilter, 2
Is a down sampling section, 3 is an up sampling section, 4 is a post filter, 5 is a 1H delay, 6, 8 is an addition section, 7 is a motion coefficient weighting section, 9 is a 1 field delay, 10 is a subtraction section,
1 is a motion detecting unit, 12 is a MAX selecting unit, 13 is an α weighting unit, and 22 is a delay unit.
【００２７】飛び越し走査系の画像信号の輝度信号Yの
一方は、プリフィルタ１に入力し、サブナイキスト標本
化で折り返し歪となる水平垂直の高域成分を除去する。
ダウンサンプル部２は、標本点の2:1のサブサンプリン
グ処理を行い、サブナイキスト標本化した信号系列を生
成する。この輝度信号Yの他方は、遅延部２２で時間遅
延を調整し、伝送走査線信号系列の輝度信号YMとして出
力する。One of the luminance signals Y of the image signal of the interlaced scanning system is input to the pre-filter 1 to remove horizontal and vertical high-frequency components that are aliasing distortions by sub-Nyquist sampling.
The down-sampling unit 2 performs a 2: 1 sub-sampling process on the sampling points to generate a signal sequence that is sub-Nyquist-sampled. The other of the luminance signals Y is adjusted in time delay by the delay unit 22, and is output as a luminance signal YM of a transmission scanning line signal sequence.
【００２８】アップサンプル部３は、標本点の2:1のア
ップサンプリング処理を行う。そして、サブナイキスト
標本化で抜けた標本点には零の信号を挿入する。ポスト
フィルタ４は、サブナイキスト標本化で抜けた標本点の
信号を、近傍の標本点の信号で補間する信号処理を行
い、入力と同じ標本点構造の輝度信号を再生する。The up-sampling section 3 performs a 2: 1 up-sampling process on the sample points. Then, a zero signal is inserted into the sample points that have been missed in the sub-Nyquist sampling. The post filter 4 performs signal processing for interpolating the signal of the sample point that has been dropped by the sub-Nyquist sampling with the signal of the nearby sample point, and reproduces the luminance signal having the same sample point structure as the input.
【００２９】この再生した信号と、１Ｈ遅延５で１ライ
ン期間遅延させた信号は、加算部６で信号加算と係数値
1/2の加重を行い、フィ−ルド内補間による動画像に適
した補間信号を生成する。The reproduced signal and the signal delayed by one line period by the 1H delay 5 are subjected to signal addition and coefficient value in the adder 6.
A weight of 1/2 is applied to generate an interpolation signal suitable for a moving image by intra-field interpolation.
【００３０】また、メモリ部９で１フィ−ルド期間相当
(263H)遅延させたサブナイキスト標本化の信号系列は、
アップサンプル部３、ポストフィルタ４で復号処理を行
い、１フィ−ルド前の輝度信号を再生し、フィ−ルド間
補間の静止画像に適した補間信号を生成する。Also, the memory unit 9 corresponds to one field period.
(263H) The signal sequence of the delayed sub-Nyquist sampling is
The decoding processing is performed by the up-sampling unit 3 and the post filter 4, and the luminance signal one field before is reproduced to generate an interpolation signal suitable for a still image of the inter-field interpolation.
【００３１】更に、メモリ部９で１フィ−ルド期間相当
(262H)遅延させた１フレ−ム前のサブナイキスト標本化
の信号系列と、現フレ−ムのサブナイキスト標本化の信
号系列は、減算部１０で減算演算を行い、１フレ−ム間
の差分信号を検出する。動き検出部１１は、この差分信
号の絶対値の大小に応じて、0から1までの値の動き情報
係数を設定する。動きの検出漏れを回避するため、ＭＡ
Ｘ選択部１２で、１フィ−ルド前の動きの情報も使用し
て、最終的な動き係数Kを設定する。すなわち、α加重
部１３で係数α(0<α<1)を加重した信号をメモリ部９で
１フィ−ルド期間相当(262H)遅延させた信号、更に１Ｈ
遅延５で１ライン期間遅延させた信号(ト−タル263Hの
遅延)と、動き情報係数の間で、最大値を検出し、この
最大値を最終的な動き係数K(0≦K≦1,静止時:K=0)とし
て出力する。Further, the memory unit 9 corresponds to one field period.
(262H) The subtraction unit 10 performs a subtraction operation on the delayed sub-Nyquist sampled signal sequence one frame before and the current frame sub-Nyquist sampled signal sequence. Detect the difference signal. The motion detection unit 11 sets a motion information coefficient having a value from 0 to 1 according to the magnitude of the absolute value of the difference signal. MA to avoid motion detection omission
The X selector 12 sets the final motion coefficient K using the information of the motion one field before. That is, the signal obtained by delaying the signal obtained by weighting the coefficient α (0 <α <1) by the α weighting unit 13 by one field period (262H) in the memory unit 9 and further by 1H
A maximum value is detected between the signal (total 263H delay) delayed by one line period by the delay 5 and the motion information coefficient, and this maximum value is determined as the final motion coefficient K (0 ≦ K ≦ 1, When stationary: K = 0) is output.
【００３２】動き係数加重部７−１と７−２は、それぞ
れ係数値K、1-Kを加重し、加算部８で両者の信号を加算
して、補間走査線信号系列の輝度信号YIを生成する。The motion coefficient weighting sections 7-1 and 7-2 weight the coefficient values K and 1-K, respectively, add the two signals in the adding section 8, and generate the luminance signal YI of the interpolated scanning line signal sequence. Generate.
【００３３】飛び越し走査系の画像信号の色差信号Cに
対しては、フィ−ルド内補間で補間信号を生成する。す
なわち、信号Cを伝送走査線信号系列の色差信号CMとし
て出力するとともに、この信号と、１Ｈ遅延５で１ライ
ン期間遅延させた信号を、加算部６で信号加算と係数値
1/2の加重を行い、補間走査線信号系列の色差信号CIを
生成する。For the color difference signal C of the interlaced scanning image signal, an interpolation signal is generated by intra-field interpolation. That is, the signal C is output as the color difference signal CM of the transmission scanning line signal sequence, and this signal and the signal delayed by one line period by the 1H delay 5 are added by the adder 6 to signal addition and coefficient value.
A weight of 1/2 is applied to generate a color difference signal CI of the interpolated scanning line signal sequence.
【００３４】本実施例における各ブロック部は、前述し
た第１の実施例と同様に構成すればよく、説明は省略す
る。Each block in this embodiment may be configured in the same manner as in the first embodiment described above, and description thereof will be omitted.
【００３５】以上に述べた如く、本実施例では、従来の
方法に較べてメモリの容量を1/2に削減したＩＰ変換の
信号処理回路が実現でき、コスト低減に顕著な効果が得
られる。As described above, in this embodiment, an IP conversion signal processing circuit in which the memory capacity is reduced by half compared with the conventional method can be realized, and a remarkable effect on cost reduction can be obtained.
【００３６】次に、本発明における画像信号のＩＰ変換
の信号処理回路の第３の実施例について、図５に示すブ
ロック構成図で説明する。同図の１はプリフィルタ、２
はダウンサンプル部、３はアップサンプル部、４はポス
トフィルタ、５は１Ｈ遅延、６,８は加算部、７は動き
係数加重部、９は１フィ−ルド遅延、１０は減算部、１
１は動き検出部、１２はＭＡＸ選択部、１３はα加重
部、２２は遅延部である。Next, a third embodiment of the signal processing circuit for IP conversion of an image signal according to the present invention will be described with reference to a block diagram shown in FIG. 1 is a prefilter, 2
Is a down sampling section, 3 is an up sampling section, 4 is a post filter, 5 is a 1H delay, 6, 8 is an addition section, 7 is a motion coefficient weighting section, 9 is a 1 field delay, 10 is a subtraction section,
1 is a motion detecting unit, 12 is a MAX selecting unit, 13 is an α weighting unit, and 22 is a delay unit.
【００３７】飛び越し走査系の画像信号の輝度信号Yの
一方は、プリフィルタ１に入力し、サブナイキスト標本
化で折り返し歪となる水平垂直の高域成分を除去する。
ダウンサンプル部２は、標本点の2:1のサブサンプリン
グ処理を行い、サブナイキスト標本化した信号系列を生
成する。One of the luminance signals Y of the image signal of the interlaced scanning system is input to the pre-filter 1 to remove horizontal and vertical high-frequency components which are aliasing due to sub-Nyquist sampling.
The down-sampling unit 2 performs a 2: 1 sub-sampling process on the sampling points to generate a signal sequence that is sub-Nyquist-sampled.
【００３８】この輝度信号Yの他方は、遅延部２２で時
間遅延を調整し、伝送走査線信号系列の輝度信号YMとし
て出力する。また、この信号と、１Ｈ遅延５で１ライン
期間遅延させた信号は、加算部６で信号加算と係数値1/
2の加重を行い、フィ−ルド内補間による動画像に適し
た補間信号を生成する。The other of the luminance signals Y is adjusted in time delay by the delay section 22 and is output as a luminance signal YM of a transmission scanning line signal sequence. Further, this signal and the signal delayed by one line period by the 1H delay 5 are added by the adder 6 to the signal addition and the coefficient value 1 /.
A weight of 2 is applied to generate an interpolation signal suitable for a moving image by intra-field interpolation.
【００３９】また、サブナイキスト標本化の信号系列
は、メモリ部９で１フィ−ルド期間相当(263H)遅延さ
せ、アップサンプル部３で標本点の2:1のアップサンプ
リング処理を行う。ポストフィルタ４は、サブナイキス
ト標本化で抜けた標本点の信号を、近傍の標本点の信号
で補間する信号処理を行う。そして、１フィ−ルド前の
輝度信号を再生し、フィ−ルド間補間の静止画像に適し
た補間信号を生成する。The signal sequence of the sub-Nyquist sampling is delayed by one field period (263H) in the memory unit 9 and the up-sampling unit 3 performs a 2: 1 up-sampling process of the sampling points. The post-filter 4 performs signal processing for interpolating the signal of the sample point that has been dropped by the sub-Nyquist sampling with the signal of a nearby sample point. Then, the luminance signal one field before is reproduced, and an interpolation signal suitable for a still image of inter-field interpolation is generated.
【００４０】更に、メモリ部９で１フィ−ルド期間相当
(262H)遅延させた１フレ−ム前のサブナイキスト標本化
の信号系列と、現フレ−ムのサブナイキスト標本化の信
号系列は、減算部１０で減算演算を行い、１フレ−ム間
の差分信号を検出する。動き検出部１１は、この差分信
号の絶対値の大小に応じて、0から1までの値の動き情報
係数を設定する。動きの検出漏れを回避するため、ＭＡ
Ｘ選択部１２で、１フィ−ルド前の動きの情報も使用し
て、最終的な動き係数Kを設定する。すなわち、α加重
部１３で係数α(0<α<1)を加重した信号をメモリ部９で
１フィ−ルド期間相当(262H)遅延させた信号、更に１Ｈ
遅延５で１ライン期間遅延させた信号(ト−タル263Hの
遅延)と、動き情報係数の間で、最大値を検出し、この
最大値を最終的な動き係数K(0≦K≦1,静止時:K=0)とし
て出力する。Further, the memory section 9 corresponds to one field period.
(262H) The subtraction unit 10 performs a subtraction operation on the delayed sub-Nyquist sampled signal sequence one frame before and the current frame sub-Nyquist sampled signal sequence. Detect the difference signal. The motion detection unit 11 sets a motion information coefficient having a value from 0 to 1 according to the magnitude of the absolute value of the difference signal. MA to avoid motion detection omission
The X selector 12 sets the final motion coefficient K using the information of the motion one field before. That is, the signal obtained by delaying the signal obtained by weighting the coefficient α (0 <α <1) by the α weighting unit 13 by one field period (262H) in the memory unit 9 and further by 1H
A maximum value is detected between the signal (total 263H delay) delayed by one line period by the delay 5 and the motion information coefficient, and this maximum value is determined as the final motion coefficient K (0 ≦ K ≦ 1, When stationary: K = 0) is output.
【００４１】動き係数加重部７−１と７−２は、それぞ
れ係数値K、1-Kを加重し、加算部８で両者の信号を加算
して、補間走査線信号系列の輝度信号YIを生成する。The motion coefficient weighting sections 7-1 and 7-2 weight the coefficient values K and 1-K, respectively, add the two signals in the adding section 8, and generate the luminance signal YI of the interpolation scanning line signal sequence. Generate.
【００４２】飛び越し走査系の画像信号の色差信号Cに
対しては、フィ−ルド内補間で補間信号を生成する。す
なわち、信号Cを伝送走査線信号系列の色差信号CMとし
て出力するとともに、この信号と、１Ｈ遅延５で１ライ
ン期間遅延させた信号を、加算部６で信号加算と係数値
1/2の加重を行い、補間走査線信号系列の色差信号CIを
生成する。For the color difference signal C of the image signal of the interlaced scanning system, an interpolation signal is generated by intra-field interpolation. That is, the signal C is output as the color difference signal CM of the transmission scanning line signal sequence, and this signal and the signal delayed by one line period by the 1H delay 5 are added by the adder 6 to signal addition and coefficient value.
A weight of 1/2 is applied to generate a color difference signal CI of the interpolated scanning line signal sequence.
【００４３】本実施例における各ブロック部は、前述し
た第１の実施例と同様に構成すればよく、説明は省略す
る。Each block in this embodiment may be configured in the same manner as in the first embodiment described above, and description thereof will be omitted.
【００４４】以上に述べた如く、本実施例では、従来の
方法に較べてメモリの容量を1/2に削減したＩＰ変換の
信号処理回路が実現でき、コスト低減に顕著な効果が得
られる。As described above, in this embodiment, an IP conversion signal processing circuit in which the memory capacity is reduced by half compared with the conventional method can be realized, and a remarkable effect on cost reduction can be obtained.
【００４５】次に本発明における画像信号のフォ−マッ
ト変換の信号処理回路に関して説明する。Next, a signal processing circuit for format conversion of an image signal according to the present invention will be described.
【００４６】図６は、この第１の実施例のブロック構成
図である。図中の２３はＩＰ変換部、２４は倍速化部、
２５は選択部、２６は水平スケ−リング部、２７は垂直
スケ−リング部、２８はメモリ部、２９は画質改善部、
３０は多重部、３１はマイコン部、３２はコントロ−ル
部である。FIG. 6 is a block diagram of the first embodiment. 23 in the figure is an IP conversion unit, 24 is a double speed unit,
25 is a selection unit, 26 is a horizontal scaling unit, 27 is a vertical scaling unit, 28 is a memory unit, 29 is an image quality improvement unit,
Reference numeral 30 denotes a multiplexing unit, 31 denotes a microcomputer unit, and 32 denotes a control unit.
【００４７】入力画像信号系列S1(4:2:2系,あるいは4:
2:0系のコンポ−ネント輝度、色差信号)は、ＩＰ変換部
２３と選択部２５に入力する。The input image signal sequence S1 (4: 2: 2 system or 4:
The 2: 0 system component luminance and color difference signals) are input to the IP conversion unit 23 and the selection unit 25.
【００４８】ＩＰ変換部２３は、前述の第１乃至第３の
実施例の信号処理回路で構成し、飛び越し走査系の入力
画像信号に対して、飛び越し走査で抜けた走査線の信号
を動き適応型の補間処理で生成し、伝送走査線信号系列
SMと補間走査線信号系列SIとを出力する。The IP conversion unit 23 is composed of the signal processing circuits of the first to third embodiments described above. The IP conversion unit 23 performs motion adaptation on a signal of a scanning line which is skipped by interlaced scanning with respect to an input image signal of an interlaced scanning system. Transmission scan line signal series
An SM and an interpolated scanning line signal sequence SI are output.
【００４９】倍速化部２４は、信号系列SMとSIをそれぞ
れ水平方向に時間軸の１／２圧縮と時系列多重の信号処
理を行い、順次走査系の画像信号系列SPを出力する。The speed doubling section 24 performs signal processing of 信号 compression on the time axis and time-sequential multiplexing of the signal sequences SM and SI in the horizontal direction, respectively, and outputs an image signal sequence SP of a sequential scanning system.
【００５０】選択部２５は、入力画像信号が飛び越し走
査系の現行ＴＶ信号では信号系列SP、順次走査系のＥＤ
ＴＶ信号やパソコン画像信号およびＨＤＴＶ信号では信
号系列S1をそれぞれ選択し、これを信号系列S2に出力す
る。The selection unit 25 determines whether the input image signal is a signal sequence SP for the current TV signal of the interlaced scanning system and an ED of the progressive scanning system.
For a TV signal, a personal computer image signal, and an HDTV signal, a signal sequence S1 is selected, and this is output to a signal sequence S2.
【００５１】水平スケ−リング部２６は、Ｋ−Ｌ変換
（Ｋ個の画素をＬ個の画素に変換）の信号処理で水平拡
大（Ｋ＜Ｌ）や水平縮小（Ｋ＞Ｌ）を行い、信号系列S3
を出力する。The horizontal scaling section 26 performs horizontal enlargement (K <L) and horizontal reduction (K> L) by signal processing of KL conversion (conversion of K pixels into L pixels). Signal sequence S3
Is output.
【００５２】垂直スケ−リング部２７は、Ｋ−Ｌ変換
（Ｋ個のラインをＬ個のラインに変換）の信号処理で垂
直拡大（Ｋ＜Ｌ）や垂直縮小（Ｋ＞Ｌ）を行う。なお、
入力信号によっては、メモリ部２８のメモリの動作制御
を行い、方式変換（例えば、ＰＡＬ−ＮＴＳＣ変換）
や、同期整合の信号処理、表示系によってはＰＡＬフィ
−ルド倍速の信号処理も併せて行う。そして、フォ−マ
ット変換した画像信号系列S4を出力する。The vertical scaling section 27 performs vertical enlargement (K <L) and vertical reduction (K> L) in the signal processing of KL conversion (conversion of K lines into L lines). In addition,
Depending on the input signal, the operation of the memory of the memory unit 28 is controlled, and the format conversion (for example, PAL-NTSC conversion) is performed.
In addition, signal processing for synchronization matching and signal processing at a PAL field double speed depending on the display system are also performed. Then, the image signal sequence S4 after the format conversion is output.
【００５３】画質改善部２９は、輝度信号の黒レベル補
正、白レベル補正などの画質改善や、色空間変換などの
信号処理を行い、３原色ＲＧＢ信号に変換する。また、
表示系がリニア特性のディスプレイでは、逆γ変換の信
号処理を行う。そして、３原色画像信号系列S5を出力す
る。The image quality improving unit 29 performs image processing such as black level correction and white level correction of a luminance signal and signal processing such as color space conversion, and converts the signal into three primary color RGB signals. Also,
In a display having a linear display system, signal processing of inverse γ conversion is performed. Then, a three-primary-color image signal sequence S5 is output.
【００５４】多重部３０は、信号系列S5にマルチ画面表
示（例えば、２画面表示、ＰＩＰ表示、マルチウィンド
表示など）のための３原色画像信号系列S7を多重する信
号処理を行う。そして、表示系のフォ−マットに合致し
た画像信号系列S6を出力する。The multiplexing section 30 performs signal processing for multiplexing the signal sequence S5 with a three primary color image signal sequence S7 for multi-screen display (for example, two-screen display, PIP display, multi-window display, etc.). Then, an image signal sequence S6 matching the display system format is output.
【００５５】マイコン部３１は、画像情報信号SPI（入
力画像信号の種類、表示系のフォ−マット、画面表示の
モ−ドなどの情報）をもとに、各ブロック部における信
号処理のパラメタを設定する。The microcomputer unit 31 converts the signal processing parameters in each block unit based on the image information signal SPI (information such as the type of input image signal, display system format, and screen display mode). Set.
【００５６】コントロ−ル部３２は、各ブロック部にお
ける信号処理に必要な同期信号や、制御信号や、クロッ
ク信号などを生成する。また、マルチ画面表示の際の同
期整合処理に必要な情報SDを出力する。The control section 32 generates a synchronization signal, a control signal, a clock signal, and the like necessary for signal processing in each block section. Also, it outputs information SD necessary for the synchronization matching process at the time of multi-screen display.
【００５７】以下では、各ブロック部の実施形態につい
て説明する。Hereinafter, embodiments of each block will be described.
【００５８】倍速化部の一構成例図を図７に示す。同図
(a)は構成、(b)はラインメモリの動作である。FIG. 7 shows an example of the structure of the speed doubling section. Same figure
(a) shows the configuration, and (b) shows the operation of the line memory.
【００５９】伝送走査線信号系列の信号SM(Y),SM(C)は
ラインメモリ３３−１、補間走査線信号系列の信号SI
(Y),SI(C)はラインメモリ３３−２に、同図(b)に示す書
き込み動作(以下WT動作と略称)で、飛び越し走査系の動
作速度で１ライン期間の信号を記憶する。The signals SM (Y) and SM (C) of the transmission scanning line signal series are stored in the line memory 33-1 and the interpolation scanning line signal series signal SI.
(Y) and SI (C) store signals for one line period in the line memory 33-2 at the operation speed of the interlaced scanning system in the write operation (hereinafter abbreviated as WT operation) shown in FIG.
【００６０】ラインメモリからの読出し動作(以下RD動
作と略称)は、順次走査系の動作速度で１ライン期間
（飛び越し走査系の1/2の時間）で、ラインメモリ３３
−１と３３−２とを交互に読み出す。そして、多重部３
４で時系列に多重し、その出力に順次走査系の画像信号
系列の輝度信号SP(Y)と、色差信号SP(C)とを得る。The read operation from the line memory (hereinafter abbreviated as RD operation) is performed in one line period (1/2 time of the interlaced scan system) at the operation speed of the sequential scan system.
-1 and 33-2 are alternately read. And the multiplexing unit 3
In step 4, the signals are multiplexed in a time series, and a luminance signal SP (Y) and a color difference signal SP (C) of an image signal sequence of a sequential scanning system are obtained at the output.
【００６１】次に、図８に水平スケ−リング部の一構成
例を示す。同図(a)は構成を示し、図中の３５は水平Ｌ
ＰＦ、３６,４０,４２,４３はスイッチ、３７は１画素
遅延、３８は係数加重部、３９は加算部、４１は１Ｈメ
モリである。また、同図(b)は、各種信号処理における
スイッチ類の選択制御を示す。Next, FIG. 8 shows an example of the configuration of the horizontal scaling section. FIG. 3A shows the configuration, in which 35 is a horizontal L
PF, 36, 40, 42, 43 are switches, 37 is one pixel delay, 38 is a coefficient weighting section, 39 is an addition section, and 41 is a 1H memory. FIG. 2B shows selection control of switches in various signal processing.
【００６２】水平縮小の信号処理では、SW1,SW2,SW4は
端子a、SW3は端子bに接続する。そして、順次走査系の
画像信号の輝度信号S2(Y)は、まず、縮小処理で折り返
し歪となる水平高域周波数成分を除去するため、水平Ｌ
ＰＦ３５で低域通過の周波数特性で帯域制限を行う。次
に、１画素遅延３７と係数加重部３８と加算部３９とで
構成する演算部で、２点線形補間の特性による画素のＫ
−Ｌ変換（Ｋ＞Ｌ）の演算を行う。すなわち、入力信号
と、１画素遅延３７で１画素遅延した信号に対し、係数
加重部３８では係数値β,1-βを加重し、加算部３９で
両者を加算し、この出力にＫ−Ｌ変換でＫ画素から生成
したＬ画素の信号を得る。なお、β,1-βは、Ｋ画素を
周期に画素毎に変化する。１Ｈメモリ４１では、間欠的
なWT動作でこのＬ画素の信号を記憶する。そして、RD動
作で連続的に信号の読出しを行う。そして、４３のＳＷ
４の出力に、L/K倍に水平縮小した信号系列S3(Y)を得
る。In signal processing for horizontal reduction, SW1, SW2, and SW4 are connected to a terminal a, and SW3 is connected to a terminal b. Then, the luminance signal S2 (Y) of the image signal of the progressive scanning system is first converted to a horizontal L level in order to remove a horizontal high frequency component which is aliasing in the reduction processing.
The band is limited by the PF 35 using the low-pass frequency characteristics. Next, an arithmetic unit composed of a one-pixel delay 37, a coefficient weighting unit 38, and an adding unit 39 calculates the K
Perform an operation of -L conversion (K> L). That is, the coefficient weighting section 38 weights the coefficient value β, 1−β with respect to the input signal and the signal delayed by one pixel by the one-pixel delay 37, and adds the two in the addition section 39. The signal of the L pixel generated from the K pixel by the conversion is obtained. Note that β, 1-β changes for each pixel in a cycle of K pixels. The 1H memory 41 stores the signal of this L pixel by intermittent WT operation. Then, the signal is continuously read out by the RD operation. And 43 SW
4, a signal sequence S3 (Y) horizontally reduced by L / K times is obtained.
【００６３】水平拡大の信号処理では、SW1,SW2は端子
b、SW3,SW4は端子aに接続する。そして、順次走査系の
画像信号の輝度信号S2(Y)は、まず、１Ｈメモリ４１
に、WT動作で連続的に信号を記憶する。そして、RD動作
では一部期間で２度読み出しの動作を行い、Ｌ画素の期
間でＫ個の画素の信号を読み出す。次に、１画素遅延３
７と係数加重部３８と加算部３９とで構成する演算部
で、２点線形補間の特性による画素のＫ−Ｌ変換（Ｋ＜
Ｌ）の演算を行う。すなわち、入力信号と、１画素遅延
３７で１画素遅延した信号に対し、係数加重部３８では
係数値β,1-βを加重し、加算部３９で両者を加算し、
この出力にＫ−Ｌ変換でＫ画素から生成したＬ画素の信
号を得る。なお、β,1-βは、Ｌ画素を周期に画素毎に
変化する。そして、４３のＳＷ４の出力に、L/K倍に水
平拡大した信号系列S3(Y)を得る。In the horizontal expansion signal processing, SW1 and SW2 are connected to terminals.
b, SW3, SW4 are connected to terminal a. Then, the luminance signal S2 (Y) of the progressive scanning image signal is
Next, the signal is continuously stored by the WT operation. In the RD operation, a read operation is performed twice in a partial period, and signals of K pixels are read in a period of L pixels. Next, one pixel delay 3
7; a coefficient weighting unit 38; and an adding unit 39. The calculating unit includes a KL conversion (K <K <
L) is calculated. That is, the coefficient weighting unit 38 weights the coefficient value β, 1−β with respect to the input signal and the signal delayed by one pixel by the one-pixel delay 37, and adds the two in the addition unit 39,
An L pixel signal generated from K pixels by KL conversion is obtained from this output. Note that β, 1-β changes for each pixel in a cycle of L pixels. Then, a signal sequence S3 (Y) horizontally expanded L / K times is obtained at the output of SW4 43.
【００６４】スル−の信号処理では、SW4を端子bに接続
する。そして、４３のＳＷ４の出力に、縮小拡大の処理
を行わない信号系列S3(Y)を得る。In the through signal processing, SW4 is connected to the terminal b. Then, a signal sequence S3 (Y) not subjected to the reduction / enlargement processing is obtained at the output of SW4 of 43.
【００６５】順次走査系の画像信号の色差信号S2(C)に
対しても、輝度信号と同一の構成による信号処理を行
い、水平縮小、水平拡大あるいはスル−の信号系列S3
(C)を得る。The color difference signal S2 (C) of the progressive scanning image signal is also subjected to signal processing having the same configuration as that of the luminance signal, and is subjected to horizontal reduction, horizontal expansion or through signal series S3.
Obtain (C).
【００６６】次に、図９に垂直スケ−リング部の一構成
例を示す。同図(a)は構成を示し、図中の４４は垂直Ｌ
ＰＦ、４５,４９,５０,５１はスイッチ、４６は１ライ
ン遅延、４７は係数加重部、４８は加算部、２８はメモ
リ部である。また、同図(b)は、各種信号処理における
スイッチ類の選択制御を示す。Next, FIG. 9 shows an example of the configuration of the vertical scaling section. FIG. 11A shows the configuration, and reference numeral 44 in the figure denotes a vertical L
PF, 45, 49, 50, and 51 are switches, 46 is a one-line delay, 47 is a coefficient weighting unit, 48 is an addition unit, and 28 is a memory unit. FIG. 2B shows selection control of switches in various signal processing.
【００６７】垂直縮小の信号処理では、SW1,SW2,SW4は
端子a、SW3は端子bに接続する。そして、順次走査系の
画像信号の輝度信号S3(Y)は、まず、縮小処理で折り返
し歪となる垂直高域周波数成分を除去するため、垂直Ｌ
ＰＦ４４で低域通過の周波数特性で帯域制限を行う。次
に、１ライン遅延４６と係数加重部４７と加算部４８と
で構成する演算部で、２点線形補間の特性によるライン
のＫ−Ｌ変換（Ｋ＞Ｌ）の演算を行う。すなわち、入力
信号と、１ライン遅延４６で１ライン遅延した信号に対
し、係数加重部４７では係数値β,1-βを加重し、加算
部４８で両者を加算し、この出力にＫ−Ｌ変換でＫライ
ンから生成したＬラインの信号を得る。なお、β,1-β
は、Ｋラインを周期にライン毎に変化する。メモリ部２
８のM-1では、図１０(a)に示す様に、１フィ−ルド期間
を周期にWT動作、RD動作を行う。WT動作では、Ｋ−Ｌ変
換で生成した信号を間欠的に書き込み記憶する。一方、
RD動作では(1-L/K)フィ−ルド期間遅れた時点より連続
的に信号を読み出す。そして、５１のＳＷ４の出力に、
L/K倍に垂直縮小した信号系列S4(Y)を得る。以上に述べ
た垂直縮小の信号処理に必要なメモリ容量は、(1-L/K)
フィ−ルド期間分あればよい。In signal processing for vertical reduction, SW1, SW2, and SW4 are connected to a terminal a, and SW3 is connected to a terminal b. Then, the luminance signal S3 (Y) of the image signal of the progressive scanning system is first converted into a vertical L signal in order to remove a vertical high frequency component which is aliasing in the reduction processing.
The PF 44 limits the band with the low-pass frequency characteristics. Next, an operation unit including a one-line delay 46, a coefficient weighting unit 47, and an addition unit 48 performs an operation of KL conversion (K> L) of a line based on characteristics of two-point linear interpolation. That is, the coefficient weighting section 47 weights the coefficient values β and 1−β with respect to the input signal and the signal delayed by one line by the one-line delay 46, adds the two to each other in the adding section 48, and outputs the KL to the output. The signal of the L line generated from the K line by the conversion is obtained. Note that β, 1-β
Changes every line in a cycle of K lines. Memory part 2
In M-1 of FIG. 8, as shown in FIG. 10A, the WT operation and the RD operation are performed in a cycle of one field period. In the WT operation, a signal generated by the KL conversion is intermittently written and stored. on the other hand,
In the RD operation, a signal is continuously read from a point in time delayed by (1-L / K) field period. And, to the output of SW4 of 51,
A signal sequence S4 (Y) vertically reduced L / K times is obtained. The memory capacity required for the vertical reduction signal processing described above is (1-L / K)
It only has to be for the field period.
【００６８】垂直拡大の信号処理では、SW1,SW2は端子
b、SW3,SW4は端子aに接続する。メモリ部２８のM-1で
は、図１０(b)に示す様に、１フィ−ルド期間を周期と
するWT動作、RD動作を行う。そして、順次走査系の画像
信号の輝度信号S3(Y)は、まず、WT動作で連続的に信号
を記憶する。一方、RD動作では一部期間で２度読み出し
の動作を行いＫラインの期間にＬラインの信号を読み出
す。次に、１ライン遅延４６と係数加重部４７と加算部
４８とで構成する演算部で、２点線形補間の特性による
ラインのＬ−Ｋ変換（Ｌ＜Ｋ）の演算を行う。すなわ
ち、入力信号と、１ライン遅延４６で１ライン遅延した
信号に対し、係数加重部４７では係数値β,1-βを加重
し、加算部４８で両者を加算し、この出力にＬ−Ｋ変換
でＬラインから生成したＫラインの信号を得る。なお、
β,1-βは、Ｋラインを周期にライン毎に変化する。そ
して、５１のＳＷ４の出力に、K/L倍に垂直拡大した信
号系列S4(Y)を得る。以上に述べた垂直拡大の信号処理
に必要なメモリ容量は、(1-L/K)フィ−ルド期間分あれ
ばよい。In the vertical magnification signal processing, SW1 and SW2 are connected to terminals.
b, SW3, SW4 are connected to terminal a. As shown in FIG. 10B, the M-1 of the memory unit 28 performs the WT operation and the RD operation with a period of one field period. Then, as the luminance signal S3 (Y) of the image signal of the progressive scanning system, first, the signal is continuously stored by the WT operation. On the other hand, in the RD operation, a read operation is performed twice in a partial period, and a signal on the L line is read in a period on the K line. Next, an arithmetic unit including a one-line delay 46, a coefficient weighting unit 47, and an adding unit 48 performs an LK conversion (L <K) of a line based on the characteristics of two-point linear interpolation. That is, the coefficient weighting unit 47 weights the coefficient values β and 1-β with respect to the input signal and the signal delayed by one line by the one-line delay 46, and adds the two in the addition unit 48. The signal of the K line generated from the L line by the conversion is obtained. In addition,
β, 1-β changes every line in a cycle of K lines. Then, a signal sequence S4 (Y) vertically expanded by K / L times is obtained at the output of SW4 51. The memory capacity required for the above-described vertical expansion signal processing may be sufficient for the (1-L / K) field period.
【００６９】ＰＡＬフィ−ルド倍速の信号処理は、順次
走査系に変換したＰＡＬ信号（以下625/50/1:1と略称）
を100フィ−ルド／秒の飛び越し走査系の信号（以下625
/100/2:1と略称）に変換するもので、SW2,SW3を端子b、
SW4を端子aに接続して実現する。メモリ部２８のM-1で
は、図１０(c)に示す様なWT動作、RD動作を行う。順次
走査系のＰＡＬ信号の輝度信号S3(Y)は、１フィ−ルド
期間を周期に、WT動作で連続的に信号を記憶する。一
方、RD動作では、0.5フィ−ルド期間遅れた時点から、
順次走査系の奇数走査線の信号系列（図中の○-O）、偶
数走査線の信号系列（図中の○-E）の順に信号の読出し
を行う。そして、５１のＳＷ４の出力に、ＰＡＬフィ−
ルド倍速した信号系列S4(Y)を得る。以上に述べたＰＡ
Ｌフィ−ルド倍速の信号処理に必要なメモリ容量は、0.
5フィ−ルド期間分あればよい。The PAL field double-speed signal processing is performed on a PAL signal (hereinafter abbreviated as 625/50/1: 1) converted into a sequential scanning system.
To a 100-field / second interlaced scanning signal (hereafter 625
/ 100/2: 1), with SW2 and SW3 connected to terminal b,
This is realized by connecting SW4 to terminal a. In M-1 of the memory unit 28, the WT operation and the RD operation as shown in FIG. The luminance signal S3 (Y) of the PAL signal of the progressive scanning system is continuously stored by the WT operation with a period of one field period. On the other hand, in the RD operation, after a delay of 0.5 field period,
The signals are read out in the order of the signal sequence of the odd-numbered scanning lines (○ -O in the figure) and the signal sequence of the even-numbered scanning lines (○ -E in the figure) of the progressive scanning system. The PAL filter is output to the output of SW4 51.
Thus, a signal sequence S4 (Y) doubled in speed is obtained. PA mentioned above
The memory capacity required for L-field double-speed signal processing is 0.
It suffices for 5 field periods.
【００７０】ＮＴＳＣ−ＰＡＬフィ−ルド倍速の信号処
理は、順次走査系に変換したＮＴＳＣ信号（以下525/60
/1:1と略称）を625/100/2:1系の信号に変換するもの
で、SW1,SW2を端子b、SW3を端子c、SW4を端子aに接続し
て実現する。順次走査系のＮＴＳＣ信号の輝度信号S3
(Y)は、図１０(d)に示す様に、メモリ部のM-1に、ＮＴ
ＳＣ１フィ−ルド期間を周期とするWT動作で、連続的に
信号を記憶する。一方、RD動作では、ＰＡＬ１フィ−ル
ド期間を周期に、一部期間で２度読み出しの動作を行い
６ラインの期間に５ラインの信号を読み出す。次に、１
ライン遅延４６と係数加重部４７と加算部４８とで構成
する演算部で、２点線形補間の特性によるラインの５−
６変換の演算で垂直拡大を行う。すなわち、入力信号
と、１ライン遅延４６で１ライン遅延した信号に対し、
係数加重部４７では係数値β,1-βを加重し、加算部４
８で両者を加算し、この出力に５−６変換で５ラインか
ら生成した６ラインの信号を得る。なお、β,1-βは、
６ラインを周期にライン毎に変化する。メモリ部２８の
M-2では、ＰＡＬ１フィ−ルド期間を周期に、WT動作で
連続的にこの信号を記憶する。一方、RD動作では、0.5
フィ−ルド期間遅れた時点から、順次走査系の奇数走査
線の信号系列（図中の○-O）、偶数走査線の信号系列
（図中の○-E）の順に信号の読出しを行う。そして、５
１のＳＷ４の出力に、ＮＴＳＣ−ＰＡＬフィ−ルド倍速
した信号系列S4(Y)を得る。以上に述べたＮＴＳＣ−Ｐ
ＡＬフィ−ルド倍速の信号処理に必要なメモリ容量は、
ＮＴＳＣ−ＰＡＬ変換に1フィ−ルド期間分、フィ−ル
ド倍速変換に0.5フィ−ルド期間分あればよい。The signal processing at the NTSC-PAL field double speed is performed by an NTSC signal (hereinafter referred to as 525/60) converted to a progressive scanning system.
/ 1: 1) is converted to a 625/100/2: 1 system signal. SW1 and SW2 are connected to terminal b, SW3 is connected to terminal c, and SW4 is connected to terminal a. The luminance signal S3 of the NTSC signal of the progressive scanning system
(Y), as shown in FIG. 10 (d), NT
Signals are continuously stored in a WT operation having a cycle of the SC1 field period. On the other hand, in the RD operation, a read operation is performed twice in a partial period with a period of the PAL1 field period, and signals of five lines are read in a period of six lines. Then, 1
An arithmetic unit composed of a line delay 46, a coefficient weighting unit 47, and an adding unit 48.
The vertical enlargement is performed by the calculation of 6 conversion. That is, for the input signal and the signal delayed by one line by the one-line delay 46,
The coefficient weighting section 47 weights the coefficient values β, 1-β,
At step 8, the signals are added, and a signal of 6 lines generated from 5 lines by 5-6 conversion is obtained from the output. Note that β, 1-β is
It changes every line every six lines. Of the memory unit 28
In M-2, this signal is continuously stored in the WT operation with the PAL1 field period as a cycle. On the other hand, in RD operation, 0.5
From the time when the field period is delayed, the signals are read out in the order of the signal sequence of the odd-numbered scanning lines (○ -O in the drawing) and the signal sequence of the even-numbered scanning lines (○ -E in the drawing) of the sequential scanning system. And 5
1, a signal sequence S4 (Y) at NTSC-PAL field double speed is obtained at the output of SW4. NTSC-P described above
The memory capacity required for AL field double speed signal processing is
It is sufficient that one field period is used for NTSC-PAL conversion and 0.5 field period is used for double-speed field conversion.
【００７１】ＰＡＬ−ＮＴＳＣ変換の信号処理は、625/
50/1:1系の信号を525/60/1:1系の信号に変換するもの
で、SW1,SW2を端子a、SW3を端子b、SW4を端子aに接続し
て実現する。順次走査系のＰＡＬ信号の輝度信号S3(Y)
は、垂直ＬＰＦ４４で低域通過の周波数特性で帯域制限
を行う。次に、１ライン遅延４６と係数加重部４７と加
算部４８とで構成する演算部で、２点線形補間の特性に
よるラインの６−５変換の演算で垂直縮小を行う。すな
わち、入力信号と、１ライン遅延４６で１ライン遅延し
た信号に対し、係数加重部４７では係数値β,1-βを加
重し、加算部４８で両者を加算し、この出力に６−５変
換で６ラインから生成した５ラインの信号を得る。な
お、β,1-βは、６ラインを周期にライン毎に変化す
る。メモリ部２８のM-1では、図１０(e)に示す様に、Ｐ
ＡＬ１フィ−ルド期間を周期とするWT動作で、６−５変
換で生成した信号を間欠的に書き込み記憶する。一方、
RD動作ではＮＴＳＣ１フィ−ルド期間を周期に信号を読
み出す。そして、５１のＳＷ４の出力に、ＰＡＬ−ＮＴ
ＳＣ変換した信号系列S4(Y)を得る。以上に述べたＰＡ
Ｌ−ＮＴＳＣ変換の信号処理に必要なメモリ容量は、１
フィ−ルド期間分あればよい。The signal processing of the PAL-NTSC conversion is 625 /
It converts 50/1: 1 system signals to 525/60/1: 1 system signals, and is realized by connecting SW1 and SW2 to terminal a, SW3 to terminal b, and SW4 to terminal a. Luminance signal S3 (Y) of PAL signal of progressive scanning system
Performs band limitation with a low-pass frequency characteristic by the vertical LPF 44. Next, an operation unit including a one-line delay 46, a coefficient weighting unit 47, and an addition unit 48 performs vertical reduction by an operation of 6-5 conversion of a line based on characteristics of two-point linear interpolation. That is, the coefficient weighting section 47 weights the coefficient values β and 1-β with respect to the input signal and the signal delayed by one line by the one-line delay 46, and adds the two at the adding section 48. The signal of five lines generated from six lines by conversion is obtained. Note that β, 1-β changes every line in a cycle of six lines. In M-1 of the memory unit 28, as shown in FIG.
The signal generated by the 6-5 conversion is intermittently written and stored in the WT operation having a cycle of the AL1 field period. on the other hand,
In the RD operation, a signal is read in a cycle of the NTSC1 field period. Then, PAL-NT is output to the output of SW4 51.
An SC-converted signal sequence S4 (Y) is obtained. PA mentioned above
The memory capacity required for signal processing of L-NTSC conversion is 1
It only has to be for the field period.
【００７２】スル−の信号処理では、SW4を端子bに接続
する。そして、５１のＳＷ４の出力に、縮小拡大の処理
を行わない信号系列S4(Y)を得る。In the through signal processing, SW4 is connected to the terminal b. Then, a signal sequence S4 (Y) that does not undergo reduction / enlargement processing is obtained at the output of SW4 51.
【００７３】順次走査系の画像信号の色差信号S3(C)に
対しても、輝度信号と同一の構成による信号処理を行
い、垂直縮小、垂直拡大、ＰＡＬフィ−ルド倍速変換、
ＮＴＳＣ−ＰＡＬフィ−ルド倍速変換、ＰＡＬ−ＮＴＳ
Ｃ変換あるいはスル−の信号系列S4(C)を得る。The color difference signal S3 (C) of the progressive scanning image signal is also subjected to signal processing with the same configuration as that of the luminance signal to reduce the vertical scale, the vertical scale, the PAL field double speed conversion,
NTSC-PAL field double speed conversion, PAL-NTS
A C-converted or through signal sequence S4 (C) is obtained.
【００７４】以上に述べた様に、垂直スケ−リング部で
は、極めて少ないメモリ容量で、フォ−マット変換に必
要な各種の信号処理を行うことができる。As described above, the vertical scaling section can perform various signal processing required for format conversion with an extremely small memory capacity.
【００７５】次に、水平スケ−リング部や垂直スケ−リ
ング部で使用する２点線形補間の特性のＫ−Ｌ変換の代
表的な例を図１１に示す。同図(a)の４−３変換は、後
述する図１３のノ−マルモ−ドで使用する。図中のマト
リクスは、４点の入力系列X1,X2,X3,X4と、３点の出力
系列Y1,Y2,Y3との対応関係を示す。従って、前述した演
算部では、係数値(β,1-β)は(1,0),(2/3,1/3),(1/3,2/
3)と変化し、出力系列を生成する。また、同図(b)の３
−４変換は、後述する図１３のシネマモ−ドで使用す
る。この場合は、４点の入力系列X1,X2,X3,X4(但し、X4
は次の入力系列のX1にも使用)と、４点の出力系列Y1,Y
2,Y3,Y4との対応関係が、同図に示すマトリクスで表さ
れる。従って、前述した演算部では、係数値(β,1-β)
は(0,1),(1/4,3/4),(2/4,2/4),(3/4,1/4)と変化し、出
力系列を生成する。一方、同図(c)は前述のＰＡＬ−Ｎ
ＴＳＣ変換に使用する６−５変換、同図(d)は前述のＮ
ＴＳＣ−ＰＡＬ変換に使用する５−６変換の例である。Next, FIG. 11 shows a typical example of the KL conversion of the characteristics of two-point linear interpolation used in the horizontal scaling unit and the vertical scaling unit. The 4-3 conversion shown in FIG. 9A is used in a normal mode shown in FIG. The matrix in the figure shows the correspondence between four input sequences X1, X2, X3, and X4 and three output sequences Y1, Y2, and Y3. Therefore, in the above-described calculation unit, the coefficient values (β, 1-β) are (1, 0), (2/3, 1/3), (1/3, 2 /
3) to generate an output sequence. Also, 3 in FIG.
The -4 conversion is used in the cinema mode shown in FIG. In this case, the input sequence of four points X1, X2, X3, X4 (however, X4
Is also used for X1 of the next input series) and four output series Y1, Y
The correspondence between 2, 2, Y3, and Y4 is represented by a matrix shown in FIG. Therefore, in the above-described calculation unit, the coefficient value (β, 1−β)
Changes to (0, 1), (1/4, 3/4), (2/4, 2/4), (3/4, 1/4) to generate an output sequence. On the other hand, FIG.
The 6-5 conversion used for the TSC conversion, FIG.
It is an example of 5-6 conversion used for TSC-PAL conversion.
【００７６】次に、画質改善部の一構成例を図１２に示
す。フォ−マット変換処理した画像信号系列の輝度信号
S4(Y)は、輝度処理部５２に入力して輪郭補正や黒レベ
ル補正や白レベル補正の信号処理を行う。また、フォ−
マット変換処理した画像信号系列の色差信号S4(C)は、
画素補間部５３に入力し、輝度信号と同じ標本点の構造
を有する色差信号U,Vに復調する信号処理を行う。色空
間変換部５４は、輝度色差系から３原色ＲＧＢ系への変
換処理を行う。また、逆γ処理部５５は、リニアな特性
を有する表示系のための逆ガンマ補正の信号処理を行
う。選択部５６は、ＣＲＴなどのガンマ特性を有する表
示系では色空間変換部の信号、ＬＣＤやＰＤＰなどリニ
アな特性の表示系では逆γ処理部の信号を選択し、３原
色画像信号系列S5として出力する。Next, an example of the configuration of the image quality improving section is shown in FIG. Luminance signal of image signal sequence after format conversion processing
S4 (Y) is input to the luminance processing unit 52 to perform signal processing for contour correction, black level correction, and white level correction. Also,
The color difference signal S4 (C) of the image signal sequence subjected to the matte conversion processing is
The signal is input to the pixel interpolator 53 and subjected to signal processing for demodulation into color difference signals U and V having the same sampling point structure as the luminance signal. The color space conversion unit 54 performs a conversion process from a luminance color difference system to a three primary color RGB system. Further, the inverse γ processing unit 55 performs inverse gamma correction signal processing for a display system having linear characteristics. The selection unit 56 selects a signal of a color space conversion unit in a display system having a gamma characteristic such as a CRT, and a signal of an inverse γ processing unit in a display system of a linear characteristic such as an LCD or a PDP. Output.
【００７７】次に、フォ−マット変換での代表的な画像
処理の一例を図１３に示す。同図(a)は、アスペクト比1
6:9の画面にアスペクト比4:3の画像を表示するため、画
像を水平に圧縮するもので、ノ−マルモ−ドと略称す
る。同図(b)は、レタ−ボックス画像をアスペクト比16:
9の画面に表示するため、画像を垂直に拡大するもの
で、シネマモ−ドと略称する。同図(c)は、アスペクト
比4:3の画像の左右を徐々に拡大し、アスペクト比16:9
の画面一杯に表示するもので、スム−ズワイドと略称す
る。同図(d)は、水平に圧縮したアスペクト比4:3の画像
を、アスペクト比16:9の画面一杯に表示するもので、フ
ルモ−ドと略称する。同図(e)は、水平垂直方向に任意
の倍率で圧縮して表示するものである。また、同図(f)
は、水平垂直方向に任意の倍率で拡大して表示（ズ−ム
モ−ドと略称）するものである。Next, an example of typical image processing in format conversion is shown in FIG. FIG. 3A shows an aspect ratio of 1.
In order to display an image having an aspect ratio of 4: 3 on a 6: 9 screen, the image is compressed horizontally, and is abbreviated as normal mode. FIG. 4B shows a letter box image having an aspect ratio of 16:
The image is vertically enlarged to be displayed on the screen 9 and is abbreviated as cinema mode. In the figure (c), the left and right sides of an image with an aspect ratio of 4: 3 are gradually enlarged, and the aspect ratio is 16: 9.
And is abbreviated as smooth wide. FIG. 1 (d) shows a horizontally compressed image with an aspect ratio of 4: 3, which is displayed on the entire screen with an aspect ratio of 16: 9, and is abbreviated as full mode. FIG. 11E shows a display compressed at an arbitrary magnification in the horizontal and vertical directions. Also, FIG.
Is to enlarge and display at an arbitrary magnification in the horizontal and vertical directions (abbreviated as zoom mode).
【００７８】次に、本実施例のフォ−マット変換の信号
処理回路で行う信号処理の概略を、代表的な表示系を例
に、図１４、図１５、図１６に纏めて示す。Next, the outline of the signal processing performed by the signal processing circuit for format conversion of this embodiment is shown in FIGS. 14, 15 and 16 by taking a typical display system as an example.
【００７９】図１４は、525/60/1:1,アスペクト比16:9
の表示系に対するＩＰ変換部、水平、垂直スケ−リング
部での信号処理の内容である。FIG. 14 shows 525/60/1: 1, aspect ratio 16: 9.
5 shows the contents of signal processing in the IP conversion unit and the horizontal and vertical scaling units for the display system of FIG.
【００８０】525/60/2:1系（現行ＮＴＳＣ方式に相当）
の入力信号は、ＩＰ変換部で順次走査に変換した信号に
対して、各種表示モ−ドに対応したフォ−マット変換を
行う。525/60/2: 1 system (corresponding to the current NTSC system)
The input signal is subjected to format conversion corresponding to various display modes with respect to the signal converted into the sequential scanning by the IP conversion unit.
【００８１】525/60/1:1系（ＥＤＴＶ方式に相当）の入
力信号は、順次走査系であるのでＩＰ変換は行わず、表
示モ−ドに応じて、スル−、拡大、縮小の処理を行う。The input signal of the 525/60/1: 1 system (corresponding to the EDTV system) is a progressive scanning system, so that IP conversion is not performed, and through, enlargement, and reduction processing is performed according to the display mode. I do.
【００８２】1125/60/2:1系（ＨＤＴＶに相当）の入力
信号は、垂直スケ−リング部で１７−１６変換を行い、
飛び越し走査系から順次走査系に変換する。また、表示
モ−ドに応じて、拡大、縮小の処理を行う。An input signal of the 1125/60/2: 1 system (corresponding to HDTV) is subjected to 17-16 conversion in a vertical scaling section,
Conversion is performed from the interlaced scanning system to the sequential scanning system. Further, enlargement / reduction processing is performed according to the display mode.
【００８３】625/50/2:1系（現行ＰＡＬ方式に相当）の
入力信号は、ＩＰ変換部で順次走査に変換した信号に対
して、垂直スケ−リング部でフレ−ムレ−ト変換、６−
５変換を行う。併せて、各種表示モ−ドに対応したフォ
−マット変換を行う。The input signal of the 625/50/2: 1 system (corresponding to the current PAL system) is obtained by converting the signal converted into the sequential scan by the IP conversion unit into a frame rate conversion by the vertical scaling unit. 6-
5 Perform conversion. At the same time, format conversion corresponding to various display modes is performed.
【００８４】ＰＣ系（パソコン画像）の入力信号は、60
フレ−ム／秒の順次走査系の信号であるので、ＩＰ変換
は行わず、水平、垂直スケ−リング部でノ−マルモ−ド
表示の処理を行う。すなわち、ＶＧＡ系(640x480)では
水平４−３変換、ＳＶＧＡ系(800x600)では水平４−３
変換と垂直５−４変換、ＸＧＡ系(1024x768)では水平４
−３変換と垂直８−５変換を行う。The input signal of the PC system (personal computer image) is 60
Since the signal is a frame / second progressive scan signal, normal mode display processing is performed in the horizontal and vertical scaling units without performing IP conversion. That is, in the VGA system (640x480), the horizontal 4-3 conversion is performed, and in the SVGA system (800x600), the horizontal 4-3 conversion is performed.
Conversion and vertical 5-4 conversion, horizontal 4 in XGA system (1024x768)
-3 conversion and vertical 8-5 conversion are performed.
【００８５】図１５は、625/100/2:1,アスペクト比16:9
の表示系に対するＩＰ変換部、水平、垂直スケ−リング
部での信号処理の内容である。FIG. 15 shows 625/100/2: 1, aspect ratio 16: 9.
5 shows the contents of signal processing in the IP conversion unit and the horizontal and vertical scaling units for the display system of FIG.
【００８６】525/60/2:1系（現行ＮＴＳＣ方式に相当）
の入力信号は、ＩＰ変換部で順次走査に変換した信号に
対して、垂直スケ−リング部でフレ−ムレ−ト変換、５
−６変換、フィ−ルド倍速変換を行う。併せて、各種表
示モ−ドに対応したフォ−マット変換を行う。525/60/2: 1 system (corresponding to the current NTSC system)
The input signal of (1) is subjected to frame rate conversion by the vertical scaling unit with respect to the signal converted into the sequential scanning by the IP conversion unit.
-6 conversion and field double speed conversion are performed. At the same time, format conversion corresponding to various display modes is performed.
【００８７】525/60/1:1系（ＥＤＴＶ方式に相当）の入
力信号は、順次走査系であるのでＩＰ変換は行わず、垂
直スケ−リング部でフレ−ムレ−ト変換、５−６変換、
フィ−ルド倍速変換を行う。また、表示モ−ドに応じ
て、スル−、拡大、縮小の処理を行う。The input signal of the 525/60/1: 1 system (corresponding to the EDTV system) is a progressive scanning system, so that IP conversion is not performed, and frame rate conversion is performed in the vertical scaling section, and 5-6. conversion,
Field double speed conversion is performed. Further, through, enlargement, and reduction processes are performed in accordance with the display mode.
【００８８】1125/60/2:1系（ＨＤＴＶに相当）の入力
信号は、垂直スケ−リング部でフレ−ムレ−ト変換、１
５−１６変換、フィ−ルド倍速変換を行う。また、表示
モ−ドに応じて、拡大、縮小の処理を行う。The input signal of the 1125/60/2: 1 system (corresponding to HDTV) is subjected to frame rate conversion, 1 in the vertical scaling section.
5-16 conversion and field double speed conversion are performed. Further, enlargement / reduction processing is performed according to the display mode.
【００８９】625/50/2:1系（現行ＰＡＬ方式に相当）の
入力信号は、ＩＰ変換部で順次走査に変換した信号に対
して、垂直スケ−リング部でフィ−ルド倍速変換を行
う。また、各種表示モ−ドに対応したフォ−マット変換
を行う。The input signal of the 625/50/2: 1 system (corresponding to the current PAL system) is subjected to field double conversion by the vertical scaling unit with respect to the signal converted into the sequential scanning by the IP conversion unit. . In addition, format conversion corresponding to various display modes is performed.
【００９０】ＰＣ系（パソコン画像）の入力信号は、60
フレ−ム／秒の順次走査系の信号であるので、ＩＰ変換
は行わず、垂直スケ−リング部でフレ−ムレ−ト変換、
フィ−ルド倍速変換を行う。また、ノ−マルノ−ド表示
のための処理を行う。すなわち、ＶＧＡ系(640x480)で
は水平４−３変換と垂直５−６変換、ＳＶＧＡ系(800x6
00)では水平４−３変換、ＸＧＡ系(1024x768)では水平
４−３変換と垂直４−３変換を行う。The input signal of the PC system (personal computer image) is 60
Since it is a signal of a frame / second progressive scanning system, the IP conversion is not performed, and the frame rate conversion and the frame rate conversion are performed by the vertical scaling unit.
Field double speed conversion is performed. Further, processing for normal node display is performed. That is, in the VGA system (640x480), horizontal 4-3 conversion and vertical 5-6 conversion, and in the SVGA system (800x6
00), horizontal 4-3 conversion and vertical 4-3 conversion are performed in the XGA system (1024 × 768).
【００９１】図１６は、1125/60/2:1,アスペクト比16:9
の表示系に対するＩＰ変換部、水平、垂直スケ−リング
部での信号処理の内容である。FIG. 16 shows a case where 1125/60/2: 1 and the aspect ratio are 16: 9.
5 shows the contents of signal processing in the IP conversion unit and the horizontal and vertical scaling units for the display system of FIG.
【００９２】525/60/2:1系（現行ＮＴＳＣ方式に相当）
の入力信号は、ＩＰ変換部で順次走査に変換した信号に
対して、各種表示モ−ドに対応したフォ−マット変換を
行う。なお、垂直スケ−リング部では１６−１７変換を
併せて行い、飛び越し走査系の信号に変換する。525/60/2: 1 system (corresponding to the current NTSC system)
The input signal is subjected to format conversion corresponding to various display modes with respect to the signal converted into the sequential scanning by the IP conversion unit. In the vertical scaling section, 16-17 conversion is also performed to convert to interlaced scanning signals.
【００９３】525/60/1:1系（ＥＤＴＶ方式に相当）の入
力信号は、順次走査系であるのでＩＰ変換は行わず、表
示モ−ドに応じて、スル−、拡大、縮小の処理を行う。
なお、垂直スケ−リング部では１６−１７変換を併せて
行い、飛び越し走査系の信号に変換する。Since the input signal of the 525/60/1: 1 system (corresponding to the EDTV system) is a progressive scanning system, it is not subjected to IP conversion, and is subjected to through, enlargement, and reduction processing in accordance with the display mode. I do.
In the vertical scaling section, 16-17 conversion is also performed to convert to interlaced scanning signals.
【００９４】1125/60/2:1系（ＨＤＴＶに相当）の入力
信号は、表示モ−ドに応じて、拡大、縮小の処理を行
う。The input signal of the 1125/60/2: 1 system (corresponding to HDTV) is subjected to enlargement / reduction processing according to the display mode.
【００９５】625/50/2:1系（現行ＰＡＬ方式に相当）の
入力信号は、ＩＰ変換部で順次走査に変換した信号に対
して、垂直スケ−リング部でフレ−ムレ−ト変換、１６
−１５変換を行い、飛び越し走査系の信号に変換する。
併せて、各種表示モ−ドに対応したフォ−マット変換を
行う。The input signal of the 625/50/2: 1 system (corresponding to the current PAL system) is obtained by converting the signal converted into the progressive scan by the IP conversion section into the frame rate conversion by the vertical scaling section. 16
Perform -15 conversion to convert to interlaced scanning signals.
At the same time, format conversion corresponding to various display modes is performed.
【００９６】ＰＣ系（パソコン画像）の入力信号は、60
フレ−ム／秒の順次走査系の信号であるので、ＩＰ変換
は行わず、水平、垂直スケ−リング部でノ−マルモ−ド
表示の処理を行う。すなわち、ＶＧＡ系(640x480)では
水平４−３変換と垂直１６−１７変換、ＳＶＧＡ系(800
x600)では水平４−３変換と垂直２０−１７変換、ＸＧ
Ａ系(1024x768)では水平４−３変換と垂直３２−２１変
換を行う。The input signal of the PC system (personal computer image) is 60
Since the signal is a frame / second progressive scan signal, normal mode display processing is performed in the horizontal and vertical scaling units without performing IP conversion. That is, in the VGA system (640x480), the horizontal 4-3 conversion and the vertical 16-17 conversion, and the SVGA system (800
x600), horizontal 4-3 conversion and vertical 20-17 conversion, XG
The A system (1024x768) performs horizontal 4-3 conversion and vertical 32-21 conversion.
【００９７】以上に述べた如く、本実施例によれば、信
号処理に伴う画質の劣化が少なく、かつ、使用するメモ
リ容量が極めて少なく、また、コスト低減に適した画像
信号のフォ−マット変換の信号処理回路を実現すること
ができる。As described above, according to this embodiment, the image quality is not deteriorated due to the signal processing, the memory capacity used is extremely small, and the format conversion of the image signal suitable for cost reduction is performed. Can be realized.
【００９８】次に、第２の実施例について、図１７のブ
ロック構成図で説明する。本実施例は、２系列に分割し
て水平、垂直スケ−リング部の信号処理を行うに好適な
ものである。同図の２３はＩＰ変換部、５７は２チャネ
ル化部、２５は選択部、２６は水平スケ−リング部、５
８は垂直スケ−リング部、５９はメモリ部、２４は倍速
化部、２９は画質改善部、３０は多重部、３１はマイコ
ン部、３２はコントロ−ル部である。Next, a second embodiment will be described with reference to the block diagram of FIG. The present embodiment is suitable for performing signal processing in the horizontal and vertical scaling units by dividing into two streams. 23 is an IP conversion unit, 57 is a two-channel conversion unit, 25 is a selection unit, 26 is a horizontal scaling unit, 5
8 is a vertical scaling section, 59 is a memory section, 24 is a double speed section, 29 is an image quality improving section, 30 is a multiplexing section, 31 is a microcomputer section, and 32 is a control section.
【００９９】入力画像信号系列S1(4:2:2系,あるいは4:
2:0系のコンポ−ネント輝度、色差信号)は、ＩＰ変換部
２３と２チャネル化部５７に入力する。The input image signal sequence S1 (4: 2: 2 system or 4:
The 2: 0 system component luminance and color difference signals) are input to the IP converter 23 and the two-channel converter 57.
【０１００】ＩＰ変換部２３は、前述の第１乃至第３の
実施例の信号処理回路で構成し、飛び越し走査系の入力
画像信号に対して、飛び越し走査で抜けた走査線の信号
を動き適応型の補間処理で生成し、伝送走査線信号系列
SMと補間走査線信号系列SIとを出力する。The IP conversion unit 23 is constituted by the signal processing circuits of the first to third embodiments described above. The IP conversion unit 23 performs motion adaptation on a signal of a scanning line which is skipped by interlaced scanning with respect to an input image signal of an interlaced scanning system. Transmission scan line signal series
An SM and an interpolated scanning line signal sequence SI are output.
【０１０１】２チャネル化部５７は、順次走査系の入力
画像信号に対して、２系列の飛び越し走査系の信号系列
SM',SI'を生成する。The two-channeling section 57 converts a two-interlaced signal sequence of an interlaced scanning system into an input image signal of a sequential scanning system.
Generate SM 'and SI'.
【０１０２】選択部２５は、入力画像信号が飛び越し走
査系の現行ＴＶ信号では信号系列SM,SI、順次走査系の
ＥＤＴＶ信号やパソコン画像信号およびＨＤＴＶ信号で
は信号系列SM',SI'をそれぞれ選択し、これを信号系列S
2M,S2Iとして出力する。The selecting section 25 selects the signal series SM and SI for the current TV signal of the interlaced scanning system and the signal series SM 'and SI' for the EDTV signal or the personal computer image signal and the HDTV signal of the progressive scanning system. And the signal sequence S
Output as 2M, S2I.
【０１０３】水平スケ−リング部２６は、信号系列S2M,
S2IのそれぞれにＫ−Ｌ変換（Ｋ個の画素をＬ個の画素
に変換）の信号処理で水平拡大（Ｋ＜Ｌ）や水平縮小
（Ｋ＞Ｌ）を行い、信号系列S3M,S3Iを出力する。The horizontal scaling section 26 generates a signal sequence S2M,
Performs horizontal expansion (K <L) or horizontal reduction (K> L) by signal processing of KL conversion (conversion of K pixels to L pixels) for each of S2Is, and outputs signal sequences S3M and S3I I do.
【０１０４】垂直スケ−リング部５８は、信号系列S3M,
S3Iに対してＫ−Ｌ変換（Ｋ個のラインをＬ個のライン
に変換）の信号処理で垂直拡大（Ｋ＜Ｌ）や垂直縮小
（Ｋ＞Ｌ）を行う。なお、入力信号によっては、メモリ
部５９のメモリの動作制御を行い、方式変換（例えば、
ＰＡＬ−ＮＴＳＣ変換）や、同期整合や、ＰＡＬフィ−
ルド倍速の信号処理も併せて実行する。そして、フォ−
マット変換した画像信号系列S4M,S4Iを出力する。The vertical scaling section 58 generates a signal sequence S3M,
Vertical expansion (K <L) and vertical reduction (K> L) are performed on the S3I by signal processing of KL conversion (conversion of K lines into L lines). In addition, depending on the input signal, the operation of the memory of the memory unit 59 is controlled, and the format conversion (for example,
PAL-NTSC conversion), synchronization matching, PAL file
The double-speed signal processing is also performed. And fore
The image signal sequences S4M and S4I that have been subjected to mat conversion are output.
【０１０５】倍速化部２４は、信号系列S4MとS4Iをそれ
ぞれ水平方向に時間軸の１／２圧縮と時系列多重の信号
処理を行い、順次走査系の画像信号系列S4を出力する。The speed doubling unit 24 performs signal processing of 1/2 compression on the time axis and time-series multiplexing of the signal sequences S4M and S4I in the horizontal direction, respectively, and outputs an image signal sequence S4 of a sequential scanning system.
【０１０６】画質改善部２９は、輝度信号の黒レベル補
正、白レベル補正などの画質改善や、色空間変換などの
信号処理を行い、３原色ＲＧＢ信号に変換する。また、
表示系がリニア特性のディスプレイでは、逆γ変換の信
号処理を行う。そして、３原色画像信号系列S5を出力す
る。The image quality improving unit 29 performs image processing such as black level correction and white level correction of the luminance signal and signal processing such as color space conversion, and converts the signal into three primary color RGB signals. Also,
In a display having a linear display system, signal processing of inverse γ conversion is performed. Then, a three-primary-color image signal sequence S5 is output.
【０１０７】多重部３０は、信号系列S5にマルチ画面表
示（例えば、２画面表示、ＰＩＰ表示、マルチウィンド
表示など）のための３原色画像信号系列S7を多重する信
号処理を行う。そして、表示系のフォ−マットに合致し
た画像信号系列S6を出力する。The multiplexing section 30 performs signal processing for multiplexing the signal sequence S5 with a three primary color image signal sequence S7 for multi-screen display (for example, two-screen display, PIP display, multi-window display, etc.). Then, an image signal sequence S6 matching the display system format is output.
【０１０８】マイコン部３１は、画像情報信号SPI（入
力画像信号の種類、表示系のフォ−マット、画面表示の
モ−ドなどの情報）をもとに、各ブロック部における信
号処理のパラメタを設定する。The microcomputer section 31 converts the parameters of signal processing in each block section based on the image information signal SPI (information such as the type of input image signal, the format of the display system, and the mode of screen display). Set.
【０１０９】コントロ−ル部３２は、各ブロック部にお
ける信号処理に必要な同期信号や、制御信号や、クロッ
ク信号などを生成する。また、マルチ画面表示の際の同
期整合処理に必要な情報SDを出力する。The control unit 32 generates a synchronization signal, a control signal, a clock signal, and the like necessary for signal processing in each block unit. Also, it outputs information SD necessary for the synchronization matching process at the time of multi-screen display.
【０１１０】以下、本実施例に特有なブロック部につい
て説明する。Hereinafter, a block part specific to this embodiment will be described.
【０１１１】図１８は、２チャネル化部の一構成例図
で、同図(a)に構成、(b)にラインメモリの動作を示す。FIGS. 18A and 18B show an example of the configuration of the two-channel unit. FIG. 18A shows the configuration, and FIG. 18B shows the operation of the line memory.
【０１１２】順次走査系の入力画像信号の輝度信号S1
(Y)と色差信号S1(C)は、それぞれラインメモリ６０−
１，６０−２に入力する。The luminance signal S1 of the input image signal of the progressive scanning system
(Y) and the color difference signal S1 (C) are respectively stored in the line memory 60-
1, 60-2.
【０１１３】ラインメモリ６０−１は、同図(b)に示す
様に、WT動作で第１の飛び越し走査系に相当する走査線
の信号（図の,,…の走査線）を記憶する。一方、RD
動作はWT動作の２倍の期間で行い、信号を読み出す。そ
して、この出力に飛び越し走査系の信号系列SM'(Y),SM'
(C)を得る。The line memory 60-1 stores the signals of the scanning lines corresponding to the first interlaced scanning system in the WT operation (the scanning lines of,...) In the WT operation, as shown in FIG. Meanwhile, RD
The operation is performed in a period twice as long as the WT operation, and a signal is read. Then, the signal sequence SM ′ (Y), SM ′ of the interlaced scanning system is added to this output.
Obtain (C).
【０１１４】ラインメモリ６０−２は、WT動作で第２の
飛び越し走査系に相当する走査線の信号（図では,,
…の走査線）を記憶する。一方、RD動作はWT動作の２倍
の期間で行い、信号を読み出す。そして、この出力に飛
び越し走査系の信号系列SI'(Y),SI'(C)を得る。In the WT operation, the line memory 60-2 receives a signal of a scanning line corresponding to the second interlaced scanning system (in FIG.
.. Scanning lines). On the other hand, the RD operation is performed in a period twice as long as the WT operation, and the signal is read. Then, a signal sequence SI ′ (Y), SI ′ (C) of the interlaced scanning system is obtained from this output.
【０１１５】次に、垂直スケ−リング部の一構成例を図
１９に示す。同図(a)は構成を示し、図中の５９はメモ
リ部、６１は垂直ＬＰＦ、６２,６６,６７,６８はスイ
ッチ、６３は１ライン遅延、６４は係数加重部、６５は
加算部である。また、同図(b)は、各種信号処理におけ
るスイッチ類の選択制御を示す。Next, FIG. 19 shows an example of the configuration of the vertical scaling section. FIG. 11A shows the configuration, in which 59 is a memory unit, 61 is a vertical LPF, 62, 66, 67, and 68 are switches, 63 is a one-line delay, 64 is a coefficient weighting unit, and 65 is an addition unit. is there. FIG. 2B shows selection control of switches in various signal processing.
【０１１６】垂直縮小の信号処理では、SW1,SW2,SW4は
端子a、SW3は端子bに接続する。そして、２系列の画像
信号の輝度信号S3M(Y),S3I(Y)は、まず、縮小処理で折
り返し歪となる垂直高域周波数成分を除去するため、垂
直ＬＰＦ６１で低域通過の周波数特性で帯域制限を行
う。次に、１ライン遅延６３と係数加重部６４と加算部
６５とで構成する演算部で、２点線形補間の特性による
ラインのＫ−Ｌ変換（Ｋ＞Ｌ）の演算を行う。すなわ
ち、１つの系は、S3M(Y),S3I(Y)の信号に対し、係数加
重部６４で係数値β,1-βを加重し、加算部６５で両者
を加算する。もう一方の系は、信号S3M(Y)を１ライン遅
延６３で１ライン遅延した信号とS3I(Y)の信号に対し、
係数加重部６４では係数値γ,1-γを加重し、加算部６
５で両者を加算する。そして、この出力にＫ−Ｌ変換で
Ｋラインから生成したＬラインの信号からなる２系列の
信号を得る。なお、係数値β,1-βとγ,1-γは、それぞ
れライン毎に変化する。例えば、４−３変換では、係数
値(β,1-β)は、(1,0),(1/3,2/3),(2/3,1/3),(1,0),…,
係数値(γ,1-γ)は、(2/3,1/3),(1,0),(1/3,2/3),(2/3,
1/3),…とライン毎に変化する。メモリ部５９のM1で
は、図２０(a)に示す様に、１フィ−ルド期間を周期にW
T動作、RD動作を行う。WT動作では、Ｋ−Ｌ変換で生成
した２系列の信号を間欠的に書き込み記憶する。一方、
RD動作では(1-L/K)フィ−ルド期間遅れた時点より連続
的に２系列の信号を読み出す。そして、６８のＳＷ４の
出力に、L/K倍に垂直縮小した２系列の信号系列S4M(Y),
S4I(Y)を得る。以上に述べた垂直縮小の信号処理に必要
なメモリ容量は、(1-L/K)フィ−ルド期間分あればよ
い。In signal processing for vertical reduction, SW1, SW2, and SW4 are connected to a terminal a, and SW3 is connected to a terminal b. Then, the luminance signals S3M (Y) and S3I (Y) of the two series of image signals are first subjected to low-pass frequency characteristics by the vertical LPF 61 in order to remove vertical high-frequency components that are aliasing in the reduction processing. Perform band limiting. Next, a calculation unit including a one-line delay 63, a coefficient weighting unit 64, and an addition unit 65 performs a KL conversion (K> L) of a line based on the characteristics of two-point linear interpolation. That is, in one system, the coefficient values β, 1−β are weighted by the coefficient weighting unit 64 on the S3M (Y), S3I (Y) signals, and both are added by the adding unit 65. In the other system, a signal obtained by delaying the signal S3M (Y) by one line by a one-line delay 63 and a signal of S3I (Y) are
The coefficient weighting unit 64 weights the coefficient values γ, 1−γ,
At 5 the two are added. Then, on this output, two series of signals consisting of the L line signals generated from the K lines by KL conversion are obtained. Note that the coefficient values β, 1-β and γ, 1-γ change for each line. For example, in the 4-3 conversion, the coefficient value (β, 1−β) is (1, 0), (1/3, 2/3), (2/3, 1/3), (1, 0) ,…,
The coefficient values (γ, 1-γ) are (2 / 3,1 / 3), (1,0), (1 / 3,2 / 3), (2/3,
1/3), ... changes for each line. In M1 of the memory unit 59, as shown in FIG.
Perform T operation and RD operation. In the WT operation, two series of signals generated by the KL conversion are intermittently written and stored. on the other hand,
In the RD operation, two series of signals are continuously read from a point in time delayed by (1-L / K) field period. Then, two signal series S4M (Y), vertically reduced L / K times, are output to the output of SW4 68.
Obtain S4I (Y). The memory capacity necessary for the above-described vertical reduction signal processing may be the (1-L / K) field period.
【０１１７】垂直拡大の信号処理では、SW1,SW2は端子
b、SW3,SW4は端子aに接続する。メモリ部５９のM1で
は、図２０(b)に示す様に、１フィ−ルド期間を周期と
するWT動作、RD動作を行う。そして、２系列の画像信号
の輝度信号S3M(Y),S3I(Y)は、まず、WT動作で連続的に
信号を記憶する。一方、RD動作では一部期間で２度読み
出しの動作を行いＫラインの期間にＬラインの２系列の
信号を読み出す。次に、１ライン遅延６３と係数加重部
６４と加算部６５とで構成する演算部で、２点線形補間
の特性によるラインのＬ−Ｋ変換（Ｌ＜Ｋ）の演算を行
う。すなわち、１つの系は、S3M(Y),S3I(Y)の信号に対
し、係数加重部６４で係数値β,1-βを加重し、加算部
６５で両者を加算する。もう一方の系は、信号S3M(Y)を
１ライン遅延６３で１ライン遅延した信号とS3I(Y)の信
号に対し、係数加重部６４では係数値γ,1-γを加重
し、加算部６５で両者を加算する。そして、この出力に
Ｌ−Ｋ変換でＬラインから生成したＫラインの信号から
なる２系列の信号を得る。なお、係数値β,1-βとγ,1-
γは、それぞれライン毎に変化する。例えば、３−４変
換では、係数値(β,1-β)は、(1,0),(2/4,2/4),(1,0),
…,係数値(γ,1-γ)は、(1/4,3/4),(3/4,1/4),(1/4,3/
4),…とライン毎に変化する。そして、６８のＳＷ４の
出力に、K/L倍に垂直拡大した２系列の信号系列S4M(Y),
S4I(Y)を得る。以上に述べた垂直拡大の信号処理に必要
なメモリ容量は、(1-L/K)フィ−ルド期間分あればよ
い。In the vertical expansion signal processing, SW1 and SW2 are connected to terminals.
b, SW3, SW4 are connected to terminal a. At M1 of the memory unit 59, as shown in FIG. 20B, the WT operation and the RD operation are performed with one field period as a cycle. First, the luminance signals S3M (Y) and S3I (Y) of the two series of image signals are continuously stored by the WT operation. On the other hand, in the RD operation, a read operation is performed twice in a partial period, and two series of signals on the L line are read in the period of the K line. Next, a calculation unit including a one-line delay 63, a coefficient weighting unit 64, and an addition unit 65 performs LK conversion (L <K) of the line based on the characteristics of two-point linear interpolation. That is, in one system, the coefficient values β, 1−β are weighted by the coefficient weighting unit 64 on the S3M (Y), S3I (Y) signals, and both are added by the adding unit 65. In the other system, a coefficient weighting unit 64 weights a coefficient value γ, 1-γ to a signal obtained by delaying the signal S3M (Y) by one line by a one-line delay 63 and a signal of S3I (Y), and At 65, both are added. Then, a two-series signal composed of K-line signals generated from L-lines by LK conversion is obtained from this output. Note that coefficient values β, 1-β and γ, 1-
γ changes for each line. For example, in the 3-4 transform, the coefficient values (β, 1-β) are (1, 0), (2/4, 2/4), (1, 0),
…, The coefficient values (γ, 1-γ) are (1/4, 3/4), (3/4, 1/4), (1/4, 3 /
4), ... changes for each line. Then, two signal series S4M (Y), vertically expanded by K / L times, are output to the output of SW4 68.
Obtain S4I (Y). The memory capacity required for the above-described vertical expansion signal processing may be sufficient for the (1-L / K) field period.
【０１１８】ＰＡＬフィ−ルド倍速の信号処理は、順次
走査系に変換したＰＡＬ信号（以下625/50/1:1と略称）
を100フィ−ルド／秒の飛び越し走査系の信号（以下625
/100/2:1と略称）に変換するもので、SW2,SW3を端子b、
SW4を端子aに接続して実現する。メモリ部５９のM1で
は、図２０(c)に示す様なWT動作、RD動作を行う。２系
列のＰＡＬ信号の輝度信号S3M(Y),S3I(Y)は、１フィ−
ルド期間を周期に、WT動作で連続的に信号を記憶する。
一方、RD動作では、0.5フィ−ルド期間遅れた時点か
ら、一方の信号系列（図中の○-O）、他方の信号系列
（図中の○-E）の順に信号の読出しを行う。そして、６
８のＳＷ４の出力に、ＰＡＬフィ−ルド倍速した２系列
の信号系列SM4(Y),S4I(Y)を得る。以上に述べたＰＡＬ
フィ−ルド倍速の信号処理に必要なメモリ容量は、1フ
ィ−ルド期間分あればよい。The PAL field double-speed signal processing is performed on a PAL signal (hereinafter abbreviated as 625/50/1: 1) converted into a sequential scanning system.
To a 100-field / second interlaced scanning signal (hereafter 625
/ 100/2: 1), with SW2 and SW3 connected to terminal b,
This is realized by connecting SW4 to terminal a. In M1 of the memory unit 59, the WT operation and the RD operation as shown in FIG. The luminance signals S3M (Y) and S3I (Y) of the two series of PAL signals are
The signal is continuously stored by the WT operation with the cycle of the threshold period.
On the other hand, in the RD operation, signals are read out in order of one signal sequence (（-O in the drawing) and the other signal sequence (○ -E in the drawing) from the point of time delayed by 0.5 field period. And 6
In the output of SW4 of No. 8, two signal sequences SM4 (Y) and S4I (Y) at PAL field double speed are obtained. PAL described above
The memory capacity required for the field double speed signal processing may be one field period.
【０１１９】ＮＴＳＣ−ＰＡＬフィ−ルド倍速の信号処
理は、順次走査系に変換したＮＴＳＣ信号（以下525/60
/1:1と略称）を625/100/2:1系の信号に変換するもの
で、SW1,SW2を端子b、SW3を端子c、SW4を端子aに接続し
て実現する。２系列のＮＴＳＣ信号の輝度信号S3M(Y),S
3I(Y)は、図２０(d)に示す様に、メモリ部５９のM1に、
ＮＴＳＣ１フィ−ルド期間を周期とするWT動作で、連続
的に信号を記憶する。一方、RD動作では、ＰＡＬ１フィ
−ルド期間を周期に、一部期間で２度読み出しの動作を
行い６ラインの期間に５ラインの２系列の信号を読み出
す。次に、１ライン遅延６３と係数加重部６４と加算部
６５とで構成する演算部で、２点線形補間の特性による
ラインの５−６変換の演算で垂直拡大を行う。すなわ
ち、１つの系は、S3M(Y),S3I(Y)の信号に対し、係数加
重部６４で係数値β,1-βを加重し、加算部６５で両者
を加算する。もう一方の系は、信号S3M(Y)を１ライン遅
延６３で１ライン遅延した信号とS3I(Y)の信号に対し、
係数加重部６４では係数値γ,1-γを加重し、加算部６
５で両者を加算する。そして、この出力に５−６変換で
５ラインから生成した６ラインの信号からなる２系列の
信号を得る。なお、係数値β,1-βとγ,1-γは、それぞ
れライン毎に変化する。メモリ部５９のM2では、ＰＡＬ
１フィ−ルド期間を周期に、WT動作で連続的に信号を記
憶する。一方、RD動作では、0.5フィ−ルド期間遅れた
時点から、一方の信号系列（図中の○-O）、他方の信号
系列（図中の○-E）の順に信号の読出しを行う。そし
て、６８のＳＷ４の出力に、ＮＴＳＣ−ＰＡＬフィ−ル
ド倍速した２系列の信号系列SM4(Y),S4I(Y)を得る。以
上に述べたＮＴＳＣ−ＰＡＬフィ−ルド倍速の信号処理
に必要なメモリ容量は、ＮＴＳＣ−ＰＡＬ変換に1フィ
−ルド期間分、フィ−ルド倍速変換に1フィ−ルド期間
分あればよい。The signal processing at the NTSC-PAL field double speed is performed on an NTSC signal (hereinafter referred to as 525/60) converted to a progressive scanning system.
/ 1: 1) is converted to a 625/100/2: 1 system signal. SW1 and SW2 are connected to terminal b, SW3 is connected to terminal c, and SW4 is connected to terminal a. Luminance signal S3M (Y), S of two NTSC signals
3I (Y) is stored in M1 of the memory unit 59 as shown in FIG.
The signal is continuously stored in the WT operation having the period of the NTSC1 field period. On the other hand, in the RD operation, the read operation is performed twice in a partial period with the PAL1 field period as a cycle, and two lines of signals of five lines are read in a period of six lines. Next, in a calculation unit including a one-line delay 63, a coefficient weighting unit 64, and an addition unit 65, vertical enlargement is performed by calculation of 5-6 conversion of a line based on characteristics of two-point linear interpolation. That is, in one system, the coefficient values β, 1−β are weighted by the coefficient weighting unit 64 on the S3M (Y), S3I (Y) signals, and both are added by the adding unit 65. In the other system, a signal obtained by delaying the signal S3M (Y) by one line by a one-line delay 63 and a signal of S3I (Y) are
The coefficient weighting unit 64 weights the coefficient values γ, 1−γ,
At 5 the two are added. Then, a two-series signal composed of six lines of signals generated from five lines by 5-6 conversion is obtained from this output. Note that the coefficient values β, 1-β and γ, 1-γ change for each line. In M2 of the memory unit 59, PAL
The signal is continuously stored by the WT operation in a cycle of one field period. On the other hand, in the RD operation, signals are read out in order of one signal sequence (（-O in the drawing) and the other signal sequence (○ -E in the drawing) from the point of time delayed by 0.5 field period. Then, two signal sequences SM4 (Y) and S4I (Y) at NTSC-PAL field double speed are obtained at the output of SW4 68. The memory capacity required for the above-described NTSC-PAL field double-speed signal processing may be one field period for NTSC-PAL conversion and one field period for field double-speed conversion.
【０１２０】ＰＡＬ−ＮＴＳＣ変換の信号処理は、625/
50/1:1系の信号を525/60/1:1系の信号に変換するもの
で、SW1,SW2を端子a、SW3を端子b、SW4を端子aに接続し
て実現する。２系列のＰＡＬ信号の輝度信号S3M(Y),S3I
(Y)は、垂直ＬＰＦ６１で低域通過の周波数特性で帯域
制限を行う。次に、１ライン遅延６３と係数加重部６４
と加算部６５とで構成する演算部で、２点線形補間の特
性によるラインの６−５変換の演算で垂直縮小を行う。
すなわち、１つの系は、S3M(Y),S3I(Y)の信号に対し、
係数加重部６４で係数値β,1-βを加重し、加算部６５
で両者を加算する。もう一方の系は、信号S3M(Y)を１ラ
イン遅延６３で１ライン遅延した信号とS3I(Y)の信号に
対し、係数加重部６４では係数値γ,1-γを加重し、加
算部６５で両者を加算する。そして、この出力に６−５
変換で６ラインから生成した５ラインの信号からなる２
系列の信号を得る。なお、係数値β,1-βとγ,1-γは、
それぞれライン毎に変化する。メモリ部５９のM1では、
図２０(e)に示す様に、ＰＡＬ１フィ−ルド期間を周期
とするWT動作で、６−５変換で生成した２系列の信号を
間欠的に書き込み記憶する。一方、RD動作ではＮＴＳＣ
１フィ−ルド期間を周期に２系列の信号を読み出す。そ
して、６８のＳＷ４の出力に、ＰＡＬ−ＮＴＳＣ変換し
た信号系列S4M(Y),S4I(Y)を得る。以上に述べたＰＡＬ
−ＮＴＳＣ変換の信号処理に必要なメモリ容量は、ＰＡ
Ｌ１フィ−ルド期間分あればよい。The signal processing of the PAL-NTSC conversion is 625 /
It converts 50/1: 1 system signals to 525/60/1: 1 system signals, and is realized by connecting SW1 and SW2 to terminal a, SW3 to terminal b, and SW4 to terminal a. Luminance signals S3M (Y), S3I of two series of PAL signals
In (Y), the vertical LPF 61 performs band limitation using low-pass frequency characteristics. Next, a one-line delay 63 and a coefficient weighting unit 64
And an adder 65, which performs vertical reduction by 6-5 conversion of the line based on the characteristics of two-point linear interpolation.
That is, one system is for S3M (Y) and S3I (Y) signals.
A coefficient weighting section 64 weights the coefficient values β, 1−β, and an addition section 65
Add both. In the other system, a coefficient weighting unit 64 weights a coefficient value γ, 1-γ with respect to a signal obtained by delaying the signal S3M (Y) by one line by one line delay 63 and a signal of S3I (Y), and At 65, both are added. And this output is 6-5
2 composed of signals of 5 lines generated from 6 lines by conversion
Get the sequence signal. Note that the coefficient values β, 1-β and γ, 1-γ are
Each changes for each line. In M1 of the memory unit 59,
As shown in FIG. 20 (e), two series of signals generated by the 6-5 conversion are intermittently written and stored by the WT operation having a cycle of the PAL1 field period. On the other hand, in RD operation, NTSC
Two series of signals are read out with a period of one field period. Then, PAL-NTSC converted signal sequences S4M (Y) and S4I (Y) are obtained at the output of SW4 68. PAL described above
-The memory capacity required for NTSC conversion signal processing is PA
What is necessary is just for the L1 field period.
【０１２１】スル−の信号処理では、SW4を端子bに接続
する。そして、６８のＳＷ４の出力に、縮小拡大の処理
を行わない２系列の信号系列S4M(Y),S4I(Y)を得る。In the through signal processing, SW4 is connected to terminal b. Then, at the output of SW4 68, two signal sequences S4M (Y) and S4I (Y) that are not subjected to reduction / enlargement processing are obtained.
【０１２２】２系列の画像信号の色差信号S3M(C)、S3I
(C)に対しても、輝度信号と同一の構成による信号処理
を行い、垂直縮小、垂直拡大、ＰＡＬフィ−ルド倍速変
換、ＮＴＳＣ−ＰＡＬフィ−ルド倍速変換、ＰＡＬ−Ｎ
ＴＳＣ変換あるいはスル−の２系列の信号系列S4M(C)、S
4I(C)を得る。The color difference signals S3M (C) and S3I of the two series of image signals
For (C), signal processing is performed using the same configuration as that of the luminance signal, and vertical reduction, vertical enlargement, PAL field double-speed conversion, NTSC-PAL field double-speed conversion, and PAL-N are performed.
TSC conversion or through two signal sequences S4M (C), S
4I (C) is obtained.
【０１２３】以上に述べた如く、本実施例によれば、極
めて少ないメモリ容量で、前述の図１３や図１４,図１
５,図１６に示した各種のフォ−マット変換を行う信号
処理回路を実現することができる。そして、特に、超高
精細ディスプレイのような極めて高速の信号処理が要求
される表示系に対して有効である。As described above, according to the present embodiment, an extremely small memory capacity is used and the above-described FIGS.
5. A signal processing circuit for performing various format conversions shown in FIG. 16 can be realized. In particular, the present invention is effective for a display system requiring an extremely high-speed signal processing such as an ultra-high-definition display.
【０１２４】[0124]
【発明の効果】本発明によれば、飛び越し走査系の画像
信号を順次走査系の画像信号に変換するＩＰ変換や、複
数方式の画像信号を表示部の所定フォ−マットの信号に
変換するフォ−マット変換の信号処理回路を、高品質な
画質を維持し、かつ、信号処理に要するメモリの容量が
極めて少なく、コスト低減に適した形態で実現すること
ができる。そして、マルチメディア対応の各種情報機器
端末の機能向上ならびにコスト低減に顕著な効果があ
る。According to the present invention, an IP conversion for converting an image signal of an interlaced scanning system into an image signal of a progressive scanning system and a format for converting an image signal of a plurality of systems into a signal of a predetermined format of a display unit. -A signal processing circuit for mat conversion can be realized in a form which maintains high quality image quality, requires a very small memory capacity for signal processing, and is suitable for cost reduction. This has a remarkable effect on improving the functions of various types of information equipment terminals supporting multimedia and reducing costs.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の第１の実施例のブロック構成図。FIG. 1 is a block diagram of a first embodiment of the present invention.
【図２】サブナイキスト標本化の一特性例図。FIG. 2 is a characteristic example diagram of sub-Nyquist sampling.
【図３】プリフィルタ、ポストフィルタの一構成例図。FIG. 3 is a configuration example diagram of a pre-filter and a post-filter.
【図４】本発明の第２の実施例のブロック構成図。FIG. 4 is a block diagram of a second embodiment of the present invention.
【図５】本発明の第３の実施例のブロック構成図。FIG. 5 is a block diagram of a third embodiment of the present invention.
【図６】本発明のフォ−マット変換回路の第１の実施例
のブロック構成図。FIG. 6 is a block diagram showing a format conversion circuit according to a first embodiment of the present invention;
【図７】倍速化部の一構成例図。FIG. 7 is a diagram illustrating a configuration example of a speed doubling unit.
【図８】水平スケ−リング部の一構成例図。FIG. 8 is a diagram illustrating a configuration example of a horizontal scaling unit.
【図９】垂直スケ−リング部の一構成例図。FIG. 9 is a diagram illustrating a configuration example of a vertical scaling unit.
【図１０】垂直スケ−リング部の信号処理とメモリ動作
の概略図。FIG. 10 is a schematic diagram of signal processing and memory operation of a vertical scaling unit.
【図１１】Ｋ−Ｌ変換の一特性例図。FIG. 11 is a diagram showing an example of characteristics of KL conversion.
【図１２】画質改善部の一構成例図。FIG. 12 is a diagram illustrating a configuration example of an image quality improvement unit.
【図１３】画像処理の一例図。FIG. 13 illustrates an example of image processing.
【図１４】525/60/1:1(アスヘ゜クト16:9)表示系における信号
処理。FIG. 14 shows signal processing in a 525/60/1: 1 (aspect 16: 9) display system.
【図１５】625/100/2:1(アスヘ゜クト16:9)表示系における信
号処理。FIG. 15 shows signal processing in a 625/100/2: 1 (aspect 16: 9) display system.
【図１６】1125/60/2:1(アスヘ゜クト16:9)表示系における信
号処理。FIG. 16 shows signal processing in a 1125/60/2: 1 (aspect 16: 9) display system.
【図１７】本発明のフォ−マット変換回路の第２の実施
例のブロック構成図。FIG. 17 is a block diagram showing a format conversion circuit according to a second embodiment of the present invention;
【図１８】２チャネル化部の一構成例図。FIG. 18 is a diagram illustrating a configuration example of a two-channel unit.
【図１９】垂直スケ−リング部の一構成例図。FIG. 19 is a diagram illustrating a configuration example of a vertical scaling unit.
【図２０】垂直スケ−リング部の信号処理とメモリ動作
の概略図。FIG. 20 is a schematic diagram of signal processing and memory operation of a vertical scaling unit.
１…プリフィルタ、２…ダウンサンプル部、３…アップ
サンプル部、４…ポストフィルタ、５,１４…１Ｈ遅
延、６,８,１６,１９,３９,４８,６５…加算部、７…動
き係数加重部、９…１フィ−ルド遅延、１０,２１…減
算部、１１…動き検出部、１２…ＭＡＸ選択部、１３…
α加重部、１５,１８,３８,４７,６４…係数加重部、１
７,３７…１画素遅延、２０,２２…遅延部、２３…ＩＰ
変換部、２４…倍速化部、２５,５６…選択部、２６…
水平スケ−リング部、２７,５８…垂直スケ−リング
部、２８,５９…メモリ部、２９…画質改善部、３０,３
４…多重部、３１…マイコン部、３２…コントロ−ル
部、３３,６０…ラインメモリ、３５…水平ＬＰＦ、３
６,４５,６２…ＳＷ１、４０,４９,６６…ＳＷ２、４１
…１Ｈメモリ、４２,５０,６７…ＳＷ３、４３,５１,６
８…ＳＷ４、４４,６１…垂直ＬＰＦ、４６,６３…１ラ
イン遅延、５２…輝度処理部、５３…画素補間部、５４
…色空間変換部、５５…逆γ処理部、５７…２チャネル
化部。DESCRIPTION OF SYMBOLS 1 ... Pre-filter, 2 ... Down sampling part, 3 ... Up sampling part, 4 ... Post filter, 5,14 ... 1H delay, 6,8,16,19,39,48,65 ... Addition part, 7 ... Motion coefficient Weighting section, 9 1-field delay, 10, 21 Subtraction section, 11 Motion detection section, 12 MAX selection section, 13
α weight part, 15, 18, 38, 47, 64 ... coefficient weight part, 1
7,37 ... 1 pixel delay, 20,22 ... delay section, 23 ... IP
Conversion unit, 24 ... double speed unit, 25, 56 ... selection unit, 26 ...
Horizontal scaling section, 27, 58 Vertical scaling section, 28, 59 Memory section, 29 Image quality improvement section, 30, 3
4 multiplex unit, 31 microcomputer unit, 32 control unit, 33, 60 line memory, 35 horizontal LPF, 3
6, 45, 62 ... SW1, 40, 49, 66 ... SW2, 41
... 1H memory, 42,50,67 ... SW3,43,51,6
8 SW4, 44, 61 Vertical LPF, 46, 63 1 line delay, 52 Luminance processing unit, 53 Pixel interpolating unit, 54
... color space conversion unit, 55 ... inverse gamma processing unit, 57 ... 2-channel conversion unit.
フロントページの続き (72)発明者 中嶋 満雄 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所マルチメディアシステム 開発本部内 (72)発明者 杉山 雅人 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所マルチメディアシステム 開発本部内 (72)発明者 栗田 俊之 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所映像情報メディア事業部 内Continued on the front page (72) Inventor Mitsuo Nakajima 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Multimedia System Development Division of Hitachi, Ltd. (72) Inventor Masato Sugiyama 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture (72) Inventor Toshiyuki Kurita 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture In-house Information and Media Division of Hitachi, Ltd.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8300037AJPH10145817A (en) | 1996-11-12 | 1996-11-12 | Signal processing circuit for IP conversion and format conversion of image signal |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8300037AJPH10145817A (en) | 1996-11-12 | 1996-11-12 | Signal processing circuit for IP conversion and format conversion of image signal |
| Publication Number | Publication Date |
|---|---|
| JPH10145817Atrue JPH10145817A (en) | 1998-05-29 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8300037APendingJPH10145817A (en) | 1996-11-12 | 1996-11-12 | Signal processing circuit for IP conversion and format conversion of image signal |
| Country | Link |
|---|---|
| JP (1) | JPH10145817A (en) |
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| US8068173B2 (en) | 2009-09-30 | 2011-11-29 | Kabushiki Kaisha Toshiba | Color difference signal format conversion device and method |
| US8218076B2 (en) | 2006-12-25 | 2012-07-10 | Kabushiki Kaisha Toshiba | Image display apparatus, image signal processing apparatus, and image signal processing method |
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| US7068320B2 (en) | 2001-04-27 | 2006-06-27 | Sharp Kabushiki Kaisha | Image processing circuit, image display device, and an image processing method |
| US7408588B2 (en) | 2001-04-27 | 2008-08-05 | Shapr Kabushiki Kaisha | Image processing circuit, image display device, and an image processing method |
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