【０００１】[0001]
【産業上の利用分野】この発明は、半導体チップの実装
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting method.
【０００２】[0002]
【従来の技術】近年、システム全体の高速化ならびに高
性能化を図るために、マルチチップモジュールと称され
る半導体パッケージが開発されている。このマルチチッ
プモジュールは、予め配線を施した基板の上に複数個の
半導体チップを搭載し、これら半導体チップの電極をワ
イヤボンディング方式、ＴＡＢ方式あるいはフリップチ
ップ方式によって基板の電極パッドと電気的に接続した
ものである。2. Description of the Related Art In recent years, a semiconductor package called a multi-chip module has been developed in order to increase the speed and performance of the entire system. In this multi-chip module, a plurality of semiconductor chips are mounted on a substrate on which wiring has been performed in advance, and the electrodes of these semiconductor chips are electrically connected to the electrode pads of the substrate by a wire bonding method, a TAB method or a flip chip method. It was done.
【０００３】ところで、半導体チップの電極と基板の電
極パッドとをワイヤボンディング方式やＴＡＢ方式で電
気的に接続すると、半導体チップの周囲にボンディング
のための接続スペースを必要とすることから、実装面積
が増大し、基板への高密度実装が困難になるという難点
がある。By the way, when the electrodes of the semiconductor chip and the electrode pads of the substrate are electrically connected by a wire bonding method or a TAB method, a connection space for bonding is required around the semiconductor chip, so that the mounting area is reduced. However, there is a problem that the number is increased and it becomes difficult to perform high-density mounting on a substrate.
【０００４】これに対し、フリップチップ方式ではチッ
プ面積以外のスペースを必要としないため、ワイヤボン
ディング方式やＴＡＢ方式よりも高密度に半導体チップ
を実度することが可能である。On the other hand, the flip chip method does not require a space other than the chip area, so that the semiconductor chips can be implemented at a higher density than the wire bonding method or the TAB method.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、フリッ
プチップ方式では半導体チップを基板上にダイボンディ
ングする際に半導体チップの電極と基板の電極パッドと
の位置合わせを必要するため、多ピン狭ピッチの半導体
チップに対してはチップ電極と基板電極との位置合わせ
が難しいという難点があった。However, in the flip-chip method, it is necessary to align the electrodes of the semiconductor chip with the electrode pads of the substrate when die-bonding the semiconductor chip onto the substrate. There is a problem that it is difficult to align the chip electrode and the substrate electrode with respect to the chip.
【０００６】この発明は上述した事情に鑑みてなされた
もので、その目的はフリップチップ方式と同等もしくは
それ以上の実装密度で半導体チップを基板に実装するこ
とのできる半導体チップの実装方法を提供しようとする
ものである。The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor chip mounting method capable of mounting a semiconductor chip on a substrate at a mounting density equal to or higher than that of a flip chip method. It is what
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、請求項１に係る発明は、基板に半導体チップを装着
する第１工程と、前記半導体チップの周囲を絶縁材で被
覆する第２工程と、前記絶縁材を介して前記基板の電極
パッドおよび前記半導体チップの電極にレーザ光を照射
し、前記絶縁材によって形成された絶縁層に配線用の孔
を形成する第３工程と、前記孔に配線材料を充填する第
４工程と、前記絶縁材によって形成された絶縁層の表面
に前記孔に充填された配線材料と電気的に導通する配線
パターンを形成する第５工程とを有することを特徴とす
るものである。In order to achieve the above object, the invention according to claim 1 includes a first step of mounting a semiconductor chip on a substrate and a second step of covering the periphery of the semiconductor chip with an insulating material. A third step of irradiating the electrode pad of the substrate and the electrode of the semiconductor chip with a laser beam through the insulating material to form a hole for wiring in an insulating layer formed of the insulating material; Having a fourth step of filling the hole with a wiring material, and a fifth step of forming a wiring pattern electrically conducting to the wiring material filled in the hole on the surface of the insulating layer formed of the insulating material. It is characterized by.
【０００８】[0008]
【作用】上記の方法によると、フリップチップ方式のよ
うに基板の電極パッドと半導体チップの電極とを位置合
せする必要がないので、半導体チップが多ピン狭ピッチ
のものであっても基板に高密度に実装することができ
る。また、ワイヤボンディング方式やＴＡＢ方式のよう
にチップ面積以外のスペースを必要としないので、半導
体チップの実装密度を高めることができる。According to the method described above, it is not necessary to align the electrode pads of the substrate with the electrodes of the semiconductor chip as in the flip chip method, and therefore, even if the semiconductor chip has a multi-pin narrow pitch, it can be mounted on the substrate. Can be implemented in density. Further, unlike the wire bonding method and the TAB method, no space other than the chip area is required, so that the mounting density of semiconductor chips can be increased.
【０００９】[0009]
【実施例】以下、この発明の一実施例を図１を参照して
説明する。この発明の一実施例は、図１の（ａ）及び
（ｂ）に示すように、予め配線が施された基板１に半導
体チップ２を装着した後、半導体チップ２の周囲をポリ
イミド等の絶縁材３で所定の厚さに被覆する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In one embodiment of the present invention, as shown in FIGS. 1A and 1B, after mounting a semiconductor chip 2 on a substrate 1 on which wiring is provided in advance, the periphery of the semiconductor chip 2 is insulated with polyimide or the like. The material 3 is coated to a predetermined thickness.
【００１０】次に、被覆された絶縁材３を介して基板１
の電極パッド４および半導体チップ２の電極５にレーザ
光を照射し、図１の（ｃ）に示す如く絶縁材３によって
形成された絶縁層６に配線用の孔７をレーザ光によって
形成する（第３工程）。Next, the substrate 1 is covered with the coated insulating material 3.
The electrode pad 4 and the electrode 5 of the semiconductor chip 2 are irradiated with laser light, and a wiring hole 7 is formed by laser light in the insulating layer 6 formed of the insulating material 3 as shown in FIG. Third step).
【００１１】次に、図１の（ｄ）及び（ｅ）に示すよう
に、孔７に銅等の配線材料８を充填した後（第４工
程）、絶縁層６の表面に配線材料８と電気的に導通する
配線パターン９を真空蒸着またはプラズマＣＶＤ等によ
って形成する（第５工程）。Next, as shown in FIGS. 1D and 1E, after the wiring material 8 such as copper is filled in the hole 7 (fourth step), the wiring material 8 is formed on the surface of the insulating layer 6. The electrically conductive wiring pattern 9 is formed by vacuum deposition or plasma CVD (fifth step).
【００１２】なお、絶縁層６の表面に配線パターン９を
形成した後は、図１の（ｆ）に示すように、配線パター
ン９をポリイミド等の絶縁材１０で被覆する。このよう
に基板１に装着された半導体チップ２の周囲をポリイミ
ド等の絶縁材３で被覆した後、絶縁材３によって形成さ
れた絶縁層６に配線用の孔７をレーザ光によって形成
し、この孔７に銅等の配線材料８を充填した後、絶縁層
６の表面に配線材料８と電気的に導通する配線パターン
９を形成することにより、半導体チップ２の電極５が配
線材料８及び配線パターン９を介して基板２の電極パッ
ド４と電気的に接続される。After the wiring pattern 9 is formed on the surface of the insulating layer 6, the wiring pattern 9 is covered with an insulating material 10 such as polyimide, as shown in FIG. 1 (f). After covering the periphery of the semiconductor chip 2 mounted on the substrate 1 with the insulating material 3 such as polyimide, a hole 7 for wiring is formed in the insulating layer 6 formed by the insulating material 3 by laser light. After the hole 7 is filled with the wiring material 8 such as copper, the wiring pattern 9 electrically connected to the wiring material 8 is formed on the surface of the insulating layer 6 so that the electrode 5 of the semiconductor chip 2 can be the wiring material 8 and the wiring. It is electrically connected to the electrode pad 4 of the substrate 2 via the pattern 9.
【００１３】従って、この発明の一実施例では、半導体
チップ２を基板１に装着する際に、例えばダイボンディ
ングを行う場合、フリップチップ方式のように基板１の
電極パッド４と半導体チップ２の電極５とを位置合せす
る必要がないので、半導体チップが多ピン狭ピッチのも
のであっても基板１に高密度に実装することができる。
また、ワイヤボンディング方式やＴＡＢ方式のようにチ
ップ面積以外のスペースを必要としないので、半導体チ
ップ２の実装密度を高めることができる。Therefore, in one embodiment of the present invention, when the semiconductor chip 2 is mounted on the substrate 1, for example, when die bonding is performed, the electrode pads 4 of the substrate 1 and the electrodes of the semiconductor chip 2 are formed by flip chip method. Since it is not necessary to align 5 and 5, the semiconductor chip can be mounted on the substrate 1 at a high density even if the semiconductor chip has a multi-pin narrow pitch.
Further, unlike the wire bonding method and the TAB method, no space other than the chip area is required, so that the mounting density of the semiconductor chips 2 can be increased.
【００１４】また、この発明の一実施例によれば、図２
に示すようなマルチチップモジュールを容易に作ること
ができる。すなわち、基板１に半導体チップ２を装着
（例えばダイボンディング）した後、前述した第２工程
から第５工程を繰り返すことにより、３次元構造のマル
チチップモジュールを得ることができる。Further, according to one embodiment of the present invention, FIG.
A multi-chip module as shown in can be easily manufactured. That is, a multi-chip module having a three-dimensional structure can be obtained by mounting the semiconductor chip 2 on the substrate 1 (for example, die bonding) and then repeating the above-described second to fifth steps.
【００１５】[0015]
【発明の効果】以上説明したように、この発明によれ
ば、フリップチップ方式と同等もしくはそれ以上の実装
密度で半導体チップを基板に実装することができる。As described above, according to the present invention, semiconductor chips can be mounted on a substrate at a mounting density equal to or higher than that of the flip chip method.
【図１】この発明の一実施例に係る半導体チップの実装
方法を示す図。FIG. 1 is a diagram showing a semiconductor chip mounting method according to an embodiment of the present invention.
【図２】マルチチップモジュールの構造を示す図。FIG. 2 is a diagram showing a structure of a multi-chip module.
１…基板 ２…半導体チップ ３…絶縁材 ４…電極パッド ５…電極 ６…絶縁層 ７…孔 ８…配線材料 ９…配線パターン DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Semiconductor chip 3 ... Insulating material 4 ... Electrode pad 5 ... Electrode 6 ... Insulating layer 7 ... Hole 8 ... Wiring material 9 ... Wiring pattern
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6247726AJPH08115953A (en) | 1994-10-13 | 1994-10-13 | Semiconductor chip mounting method |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6247726AJPH08115953A (en) | 1994-10-13 | 1994-10-13 | Semiconductor chip mounting method |
| Publication Number | Publication Date |
|---|---|
| JPH08115953Atrue JPH08115953A (en) | 1996-05-07 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6247726APendingJPH08115953A (en) | 1994-10-13 | 1994-10-13 | Semiconductor chip mounting method |
| Country | Link |
|---|---|
| JP (1) | JPH08115953A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001037338A3 (en)* | 1999-11-16 | 2001-12-27 | Fraunhofer Ges Forschung | Method for integrating a chip in a printed board and integrated circuit |
| US7145228B2 (en) | 2003-03-14 | 2006-12-05 | Micron Technology, Inc. | Microelectronic devices |
| US7524775B2 (en) | 2006-07-13 | 2009-04-28 | Infineon Technologies Ag | Method for producing a dielectric layer for an electronic component |
| US8637341B2 (en) | 2008-03-12 | 2014-01-28 | Infineon Technologies Ag | Semiconductor module |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001037338A3 (en)* | 1999-11-16 | 2001-12-27 | Fraunhofer Ges Forschung | Method for integrating a chip in a printed board and integrated circuit |
| DE19954941C2 (en)* | 1999-11-16 | 2003-11-06 | Fraunhofer Ges Forschung | Method for integrating a chip within a printed circuit board |
| US7145228B2 (en) | 2003-03-14 | 2006-12-05 | Micron Technology, Inc. | Microelectronic devices |
| SG137651A1 (en)* | 2003-03-14 | 2007-12-28 | Micron Technology Inc | Microelectronic devices and methods for packaging microelectronic devices |
| US7754531B2 (en) | 2003-03-14 | 2010-07-13 | Micron Technology, Inc. | Method for packaging microelectronic devices |
| US7524775B2 (en) | 2006-07-13 | 2009-04-28 | Infineon Technologies Ag | Method for producing a dielectric layer for an electronic component |
| US8637341B2 (en) | 2008-03-12 | 2014-01-28 | Infineon Technologies Ag | Semiconductor module |
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