【０００１】[0001]
【産業上の利用分野】本発明は半導体レーザ、発光ダイ
オード等の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a semiconductor laser or a light emitting diode.
【０００２】[0002]
【従来の技術】ＩＩ−ＶＩ族化合物半導体を用いた青色
領域の発光ダイオードや青色領域の半導体レーザ等の半
導体装置（発光デバイス）が開発されている。発光ダイ
オードや半導体レーザ等の半導体装置を作製するには、
信頼性が高く且つ良好なオーミック性を有するオーミッ
ク性電極を半導体表面に形成する必要がある。2. Description of the Related Art Semiconductor devices (light emitting devices) such as blue light emitting diodes and blue region semiconductor lasers using II-VI compound semiconductors have been developed. To make semiconductor devices such as light emitting diodes and semiconductor lasers,
It is necessary to form an ohmic electrode having high reliability and good ohmic properties on the semiconductor surface.
【０００３】Ｚn1-XＭgXＳ1-YＳeY（0≦X＜1、0＜Y≦
1）等のワイドギャップＩＩ−ＶＩ族化合物半導体に対
するオーミック性電極は、ｎ型についてはＩn、Ａl、Ｇ
a等の金属を用いており、これら金属は良好なオーミッ
ク性を示している。一方、ｐ型については一般にＡu等
の金属が電極材料として使用されるが、ＩＩ−ＶＩ族化
合物半導体と金属（Ａu）との界面に電位障壁が存在す
るため、例えば順方向の立上がり印加電圧が約３０Ｖの
ショットキー性を示すなど良好なオーミック性が得られ
ない。そこで、半導体表面に界面準位を形成しオーミッ
ク性を得る試みもなされているが良好な結果は得られて
いない。Zn1-X MgX S1-Y SeY (0≤X <1, 0 <Y≤
Ohmic electrodes for wide-gap II-VI group compound semiconductors such as 1) are In, Al, G for n-type.
Metals such as a are used, and these metals show good ohmic properties. On the other hand, for p-type, a metal such as Au is generally used as an electrode material, but since a potential barrier exists at the interface between the II-VI group compound semiconductor and the metal (Au), for example, a forward applied voltage is increased. Good ohmic properties such as a Schottky property of about 30 V cannot be obtained. Therefore, attempts have been made to form an interface state on the semiconductor surface to obtain ohmic properties, but good results have not been obtained.
【０００４】また、ｐ型ＩＩ−ＶＩ族化合物半導体に対
する電極として金属に代わりナローギャップＩＩ−ＶＩ
族化合物半導体を用いた電極、例えばＺnＴe（Y.Fan et
al.,Appl.Phys.Lett.61(1992)3160）やＨgＳe（Y.Lans
ari et al.,Appl.Phys.Lett.61(1992)2554）が提案され
ている。Narrow gap II-VI instead of metal is used as an electrode for p-type II-VI group compound semiconductors.
Electrodes using group compound semiconductors, such as ZnTe (Y. Fan et al.
al., Appl.Phys.Lett.61 (1992) 3160) and HgSe (Y.Lans
ari et al., Appl. Phys. Lett. 61 (1992) 2554) have been proposed.
【０００５】[0005]
【発明が解決しようとする課題】ｐ型ＩＩ−ＶＩ族化合
物半導体に対する電極としてのＺnＴeは、ＡuやＰd／Ｐ
t／Ａu（積層体）とはオーミック性を示すが、Ｚn1-XＭ
gXＳ1-YＳeY（0≦X＜1、0＜Y≦1）、特にＺnＳeに対し
ては約１ｅＶの電位障壁が存在するため、単純にＺn1-X
ＭgXＳ1-YＳeY（0≦X＜1、0＜Y≦1）化合物に積層した
だけではオーミック性を示さない。このため、ＺnＳe
1-XＴeX混晶をＺnＴeとＺn1-XＭgXＳ1-YＳeYとの間に介
在させ電位障壁を低減することが考えられるが、ＺnＳe
1-XＴeX混晶の作製は難しく、ＺnＳe／ＺnＴe超格子を
作製し約１ｅＶの電位障壁を階段状に分散して見掛け上
の障壁を減少させるようにしている。しかしながら、超
格子層の厚みは最小で僅かに３原子層であり、生産性に
問題があるだけでなく、半導体装置が発熱を伴う場合に
は熱による相互拡散によって合金化する不利がある。ZnTe as an electrode for a p-type II-VI compound semiconductor is Au or Pd / P.
t / Au (laminate) shows ohmic properties, but Zn1-X M
gX S1-Y SeY (0 ≦ X <1, 0 <Y ≦ 1), especially for ZnSe, since there is a potential barrier of about 1 eV, simply Zn1-X
Ohmic properties are not exhibited only by stacking on a MgX S1-Y SeY (0 ≦ X <1, 0 <Y ≦ 1) compound. Therefore, ZnSe
It is considered that a 1-X TeX mixed crystal is interposed between ZnTe and Zn1-X MgX S1-Y SeY to reduce the potential barrier.
It is difficult to produce a1-X TeX mixed crystal, and a ZnSe / ZnTe superlattice is produced to disperse a potential barrier of about 1 eV stepwise to reduce the apparent barrier. However, the thickness of the superlattice layer is a minimum of only three atomic layers, which not only has a problem in productivity but also has a disadvantage of alloying by mutual diffusion due to heat when the semiconductor device generates heat.
【０００６】一方、ｐ型ＩＩ−ＶＩ族化合物半導体に対
する電極としてのＨgＳeは、ＺnＴeに比較すると電位障
壁は小さいが、Ｚn1-XＭgXＳ1-YＳeY（0≦X＜1、0＜Y≦
1）化合物に積層した場合には完全なオーミック性は示
さず、またＨgがＺn1-XＭgXＳ1-YＳeY（0≦X＜1、0＜Y
≦1）化合物に対して拡散しやすく、信頼性の面で問題
がある。On the other hand, HgSe as an electrode for a p-type II-VI group compound semiconductor has a smaller potential barrier than ZnTe, but Zn1-X MgX S1-Y SeY (0≤X <1,0 <Y ≦
1) When laminated on a compound, it does not show perfect ohmic property, and Hg is Zn1-X MgX S1-Y SeY (0 ≦ X <1, 0 <Y
≦ 1) Difficult to diffuse into the compound, and there is a problem in terms of reliability.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決すべく本
発明は、Ｚn1-XＭgXＳ1-YＳeY（0≦X＜1、0＜Y≦1）な
どｐ型ＩＩ−ＶＩ族化合物半導体上にオーミック性電極
層を形成した部分を有する半導体装置において、前記オ
ーミック性電極層を少なくともＣdＳeなどのｐ型ＩＩ−
ＶＩ族化合物半導体にて構成した。In order to solve the above problems, the present invention provides a p-type II-VI such as Zn1-X MgX S1-Y SeY (0≤X <1, 0 <Y≤1). In a semiconductor device having a portion in which an ohmic electrode layer is formed on a group compound semiconductor, the ohmic electrode layer is at least a p-type II-type such as CdSe.
It is composed of a Group VI compound semiconductor.
【０００８】ここで、前記オーミック性電極層の上に配
線等のコンタクト層としてＡu元素を含む層を形成して
もよい。また、Ｚn1-XＭgXＳ1-YＳeY層とＣdＳeとの間
にＺn1-XＣdXＳeの混晶を介在せしめてもよい。Here, a layer containing an Au element may be formed on the ohmic electrode layer as a contact layer for wiring or the like. Also, a mixed crystal of Zn1-X CdX Se may be interposed between the Zn1-X MgX S1-Y SeY layer and CdSe.
【０００９】[0009]
【作用】ｐ型ＣdＳeはＺn1-XＭgXＳ1-YＳeY（0≦X＜1、
0＜Y≦1）に対してもまたＡuに対しても電位障壁を小さ
くすることが可能なので、これらの間にｐ型ＣdＳeを含
む層を介在させることで、良好なオーミック性を得るこ
とが可能になる。FUNCTION P-type CdSe is Zn1-X MgX S1-Y SeY (0≤X <1,
Since it is possible to reduce the potential barrier for both 0 <Y ≦ 1) and Au, it is possible to obtain good ohmic properties by interposing a layer containing p-type CdSe between them. It will be possible.
【００１０】[0010]
【実施例】以下に本発明の実施例を添付図面に基づいて
説明する。図１は本発明に係る半導体装置の断面図であ
り、半導体装置はｐ型ＧaＡs基板１下面にＩn電極２が
形成され、またｐ型ＧaＡs基板１上面にはｐ型ＺnＳe層
３が形成され、このｐ型ＺnＳe層３の上面にｐ型ＣdＳe
４が形成され、更にｐ型ＣdＳe４上面にＡu電極５が形
成されている。Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of a semiconductor device according to the present invention. In the semiconductor device, an In electrode 2 is formed on the lower surface of a p-type GaAs substrate 1, and a p-type ZnSe layer 3 is formed on the upper surface of the p-type GaAs substrate 1. On the upper surface of the p-type ZnSe layer 3, p-type CdSe is formed.
4 is formed, and further an Au electrode 5 is formed on the upper surface of the p-type CdSe 4.
【００１１】ここで、前記ｐ型ＺnＳe層３及びｐ型Ｃd
Ｓe４はＭＢＥ（Molecular Beam Epitaxy）及びラジカ
ルガンを用いてｐ型ＧaＡs基板１上に順次成長せしめ
た。即ち、放電室に窒素ガス（100%）をチャンバー内真
空度が１×１０-6Torrになるまで導入し、次いで、2.45
GHzのマイクロ波を１５０Ｗ印加してラジカルを発生さ
せ、発生したラジカルを直径0.5mmの絞りから予め真空
排気された１０-4Torrの成長室に導入し、このラジカル
と各々２×１０-7Torr、４×１０-7Torrに蒸気圧を調整
したＣdとＳe分子線を、予め低抵抗ｐ型ＺnＳe層３を成
長させたｐ型ＧaＡs基板１に同時に照射してｐ型ＣdＳe
４を成長させた。成長中のｐ型ＧaＡs基板１温度は２３
０℃であった。この後、ｐ型ＣdＳe４上面に真空蒸着法
によってＡuを蒸着し、不活性雰囲気中にて熱処理を施
しＡu電極５を形成し、図１に示した半導体装置を得
る。Here, the p-type ZnSe layer 3 and the p-type Cd are formed.
Se4 was sequentially grown on the p-type GaAs substrate 1 using MBE (Molecular Beam Epitaxy) and a radical gun. That is, nitrogen gas (100%) was introduced into the discharge chamber until the degree of vacuum in the chamber reached 1 × 10−6 Torr, and then 2.45.
Microwaves in the GHz to generate radicals and 150W is applied, the generated radicals introduced into the growth chamber of 10-4 Torr in advance evacuated from aperture diameter 0.5 mm, the radicals and each 2 × 10-7 Torr The p-type GaAs substrate 1 on which the low-resistance p-type ZnSe layer 3 was previously grown was simultaneously irradiated with Cd and Se molecular beams whose vapor pressure was adjusted to 4 × 10−7 Torr to p-type CdSe.
4 was grown. The temperature of the p-type GaAs substrate 1 during growth is 23.
It was 0 ° C. After that, Au is vapor-deposited on the upper surface of the p-type CdSe 4 by a vacuum vapor deposition method, and heat treatment is performed in an inert atmosphere to form an Au electrode 5 to obtain the semiconductor device shown in FIG.
【００１２】尚、ｐ型半導体を形成するためのドーパン
トとしては上記実施例ではＮ（窒素）を用いたが、Ａ
s、Ｐ、ＬiまたはＮa或いは前記各元素を含む化合物若
しくは混合物、例えばＬi3Ｎを用いてもよい。また、ｐ
型ＺnＳe層はｐ型ＩＩ−ＶＩ族化合物半導体としてのＺ
n1-XＭgXＳ1-YＳeY（0≦X＜1、0＜Y≦1）の一例として
挙げたものであり、ＺnＳeに限定されるものではなく、
更にプラズマ発生の手段としてはマイクロ波の他、高周
波、電子サイクロトロン共鳴を用いてもよい。Although N (nitrogen) was used as the dopant for forming the p-type semiconductor in the above embodiment,
You may use s, P, Li or Na, or the compound or mixture containing said each element, for example, Li3N. Also, p
The type ZnSe layer is Z as a p-type II-VI group compound semiconductor.
n1-X MgX S1-Y SeY (0 ≦ X <1, 0 <Y ≦ 1) is given as an example, and is not limited to ZnSe,
In addition to microwaves, high frequency or electron cyclotron resonance may be used as a means for generating plasma.
【００１３】図２は図１に示した半導体装置の電流−電
圧特性（（Ａ）はＡu電極５間の電流電圧特性、（Ｂ）
はＡu電極５とＩn電極２間の電流電圧特性）を示すグラ
フであり、このグラフからは整流性は全く観察されず良
好なオーミック特性を有することが分る。FIG. 2 is a current-voltage characteristic of the semiconductor device shown in FIG. 1 ((A) is a current-voltage characteristic between the Au electrodes 5, and (B) is a characteristic curve).
Is a graph showing the current-voltage characteristics between the Au electrode 5 and the In electrode 2). From this graph, it can be seen that no rectifying property is observed and the ohmic characteristics are good.
【００１４】図３は図１に示すタイプに混晶を介在させ
た半導体装置の断面図であり、この実施例にあっては、
ｐ型ＺnＳe層３とｐ型ＣdＳe４との間にＺn1-XＣdXＳe
混晶６を介在させた構造としている。このような構造
は、ＺnとＣdの分子線強度を制御しているセル温度を相
対的に変化させることにより実現できる。また、このよ
うな構造とすることで、電位障壁の傾きを滑らかにする
ことができる。FIG. 3 is a sectional view of a semiconductor device in which a mixed crystal is interposed in the type shown in FIG. 1, and in this embodiment,
Zn1-X CdX Se between the p-type ZnSe layer 3 and the p-type CdSe 4
The structure is such that mixed crystal 6 is interposed. Such a structure can be realized by relatively changing the cell temperature controlling the molecular beam intensities of Zn and Cd. Further, with such a structure, the slope of the potential barrier can be smoothed.
【００１５】図４は金属電極の構造を異ならせた別実施
例を示す断面図であり、この実施例にあっては、前記Ａ
u電極５の代りにＰd／Ｐt／Ａu積層電極７を用いてい
る。また、この他にもＣr／Ｔi／Ａu積層体、或いはＰt
／Ａu積層体を電極として用いることができる。FIG. 4 is a cross-sectional view showing another embodiment in which the structure of the metal electrode is different. In this embodiment, the above-mentioned A
Instead of the u electrode 5, a Pd / Pt / Au laminated electrode 7 is used. In addition to this, a Cr / Ti / Au laminated body or Pt
The / Au laminate can be used as an electrode.
【００１６】図５は発光層を介在した本発明に係る半導
体装置（半導体レーザ発振器）の断面図であり、この半
導体レーザ発振器は、ｐ型ＧaＡs基板１下面にＩn電極
２が形成され、またｎ型ＧaＡs基板１４上面には低抵抗
ｎ型ＺnＳ0.06Ｓe0.94層１１が形成され、このｎ型Ｚn
Ｓ0.06Ｓe0.94層１１上にＺn0.8Ｃd0.2Ｓe発光層１２が
形成され、このＺn0.8Ｃd0.2Ｓe発光層１２上に低抵抗
ｐ型ＺnＳ0.06Ｓe0.94層１３が形成され、この低抵抗ｐ
型ＺnＳ0.06Ｓe0.94層１３上に低抵抗ｐ型ＺnＳe層３が
形成され、このｐ型ＺnＳe層３の上面にｐ型ＣdＳe４が
形成され、更にｐ型ＣdＳe４上面に絶縁層１５を介して
Ａu電極５が形成されている。FIG. 5 is a cross-sectional view of a semiconductor device (semiconductor laser oscillator) according to the present invention with a light emitting layer interposed. In this semiconductor laser oscillator, an In electrode 2 is formed on the lower surface of a p-type GaAs substrate 1, and n is formed. A low-resistance n-type ZnS0.06 Se0.94 layer 11 is formed on the upper surface of the n-type GaAs substrate 14.
A Zn0.8 Cd0.2 Se light emitting layer 12 is formed on the S0.06 Se0.94 layer 11, and a low resistance p-type ZnS0.06 Se0.94 layer 13 is formed on this Zn0.8 Cd0.2 Se light emitting layer 12, and this low resistance p is formed.
A low-resistance p-type ZnSe layer 3 is formed on the p-type ZnS0.06 Se0.94 layer 13, p-type CdSe 4 is formed on the upper surface of this p-type ZnSe layer 3, and an Au electrode is formed on the upper surface of the p-type CdSe 4 via an insulating layer 15. 5 is formed.
【００１７】図６は図５に示した半導体装置（半導体レ
ーザ発振器）の電流−電圧特性を示すグラフであり、従
来構造の電極では順方向立上がり印加電圧が約３０Ｖで
あったのが本発明の構造によれば約５Ｖに低減された。
また、本発明装置にあっては０℃で５１０ｎｍに発振ピ
ークをもつ青緑発光が観察された。FIG. 6 is a graph showing the current-voltage characteristics of the semiconductor device (semiconductor laser oscillator) shown in FIG. 5. In the electrode of the conventional structure, the forward rising voltage applied is about 30 V. According to the structure, it was reduced to about 5V.
Further, in the device of the present invention, blue-green light emission having an oscillation peak at 510 nm was observed at 0 ° C.
【００１８】図７は図５に示すタイプに混晶を介在させ
た半導体装置の断面図であり、この実施例にあっては図
３に示した実施例と同様に、ｐ型ＺnＳe層３とｐ型Ｃd
Ｓe４との間にＺn1-XＣdXＳe混晶６を介在させた構造と
している。上記図５、図７において、Ａu電極の代りに
Ｐd／Ｐt／Ａuとすることも可能であり、Ｉnの代りにＡ
u／Ｇe／Ｎiとすることも可能である。FIG. 7 is a sectional view of a semiconductor device in which a mixed crystal of the type shown in FIG. 5 is interposed. In this embodiment, a p-type ZnSe layer 3 and a p-type ZnSe layer 3 are formed as in the embodiment shown in FIG. p-type Cd
The structure is such that a Zn1-X CdX Se mixed crystal 6 is interposed between it and Se 4. 5 and 7, Pd / Pt / Au can be used instead of the Au electrode, and A can be used instead of In.
It is also possible to use u / Ge / Ni.
【００１９】[0019]
【発明の効果】以上の説明から明らかなように本発明に
よれば、Ｚn1-XＭgXＳ1-YＳeY（0≦X＜1、0＜Y≦1）な
どｐ型ＩＩ−ＶＩ族化合物半導体上にｐ型ＣdＳeなどの
ＩＩ−ＶＩ族化合物半導体からなるオーミック性電極層
を形成したので、良好なるオーミック性が得られ、電極
半導体界面に電解集中が起こらず半導体装置の破損や発
熱による悪影響を受けることがなく、半導体装置の長寿
命化が図れる。As is apparent from the above description, according to the present invention, a p-type II-VI compound such as Zn1-X MgXS1-Y SeY (0≤X <1, 0 <Y≤1) is used. Since the ohmic electrode layer made of a II-VI group compound semiconductor such as p-type CdSe is formed on the semiconductor, good ohmic properties are obtained, and no electrolytic concentration occurs at the electrode-semiconductor interface, which adversely affects the damage or heat generation of the semiconductor device. The life of the semiconductor device can be extended without receiving the damage.
【００２０】オーミック性電極層の上に配線等のコンタ
クト層としてＡu元素を含む層を形成した場合には、Ａu
とｐ型ＣdＳeとの間にも良好なオーミック性を有する半
導体装置が得られる。When a layer containing an Au element is formed as a contact layer for wiring or the like on the ohmic electrode layer, Au is used.
It is possible to obtain a semiconductor device having a good ohmic contact between p-type and CdSe.
【００２１】また、Ｚn1-XＭgXＳ1-YＳeY層とＣdＳeと
の間にＺn1-XＣdXＳeの混晶を介在せしめるようにすれ
ば、より滑らかな電位障壁の傾きを有するオーミック性
電極を形成することができる。If a mixed crystal of Zn1-X CdX Se is interposed between the Zn1-X MgX S1-Y SeY layer and CdSe, a smoother slope of the potential barrier can be obtained. An ohmic electrode having the same can be formed.
【図１】本発明に係る半導体装置の断面図FIG. 1 is a sectional view of a semiconductor device according to the present invention.
【図２】図１に示した半導体装置の電流−電圧特性を示
すグラフFIG. 2 is a graph showing current-voltage characteristics of the semiconductor device shown in FIG.
【図３】図１に示すタイプに混晶を介在させた半導体装
置の断面図FIG. 3 is a sectional view of a semiconductor device in which a mixed crystal is interposed in the type shown in FIG.
【図４】金属電極の構造を異ならせた別実施例を示す断
面図FIG. 4 is a sectional view showing another embodiment in which the structure of the metal electrode is different.
【図５】発光層を介在した本発明に係る半導体装置の断
面図FIG. 5 is a cross-sectional view of a semiconductor device according to the present invention with a light emitting layer interposed.
【図６】図５に示した半導体装置の電流−電圧特性を示
すグラフ6 is a graph showing current-voltage characteristics of the semiconductor device shown in FIG.
【図７】図５に示すタイプに混晶を介在させた半導体装
置の断面図FIG. 7 is a cross-sectional view of a semiconductor device in which a mixed crystal is interposed in the type shown in FIG.
１…ｐ型ＧaＡs基板、２…Ｉn電極、３…ｐ型ＺnＳe
層、４…ｐ型ＣdＳe、５…Ａu電極、６…Ｚn1-XＣdXＳe
混晶、７…Ｐd／Ｐt／Ａu積層電極、 １１…低抵抗ｎ型
ＺnＳ0.06Ｓe0.94層、１２…Ｚn0.8Ｃd0.2Ｓe発光層、
１３…低抵抗ｐ型ＺnＳ0.06Ｓe0.94層、１４…ｎ型Ｇa
Ａs基板。1 ... p-type GaAs substrate, 2 ... In electrode, 3 ... p-type ZnSe
Layers, 4 ... P-type CdSe, 5 ... Au electrodes, 6 ... Zn1-X CdX Se
Mixed crystal, 7 ... Pd / Pt / Au laminated electrode, 11 ... Low resistance n-type ZnS0.06 Se0.94 layer, 12 ... Zn0.8 Cd0.2 Se light emitting layer,
13 ... Low resistance p-type ZnS0.06 Se0.94 layer, 14 ... n-type Ga
As substrate.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 八百 隆文 広島県東広島市鏡山１丁目４番１号 広島 大学内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takafumi Yao 1-4-1 Kagamiyama, Higashihiroshima City, Hiroshima Prefecture Hiroshima University
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| JP35187693AJP3501299B2 (en) | 1993-12-28 | 1993-12-28 | Semiconductor device |
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