【０００１】[0001]
【産業上の利用分野】この発明は、半導体チップの所望
ピンから電気信号を正確，簡単に取り出すための半導体
チップ用信号取出しアダプタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip signal extraction adapter for accurately and easily extracting an electric signal from a desired pin of a semiconductor chip.
【０００２】[0002]
【従来の技術】近年、電子機器の小形化，高性能化の要
求に応じて適用電子部品は、ＩＣ部品ではスモール・ア
ウトライン・パッケージのように表面実装形部品が主流
になりつつある。この表面実装形部品は、それ自体のピ
ン間隔が狭く、また各部品がプリント配線板に実装され
るときは高密度におこなわれる傾向にある。しかも、高
性能化された電子機器の試作段階，製品段階における性
能確認，保守のために、部品の所望ピンから電気信号を
取り出して観測する必要性がますます増大する。そのた
めに用いられる補助具について、図８，図９を参照しな
がら説明する。図８は一従来例の使用時における側面
図、図９は別の従来例の使用時における側面図である。2. Description of the Related Art In recent years, in response to demands for miniaturization and high performance of electronic equipment, surface mount type parts such as small outline packages are becoming the mainstream for electronic parts to be applied. This surface mount type component has a narrow pin interval between itself and tends to be densely packed when each component is mounted on a printed wiring board. In addition, it becomes more and more necessary to take out electrical signals from desired pins of parts and observe them for performance confirmation and maintenance at the prototype stage and product stage of high performance electronic devices. Auxiliary tools used for that purpose will be described with reference to FIGS. 8 and 9. FIG. 8 is a side view of a conventional example when it is used, and FIG. 9 is a side view of another conventional example when it is used.
【０００３】図８において、一従来例としてのアダプタ
30は、クリップ形式の市販品で、プリント配線板7 に表
面実装されるＩＣチップ8 の、所望の信号用と接地用と
の各ピン9 に、これを挟む形で接続され、この各ピン9
から信号が取り出される。図９において、別の従来例と
してのプローブ31は、実装されたＩＣチップ8 の、所望
の信号用と接地用との各ピン9 に接触させる形で接続さ
れ、この各ピン9 から信号が取り出される。In FIG. 8, an adapter as a conventional example
30 is a commercially available clip type product, which is connected to each pin 9 for desired signal and for grounding of the IC chip 8 which is surface-mounted on the printed wiring board 7 by sandwiching them.
The signal is extracted from. In FIG. 9, a probe 31 as another conventional example is connected so as to be in contact with the desired signal and ground pins 9 of the mounted IC chip 8, and signals are taken out from these pins 9. Be done.
【０００４】[0004]
【発明が解決しようとする課題】一従来例としてのアダ
プタ30では、とかく引出し線が長くなるため、信号が高
速信号の場合には、インダクタンス成分や線間のキャパ
シタンス成分が無視できなくなり、観測波形を歪ませる
原因になって、観測の信頼性を損なう。また、アダプタ
30の取付けのために広いスペースが必要なのも使用上問
題である。別の従来例としてのプローブ31では、その先
端部を各ピン9 に当て、手で保持しながら観測がおこな
われるため、この保持状態が不安定であって、接触不良
や隣り合うピンとの短絡などの不具合を生じ、その結
果、観測の信頼性が低下する。In the adapter 30 as a conventional example, since the lead wire becomes long anyway, when the signal is a high-speed signal, the inductance component and the capacitance component between the lines cannot be ignored and the observed waveform And distort the reliability of the observation. Also the adapter
It is also a problem in use that a large space is required for mounting 30. In another conventional probe 31, the tip end is applied to each pin 9 and observation is performed while holding it by hand, so this holding state is unstable, contact failure, short circuit between adjacent pins, etc. However, the reliability of observation decreases as a result.
【０００５】この発明の課題は、従来の技術がもつ以上
の問題点を解消し、半導体チップの所望ピンから電気信
号を正確，簡単に取り出すための半導体チップ用信号取
出しアダプタを提供することにある。An object of the present invention is to solve the above problems of the prior art and to provide a semiconductor chip signal extraction adapter for accurately and easily extracting an electrical signal from a desired pin of a semiconductor chip. .
【０００６】[0006]
【課題を解決するための手段】請求項１に係る信号取出
しアダプタは、半導体チップの各ピンに対応して並設さ
れる接触部、および試験用プローブが挿入される受口部
が導通接続されてなり、絶縁性基体に設けられる接続部
と；基体に設けられ、半導体チップに対して掛け止めさ
れる掛止部と；を備える。According to a first aspect of the present invention, there is provided a signal take-out adapter in which a contact portion arranged in parallel with each pin of a semiconductor chip and a receiving portion into which a test probe is inserted are electrically connected. A connecting part provided on the insulating base; and a hooking part provided on the base and hooked on the semiconductor chip.
【０００７】請求項２に係る信号取出しアダプタは、請
求項１に記載のアダプタにおいて、受口部が、信号用ま
たは電源用として接触部の列と平行に両側の２列に配設
されるとともに、接地用として基体内で共通に接続され
て中央の１列に配設され、かつ隣り合う列の間隔が同一
である。請求項３に係る信号取出しアダプタは、半導体
チップの各ピンに対応して並設される接触部、試験用プ
ローブが挿入される第１の受口部、および基体表面に露
出する第１の端子部が導通接続されてなり、絶縁性基体
に設けられる第１の接続部と；試験用プローブが挿入さ
れる第２の受口部、および第２の端子部が導通接続され
てなり、基体に設けられる第２の接続部と；基体に設け
られ、半導体チップに対して掛け止めされる掛止部と；
を備える。A signal take-out adapter according to a second aspect is the adapter according to the first aspect, wherein the receiving portions are arranged in two rows on both sides in parallel with the row of the contact portions for signal or power supply. , Are connected in common in the base body for grounding, are arranged in one central row, and the intervals between adjacent rows are the same. The signal take-out adapter according to claim 3 includes a contact portion arranged in parallel corresponding to each pin of the semiconductor chip, a first receiving portion into which the test probe is inserted, and a first terminal exposed on the surface of the substrate. The first connecting portion provided on the insulating base, the second receiving portion into which the test probe is inserted, and the second terminal portion being conductively connected to the base. A second connection portion provided; a hook portion provided on the base body and hooked to the semiconductor chip;
Equipped with.
【０００８】請求項４に係る信号取出しアダプタは、請
求項３に記載のアダプタにおいて、第１受口部が、信号
用，接地用または電源用として接触部の列と平行に２列
に配設され、第２受口部が、接地用として中央の１列に
配設され、かつ隣り合う列の間隔が同一である。A signal take-out adapter according to a fourth aspect is the adapter according to the third aspect, wherein the first receptacles are arranged in two rows parallel to the row of contact portions for signal, ground or power supply. The second sockets are arranged in the central one row for grounding, and the intervals between the adjacent rows are the same.
【０００９】[0009]
【作用】請求項１または２に係る信号取出しアダプタで
は、半導体チップの各ピンに接続部の接触部を接触さ
せ、掛止部によって半導体チップに基体を掛け止めした
後に、接地ピンに対応する接続部の受口部と、所望の信
号ピンに対応する接続部の受口部とに試験プローブを挿
入することによって、その所望の信号ピンからの信号が
取り出される。In the signal take-out adapter according to the first or second aspect of the present invention, each pin of the semiconductor chip is brought into contact with the contact portion of the connecting portion, and the base is hooked on the semiconductor chip by the hooking portion, and then the connection corresponding to the ground pin is made. The signal from the desired signal pin is extracted by inserting the test probe into the receiving part of the part and the receiving part of the connection part corresponding to the desired signal pin.
【００１０】とくに請求項２に係る信号取出しアダプタ
では、両側のいずれかの列の信号用受口部と、これと隣
り合う中央列の接地用受口部とに、これと同じ間隔の試
験用ジャックを介し、試験用プローブを挿入して信号が
取り出される。請求項３または４に係る信号取出しアダ
プタでは、半導体チップの各ピンに第１接続部の接触部
を接触させ、掛止部によって半導体チップに基体を掛け
止めした後に、接地ピンに対応する第１接続部の端子部
と、第２接続部の端子部とを接続線によって導通接続
し、その第２接続部の受口部と、所望の信号ピンに対応
する第１接続部の受口部とに試験プローブを挿入するこ
とによって、その所望の信号ピンからの信号が取り出さ
れる。Particularly, in the signal take-out adapter according to the second aspect of the present invention, the signal receiving portion of one of the rows on both sides and the grounding receiving portion of the center row adjacent to the signal receiving portion are provided at the same intervals for testing. The test probe is inserted through the jack to extract the signal. In the signal take-out adapter according to claim 3 or 4, the pins of the semiconductor chip are brought into contact with the contact portions of the first connecting portion, and the base portion is hooked on the semiconductor chip by the hooking portion, and then the first pin corresponding to the ground pin is attached. The terminal portion of the connecting portion and the terminal portion of the second connecting portion are electrically connected by a connecting wire, and the receiving portion of the second connecting portion and the receiving portion of the first connecting portion corresponding to a desired signal pin are provided. The signal from the desired signal pin is extracted by inserting the test probe into.
【００１１】とくに請求項４に係る信号取出しアダプタ
では、両側のいずれかの列の第１の信号用受口部と、こ
れと隣り合う中央列の第２の接地用受口部とに、これと
同じ間隔の試験用ジャックを介し、試験用プローブを挿
入して信号が取り出される。また、両側のいずれかの列
にある第１の信号用受口部と、これと隣り合う中央列の
第２の接地用受口部とに、これと同じ端子間隔の回路部
品、たとえばプルアップ，プルダウン用の各抵抗器を挿
入することができる。Particularly, in the signal take-out adapter according to the fourth aspect, the first signal receiving portion in either row on both sides and the second grounding receiving portion in the central row adjacent thereto are provided. The signal is taken out by inserting the test probe through the test jack at the same interval as. Further, a circuit component having the same terminal spacing, for example, a pull-up, in the first signal receiving portion in either row on both sides and the second grounding receiving portion in the central row adjacent to the first signal receiving portion. Each pull-down resistor can be inserted.
【００１２】[0012]
【実施例】この発明に係る信号取出しアダプタの実施例
について、以下に図を参照しながら説明する。図１は第
１実施例であるアダプタ10の平面図、図２はそのＡ−Ａ
断面に係る断面図、図３は同じくその正面図である。図
１において、プラスチック成形品としての絶縁性基体１
に、以下に述べるユニットが挿入成形される。ユニット
は大別して3 種類あり、第１, 第２は、バネ性をもつ接
触部2a,4a と、試験用プローブが挿入される受口部2b,4
b とがそれぞれ導通接続される信号用, 電源用の各ユニ
ットで、第３は、バネ性をもつ1 個の接触部3aと、試験
用プローブが挿入される10個の受口部3bとが、共通に板
状の接地層3cを介して導通接続される接地用ユニットで
ある( 図2 参照) 。ところで、各接触部2a,3a,4aと、各
受口部2b,3b,4bとは信号用, 接地用, 電極用の使用上の
別はあるが、部材としては全て共通である。図1 におい
て、信号用ユニットは、左側列の下端と右側列の上端と
を除く全てである。電源用ユニットは右側列の上端に位
置し、また接地用ユニットは、その接触部3aが左側列の
下端に位置し、その受口部3bが中央列の全てである。言
いかえれば、各接触部2a,3a,4aは、ここに図示してない
半導体チップの、信号ピン, 接地ピン, 電源ピンにそれ
ぞれ対応し、これと接触するようにアダプタ10が、基体
1 両端のフック5 によって、半導体チップに掛止め装着
される。なお、図1 において、左側列, 中央列, 右側列
の隣り合う列間隔は同一である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the signal extraction adapter according to the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an adapter 10 according to the first embodiment, and FIG. 2 is its AA.
A sectional view relating to the section and FIG. 3 are front views thereof. In FIG. 1, an insulating substrate 1 as a plastic molded product.
Then, the unit described below is insert-molded. There are roughly three types of units. The first and second units are contact portions 2a and 4a having spring properties and socket portions 2b and 4 into which test probes are inserted.
b is a unit for signals and a unit for power supply, which are conductively connected to each other. Thirdly, one contact part 3a having a spring property and ten receiving parts 3b into which a test probe is inserted are provided. Is a grounding unit that is electrically connected in common via a plate-shaped grounding layer 3c (see FIG. 2). By the way, the contact portions 2a, 3a, 4a and the respective receptacle portions 2b, 3b, 4b are different in use for signals, grounds, and electrodes, but they are all common members. In FIG. 1, the signal units are all except the lower end of the left column and the upper end of the right column. The power supply unit is located at the upper end of the right column, and the grounding unit has its contact portion 3a located at the lower end of the left column, and its socket 3b is the central column. In other words, the contact portions 2a, 3a, 4a correspond to the signal pin, the ground pin, and the power pin, respectively, of the semiconductor chip (not shown), and the adapter 10 is connected to the base so as to make contact therewith.
1 Hooks 5 on both ends attach to the semiconductor chip. In FIG. 1, the left column, the center column, and the right column have the same interval between adjacent columns.
【００１３】第１実施例の使用方法について、図４の使
用時における正面図、図５の同じくその側面図を参照し
ながら説明する。図4 において、プリント配線板7 に表
面実装されたＩＣチップ8 の各ピンから、アダプタ10を
用いて信号取出しがおこなわれる。アダプタ10は、その
各接触部( 図1,図2 参照) をＩＣチップ8 の対応するピ
ン9(代表符号) にそれぞれ接触させる形で、ＩＣチップ
8 にフック5 によって掛止め装着される( 図5 参照) 。
図5 において、試験用プローブ24は、テスト用ジャック
23を介して対応する受口部に挿入される。テスト用ジャ
ック23は、先端部が二股になっていて、一方の端部が所
望の信号用受口部に、他方の端部が接地用受口部にそれ
ぞれ挿入される。図1 で具体的に説明すると、所望の信
号取出し用の信号ピンに対応する信号用受口部2bが、左
側列の下から5 番目であるとし、これと、それに隣り合
う、つまり直ぐ右の接地用受口部3bとにテスト用ジャッ
ク23を挿入し、これにプローブ24を挿入する。したがっ
て、信号取出し箇所に応じて、その都度テスト用ジャッ
ク23は、左側列または右側列の信号用受口部2bと、それ
と隣り合う中央列の接地用受口部3bとに挿入される。こ
のテスト用ジャック23の使用によって、多数箇所の所望
ピンからの信号取出しが非常に容易，迅速にできる。The method of using the first embodiment will be described with reference to the front view of FIG. 4 in use and the side view of FIG. In FIG. 4, a signal is taken out from each pin of the IC chip 8 surface-mounted on the printed wiring board 7 using the adapter 10. The adapter 10 has its contact parts (see FIGS. 1 and 2) contacting the corresponding pins 9 (representative symbol) of the IC chip 8 respectively.
It is attached to 8 by hook 5 (see Fig. 5).
In FIG. 5, the test probe 24 is a test jack.
It is inserted into the corresponding socket through 23. The tip of the test jack 23 is bifurcated, one end of which is inserted into a desired signal receiving portion and the other end of which is inserted into a grounding receiving portion. Specifically, referring to FIG. 1, it is assumed that the signal receiving portion 2b corresponding to the signal pin for extracting a desired signal is the fifth from the bottom of the left column and is adjacent to it, that is, immediately to the right. The test jack 23 is inserted into the grounding receptacle 3b, and the probe 24 is inserted therein. Therefore, the test jacks 23 are inserted into the signal receptacles 2b in the left column or the right column and the ground receptacles 3b in the center column adjacent to the signal jacks 2b in each case, depending on the signal extraction location. By using this test jack 23, it is very easy and quick to take out signals from a large number of desired pins.
【００１４】図６は第２実施例の平面図、図７はそのＢ
−Ｂ断面に係る断面図である。第２実施例であるアダプ
タ20が第１実施例のアダプタ10と異なる点は、対象のＩ
Ｃチップの形式によって接地ピンの位置が違っても柔軟
に対応できることである。これらの図において、プラス
チック成形品としての絶縁性基体11に、以下に述べるユ
ニットが挿入成形される。ユニットは大別して2 種類あ
り、その第１は、接触部12a と、試験用プローブが挿入
される受口部12b と、端子部12d とがそれぞれ導通接続
されるユニットで、左側列, 右側列としてそれぞれ10個
設けられ、それぞれが信号用, 接地用, 電源用に使い分
けられる。その第２は、左右の各側に突起状端子部を有
する板状接地層13と、10個の受口部12b とが導通接続さ
れる接地用ユニットで、基体11の中央に露出する形で設
けられる。図6 において、P 矢印の左側列の下から7 番
目と、Q 矢印の右側列の下から4 番目とに位置する各接
触部12a が、図示してないＩＣチップの接地ピンに対応
する。また、とくに図示してないが、1 または2 個の接
触部が電源ピンに対応する。それ以外の接触部が、ＩＣ
チップの信号ピンに対応する。ここで、受口部12b の左
側列, 中央列, 右側列の隣り合う列間隔は同一であるよ
うに設計される。FIG. 6 is a plan view of the second embodiment, and FIG. 7 is its B.
It is sectional drawing concerning the -B cross section. The adapter 20 of the second embodiment differs from the adapter 10 of the first embodiment in that the target I
Even if the position of the ground pin differs depending on the type of C chip, it can be flexibly dealt with. In these figures, the unit described below is insert-molded into an insulating base 11 as a plastic molded product. There are roughly two types of units. The first is a unit in which the contact part 12a, the socket part 12b into which the test probe is inserted, and the terminal part 12d are conductively connected. There are 10 of each, and each is used for signals, grounds, and power supplies. The second is a grounding unit in which a plate-shaped grounding layer 13 having projecting terminal portions on each of the left and right sides and 10 sockets 12b are electrically connected, and are exposed in the center of the base 11. It is provided. In FIG. 6, the contact parts 12a located at the seventh from the bottom of the left column of the P arrow and the fourth from the bottom of the right column of the Q arrow correspond to the ground pins of the IC chip (not shown). Also, although not particularly shown, one or two contacts correspond to the power pins. Other contact parts are IC
Corresponds to the signal pin of the chip. Here, the left column, the center column, and the right column of the receiving portion 12b are designed so that adjacent column intervals are the same.
【００１５】信号取出しの準備として、まず接地ピンに
対応する、各矢印P,Q の位置にある端子部12d と、接地
層13のこれと隣り合う端子部とが、接続線21によってハ
ンダ付けされる。次に、アダプタ20が、その各接触部12
a を、図示してない半導体チップの各ピンと接触させる
形で、基体1 両端のフック5 によって半導体チップに掛
止め装着される。所望の信号ピンに対応する受口部12b
、たとえば左側列の下から5 番目と、中央列の同じ下
から5 番目の受口部12b とに、図5 に示したテスト用ジ
ャック23を挿入し、これを介してプローブ24によって、
その所望の信号ピンからの信号が取り出される。したが
って、とくに、半導体チップの形式によって接地用ピン
の位置が変わることがあっても、接続線を用いることで
柔軟に対応可能で、さらに簡便さが支援される。ところ
で、図６に示したように、必要に応じて左側, 右側のい
ずれかの列にある信号用受口部と、これと隣り合う中央
列の接地用受口部とに、これと同じ端子間隔の回路部品
22としてのプルアップ，プルダウン用の各抵抗器を挿入
することにより、ハイインピーダンス状態を防止し、ひ
いてノイズ対策を講じることができる。なお、接続線21
は、プルアップのときには、電源側端子部, 接地層13間
に、プルダウンのときには、接地側端子部, 接地層13間
にそれぞれ接続される。In preparation for signal extraction, first, the terminal portion 12d corresponding to the ground pin at the position of each arrow P, Q and the terminal portion adjacent to this of the ground layer 13 are soldered by the connecting wire 21. It The adapter 20 then attaches each contact 12
The a is brought into contact with each pin of the semiconductor chip (not shown), and is hooked and attached to the semiconductor chip by the hooks 5 at both ends of the base 1. Receptacle 12b corresponding to the desired signal pin
For example, insert the test jack 23 shown in Fig. 5 into the fifth row from the bottom of the left column and the fifth bottom slot 12b from the same in the center row, and through this, with the probe 24,
The signal from the desired signal pin is taken out. Therefore, in particular, even if the position of the grounding pin is changed depending on the type of the semiconductor chip, it is possible to flexibly deal with it by using the connection line, and the simplicity is further supported. By the way, as shown in FIG. 6, if necessary, the same receptacles are provided on the signal receptacles on either the left or right row and the ground receptacles on the center row adjacent to the signal receptacles. Spacing circuit components
By inserting the pull-up and pull-down resistors as 22, it is possible to prevent a high impedance state and take noise countermeasures. In addition, connection line 21
Are connected between the power supply side terminal portion and the ground layer 13 when pulling up, and between the grounding side terminal portion and the ground layer 13 when pulling down.
【００１６】なお、以上に述べた第１，第２の各実施例
に係る半導体チップは、表面実装形で、ピンが鴎翼形で
方形の対向する２辺に出ている、いわゆるＳＯＰ(Small
Out-Line Package)である。しかし、この各実施例は、
一般に挿入実装形や、ピン形状がＪ形、ピンが方形の４
辺のすべてに出ている形式などの半導体チップにも、接
触部の形状を変えることで同様に適用可能である。たと
えば、ＳＯＪ(Small Out-Line J-leaded Package) 、Ｑ
ＦＰ(Quad Flat Package) 、ＱＦＪ(Quad FlatJ-leaded
Package) などに対しても適用できる。The semiconductor chips according to the first and second embodiments described above are of the surface mount type, and the pins are so-called wing-shaped and are formed on two opposite sides of a square, so-called SOP (Small).
Out-Line Package). However, each of these examples
Generally, insert mounting type, J-shaped pin, square pin
The present invention can be similarly applied to a semiconductor chip such as a type that appears on all sides by changing the shape of the contact portion. For example, SOJ (Small Out-Line J-leaded Package), Q
FP (Quad Flat Package), QFJ (Quad Flat J-leaded
Package) etc.
【００１７】[0017]
【発明の効果】請求項１または２に係る信号取出しアダ
プタでは、半導体チップの各ピンに接続部の接触部を接
触させ、掛止部によって半導体チップに基体を掛け止め
した後に、接地ピンに対応する接続部の受口部と、所望
の信号ピン，接地ピンに対応する接続部の受口部とに試
験プローブを挿入することによって、その所望の信号ピ
ンからの信号が取り出される。したがって、プローブが
所望のピン，接地ピンに対応する受口部に挿入され、か
つこの接触が確実，安定しているから、ピン間隔が狭
く、隣り合うもの同士が近接した半導体チップの所望ピ
ンからの電気信号が正確，簡便に取り出され、電子機器
の性能確認や保守が適正におこなわれる。In the signal extraction adapter according to the first or second aspect of the present invention, each pin of the semiconductor chip is brought into contact with the contact portion of the connecting portion, and the base portion is hooked on the semiconductor chip by the hooking portion, and then the grounding pin is handled. By inserting the test probe into the receptacle of the connecting portion and the receptacle of the connecting portion corresponding to the desired signal pin and the ground pin, the signal from the desired signal pin is taken out. Therefore, since the probe is inserted into the receptacle corresponding to the desired pin and the ground pin, and this contact is reliable and stable, the pin interval is narrow and the adjacent pins are close to each other from the desired pin of the semiconductor chip. The electric signals of are accurately and easily taken out, and the performance confirmation and maintenance of electronic devices are properly performed.
【００１８】とくに請求項２に係る信号取出しアダプタ
では、両側のいずれかの列の信号用受口部と、これと隣
り合う中央列の接地用受口部とに、これと同じ間隔の試
験用ジャックを介し、試験用プローブを挿入して信号が
取り出される。したがって、試験用ジャックの使用によ
って、多数箇所の所望ピンからの信号取出しが容易，迅
速にでき簡便さが支援される。Particularly, in the signal take-out adapter according to the second aspect of the present invention, the signal receiving portion of one of the rows on both sides and the grounding receiving portion of the central row adjacent to the signal receiving portion are provided at the same intervals for the test. The test probe is inserted through the jack to extract the signal. Therefore, the use of the test jack facilitates quick and easy signal extraction from desired pins at a large number of locations, which facilitates convenience.
【００１９】請求項３または４に係る信号取出しアダプ
タでは、半導体チップの各ピンに第１接続部の接触部を
接触させ、掛止部によって半導体チップに基体を掛け止
めした後に、接地ピンに対応する第１接続部の端子部
と、第２接続部の端子部とを接続線によって導通接続
し、その第２接続部の受口部と、所望の信号ピンに対応
する第１接続部の受口部とに試験プローブを挿入するこ
とによって、その所望の信号ピンからの信号が取り出さ
れる。したがって、請求項１または２に係る信号取出し
アダプタと同じ効果が得られる外に、とくに、半導体チ
ップの形式によって接地ピンの位置が変わることがあっ
ても、接続線を用いることで柔軟に対応可能で、簡便さ
が支援される。In the signal extraction adapter according to the third or fourth aspect of the present invention, each pin of the semiconductor chip is brought into contact with the contact portion of the first connecting portion, and the base portion is hooked on the semiconductor chip by the hooking portion, and then the grounding pin is applied. The terminal portion of the first connecting portion and the terminal portion of the second connecting portion are electrically connected by a connecting wire, and the receiving portion of the second connecting portion and the receiving portion of the first connecting portion corresponding to the desired signal pin are connected. By inserting the test probe into the mouth, the signal from the desired signal pin is extracted. Therefore, in addition to the same effect as the signal extraction adapter according to claim 1 or 2, even if the position of the ground pin may change depending on the type of the semiconductor chip, it is possible to flexibly deal with it by using the connection line. Therefore, convenience is supported.
【００２０】とくに請求項４に係る信号取出しアダプタ
では、両側のいずれかの列の第１の信号用受口部と、こ
れと隣り合う中央列の第２の接地用受口部とに、これと
同じ間隔の試験用ジャックを介し、試験用プローブを挿
入して信号が取り出される。また、両側のいずれかの列
にある第１の信号用受口部と、これと隣り合う中央列の
第２の接地用受口部とに、これと同じ端子間隔の回路部
品、たとえばプルアップ，プルダウン用の各抵抗器を挿
入することができる。したがって、試験用ジャックの使
用によって、多数箇所の所望ピンからの信号取出しが容
易，迅速にでき簡便さが支援されるとともに、必要に応
じてプルアップ，プルダウン用の各抵抗器の挿入によっ
て、ハイインピーダンス状態を防止し、ひいてノイズ対
策を講じることができる。Particularly, in the signal take-out adapter according to the fourth aspect, the first signal receiving portion in either row on both sides and the second grounding receiving portion in the central row adjacent thereto are provided. The signal is taken out by inserting the test probe through the test jack at the same interval as. Further, a circuit component having the same terminal spacing, for example, a pull-up, in the first signal receiving portion in either row on both sides and the second grounding receiving portion in the central row adjacent to the first signal receiving portion. Each pull-down resistor can be inserted. Therefore, by using the test jack, it is possible to easily and quickly take out the signals from the desired pins at multiple points, and the convenience is supported, and by inserting the pull-up and pull-down resistors as necessary, Impedance conditions can be prevented, and noise countermeasures can be taken.
【図１】発明に係る第１実施例の平面図FIG. 1 is a plan view of a first embodiment according to the invention.
【図２】図１のＡ−Ａ断面に係る断面図2 is a sectional view taken along the line AA of FIG.
【図３】第１実施例の正面図FIG. 3 is a front view of the first embodiment.
【図４】第１実施例の使用時における正面図FIG. 4 is a front view when the first embodiment is used.
【図５】同じくその側面図FIG. 5 is a side view of the same.
【図６】発明に係る第２実施例の平面図FIG. 6 is a plan view of a second embodiment according to the invention.
【図７】図６のＢ−Ｂ断面に係る断面図7 is a sectional view taken along the line BB of FIG.
【図８】一従来例の使用時における側面図FIG. 8 is a side view when one conventional example is used.
【図９】別の従来例の使用時における側面図FIG. 9 is a side view when another conventional example is used.
１ 基体 ２ａ，３ａ，４ａ 接触部 ２ｂ，３ｂ，４ｂ 受口部 ３ｃ 接地層 ５ フック ７ プリント配線板 ８ ＩＣチップ ９ ピン １０ アダプタ １１ 基体 １２ａ 接触部 １２ｂ 受口部 １２ｄ 端子部 １３ 接地層 １５ フック ２０ アダプタ ２１ 接続線 ２２ 回路部品 ２３ テスト用ジャック ２４ プローブ 1 Base 2a, 3a, 4a Contact part 2b, 3b, 4b Receptacle part 3c Ground layer 5 Hook 7 Printed wiring board 8 IC chip 9 pins 10 Adapter 11 Base 12a Contact part 12b Receptacle part 12d Terminal part 13 Ground layer 15 hook 20 Adapter 21 Connection Wire 22 Circuit Parts 23 Test Jack 24 Probe
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5068943AJPH06281697A (en) | 1993-03-29 | 1993-03-29 | Signal adapter for semiconductor chip |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5068943AJPH06281697A (en) | 1993-03-29 | 1993-03-29 | Signal adapter for semiconductor chip |
| Publication Number | Publication Date |
|---|---|
| JPH06281697Atrue JPH06281697A (en) | 1994-10-07 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5068943APendingJPH06281697A (en) | 1993-03-29 | 1993-03-29 | Signal adapter for semiconductor chip |
| Country | Link |
|---|---|
| JP (1) | JPH06281697A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012022815A (en)* | 2010-07-12 | 2012-02-02 | Enplas Corp | Electric component socket |
| JP2014175119A (en)* | 2013-03-07 | 2014-09-22 | Nec Engineering Ltd | Connector |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012022815A (en)* | 2010-07-12 | 2012-02-02 | Enplas Corp | Electric component socket |
| JP2014175119A (en)* | 2013-03-07 | 2014-09-22 | Nec Engineering Ltd | Connector |
| Publication | Publication Date | Title |
|---|---|---|
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