【０００１】[0001]
【産業上の利用分野】本発明は、高密度多層配線板やモ
ジュール基板の内層回路とブラインドビアホール内に形
成する無電解めっき膜との接着性を向上させる多層配線
板の製法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a multi-layer wiring board which improves the adhesion between an inner layer circuit of a high-density multi-layer wiring board or a module substrate and an electroless plating film formed in a blind via hole.
【０００２】[0002]
【従来の技術】多層配線板やモジュール基板の配線密度
を向上させる方法として、内層回路を形成した基板の表
面に絶縁層及び接着層を形成し、次いでレーザーまたは
溶剤により直径０.３ｍｍ以下のブラインドビアホール
を形成し、無電解めっきまたは無電解めっきと電解めっ
きを併用して回路を形成する際にブラインドビアホール
をめっきして導電化することが行われている。2. Description of the Related Art As a method for improving the wiring density of a multilayer wiring board or a module substrate, an insulating layer and an adhesive layer are formed on the surface of a substrate on which an inner layer circuit is formed, and then a blind with a diameter of 0.3 mm or less is formed by a laser or a solvent. BACKGROUND ART When a via hole is formed and a circuit is formed by electroless plating or a combination of electroless plating and electrolytic plating, a blind via hole is plated to make it conductive.
【０００３】ブラインドビアホールのレーザーによる形
成方法の一例としては、特開昭６２−２１６２９７号公
報がある。しかしこの場合、絶縁層がガラスクロスを含
むと、ガラスクロスの切断が困難なためにブラインドビ
アホールの内壁を高精度に加工することができない。そ
のため、絶縁層はガラスクロスを含まずレーザー光の吸
収波長を持った染料を含む合成樹脂または該合成樹脂と
フィラーによって構成することが特開平１−２０６６９
８号，同３−１６５５９４号公報に開示されている。こ
れらによればブラインドビアホールの内壁を精度よく加
工することができる。As an example of a method for forming a blind via hole with a laser, there is JP-A-62-216297. However, in this case, when the insulating layer includes the glass cloth, the inner wall of the blind via hole cannot be processed with high accuracy because the glass cloth is difficult to cut. Therefore, the insulating layer may be composed of a synthetic resin containing a dye having an absorption wavelength of laser light or a synthetic resin and a filler without containing glass cloth.
No. 8 and No. 3-165594. According to these, the inner wall of the blind via hole can be accurately processed.
【０００４】また、ブラインドビアホールの溶剤による
形成方法の一例としては、特開平４−１４８５９０号公
報の実施例に、絶縁層を光硬化性樹脂で構成し、ブライ
ンドビアホール形成部以外に紫外線を照射して光硬化
し、次いで溶剤によりブラインドビアホール部の未硬化
の樹脂を除去してブラインドビアホールを形成する方法
が開示されている。As an example of a method of forming a blind via hole with a solvent, the insulating layer is made of a photo-curing resin in the embodiment of Japanese Patent Laid-Open No. 148590/1992, and ultraviolet rays are radiated to portions other than the blind via hole forming portion. A method is disclosed in which a blind via hole is formed by photo-curing the resin and then removing the uncured resin in the blind via hole portion with a solvent.
【０００５】上記の方法では、内層回路に銅を用いた場
合、該銅表面に酸化皮膜があると、無電解銅めっき液の
めっき反応電位が内層回路に伝播し、酸化皮膜が還元さ
れて酸化皮膜が消失（ハローイング現象）し、内層回路
と絶縁層との間に隙間が生じ、その隙間にめっき液が侵
入して接着力を低下させると云う問題がある。In the above method, when copper is used for the inner layer circuit, if an oxide film is present on the copper surface, the plating reaction potential of the electroless copper plating solution propagates to the inner layer circuit, and the oxide film is reduced and oxidized. There is a problem that the film disappears (haloing phenomenon), a gap is formed between the inner layer circuit and the insulating layer, and the plating solution enters the gap to reduce the adhesive strength.
【０００６】これを防止する方法としては、本出願人が
先に提案（特開平３−３２５０４１号公報）した技術を
利用することができる。それは、内層回路表面を粗化
し、次に超微粒子状の酸化皮膜を形成する。この状態で
酸化皮膜を還元して、その後に絶縁層を形成する方法で
ある。その後でレーザーや溶剤でブラインドビアホール
を形成すれば、無電解銅めっき時のハローイング現象を
防止することができ、内層回路と絶縁層との接着力を向
上することができる。As a method of preventing this, the technique previously proposed by the present applicant (Japanese Patent Laid-Open No. 3-325041) can be used. It roughens the surface of the inner layer circuit and then forms an oxide film in the form of ultrafine particles. In this state, the oxide film is reduced, and then the insulating layer is formed. If a blind via hole is then formed with a laser or a solvent, the haloing phenomenon at the time of electroless copper plating can be prevented, and the adhesion between the inner layer circuit and the insulating layer can be improved.
【０００７】[0007]
【発明が解決しようとする課題】しかし、前記の方法に
おいても新たな問題があることが分かった。それは、ブ
ラインドビアホール底部に露出した内層回路と、無電解
銅めっき膜との接着力が不十分で接続信頼性が低いこと
である。However, it has been found that there is a new problem in the above method. That is, the adhesion between the inner layer circuit exposed at the bottom of the blind via hole and the electroless copper plating film is insufficient and the connection reliability is low.
【０００８】上記の原因は、内層回路表面にブラインド
ビアホール形成時に絶縁層の残渣樹脂が付着しているこ
とゝ、ブラインドビアホール底部に露出した還元済みの
内層回路面が、再び空気で酸化されることである。The above causes are that the residual resin of the insulating layer adheres to the inner layer circuit surface when the blind via hole is formed, and the reduced inner layer circuit surface exposed at the bottom of the blind via hole is again oxidized by air. Is.
【０００９】上記絶縁層の残渣樹脂は、レーザーでブラ
インドビアホールを形成したときに発生する絶縁層の破
片等がカーボナイズされたものや、溶剤でブラインドビ
アホールを形成したときの現像時の残りかすが主であ
る。また、還元済みの内層回路面が空気で再び酸化され
るのは、レーザーによるブラインドビアホールの形成時
や、その後に行なわれるめっきの前処理までの待ち時間
中や、あるいは、溶剤によるブラインドビアホールの形
成後に行う乾燥工程において生じる。The residual resin of the insulating layer is mainly carbonized from fragments of the insulating layer generated when a blind via hole is formed by a laser, and residuals during development when a blind via hole is formed by a solvent. is there. Also, the reduced inner layer circuit surface is re-oxidized by air when the blind via hole is formed by the laser, during the waiting time before the pretreatment of the plating to be performed thereafter, or when the blind via hole is formed by the solvent. It occurs in a drying process performed later.
【００１０】本発明の目的は、レーザーや溶剤で形成し
たブラインドビアホール底部に露出した内層回路表面と
無電解めっき膜との接着力を高めて接続信頼性を向上し
た多層配線板の製法を提供することにある。An object of the present invention is to provide a method for producing a multilayer wiring board in which the adhesiveness between an electroless plating film and the inner layer circuit surface exposed at the bottom of a blind via hole formed by a laser or a solvent is enhanced to improve connection reliability. Especially.
【００１１】[0011]
【課題を解決するための手段】前記課題を解決する本発
明の要旨は次のとおりである。Means for Solving the Problems The gist of the present invention for solving the above problems is as follows.
【００１２】（１） 内層回路の表面を粗化後、該表面
を酸化して酸化皮膜を形成し、次いで還元処理した後、
絶縁層及び接着層を設け、ブラインドビアホールを形成
し、該接着層の表面に無電解めっきで回路を形成する多
層配線板の製法において、前記ブラインドビアホールの
底部に露出した内層回路の表面に付着している残渣樹脂
と該表面の酸化膜を除去して活性化し、該活性面とブラ
インドビアホール内を無電解めっきを施すことにより配
線回路を形成することを特徴とする多層配線板の製法。(1) After roughening the surface of the inner layer circuit, the surface is oxidized to form an oxide film and then subjected to reduction treatment,
In the method for manufacturing a multilayer wiring board in which an insulating layer and an adhesive layer are provided to form a blind via hole and a circuit is formed on the surface of the adhesive layer by electroless plating, the adhesive layer is attached to the surface of the inner layer circuit exposed at the bottom of the blind via hole. A method for manufacturing a multilayer wiring board, characterized in that the residual resin and the oxide film on the surface are removed and activated, and the wiring surface is formed by electroless plating the active surface and the blind via holes.
【００１３】（２） 前記ブラインドビアホールの底部
に露出した内層回路の表面に付着している残渣樹脂と該
表面の酸化膜を無機酸の水溶液、または該水溶液に過硫
酸アンモニウム塩、塩化第二銅、塩化第二鉄、過酸化水
素水の１種以上を添加した水溶液で処理することにより
除去して活性化し、該活性面とブラインドビアホール内
を無電解めっきを施すことにより配線回路を形成する前
記（１）の多層配線板の製法。(2) The residual resin adhering to the surface of the inner layer circuit exposed at the bottom of the blind via hole and the oxide film on the surface are treated with an aqueous solution of an inorganic acid, or an ammonium persulfate salt, cupric chloride in the aqueous solution. The wiring circuit is formed by treating with an aqueous solution containing at least one of ferric chloride and hydrogen peroxide to remove and activate it, and by electroless plating the active surface and the blind via hole. The manufacturing method of the multilayer wiring board of 1).
【００１４】上記ブラインドビアホール内の残渣樹脂と
ブラインドビアホール形成時に生成した酸化膜は、ブラ
インドビアホールを形成した基板を、単に希硫酸、希塩
酸、希釈王水などの無機酸の水溶液で処理することでの
除去できる。例えば、希硫酸は濃硫酸１０〜５０ｍｌ／
ｌ、希塩酸は３６％塩酸５０〜２００ｍｌ／ｌの２０〜
４０℃に加温した水溶液中に２分以上浸漬することで達
成される。また、上記希釈王水の場合には、王水３０〜
２００ｍｌ／ｌの１０〜４０℃に加温した水溶液中に
０.５〜２分浸漬することで達成される。The residual resin in the blind via hole and the oxide film formed at the time of forming the blind via hole can be obtained by simply treating the substrate on which the blind via hole is formed with an aqueous solution of an inorganic acid such as dilute sulfuric acid, dilute hydrochloric acid or diluted aqua regia. Can be removed. For example, dilute sulfuric acid is concentrated sulfuric acid 10 to 50 ml /
1, diluted hydrochloric acid is 36% hydrochloric acid 50-200 ml / l 20-
It is achieved by immersing in an aqueous solution heated to 40 ° C. for 2 minutes or more. In the case of the diluted aqua regia, aqua regia 30 ~
It can be achieved by immersing in an aqueous solution of 200 ml / l heated to 10 to 40 ° C for 0.5 to 2 minutes.
【００１５】また、ブラインドビアホールの直径が０.
３ｍｍ以下、特に１００μｍ以下とのものでは、前記水
溶液に界面活性剤を添加して該水溶液の表面張力を低下
させたものが、ブラインドビアホール内に該水溶液を十
分浸入させる上で好ましい。なお、上記界面活性剤とし
ては、該水溶液の表面張力を低下させる効果があるもの
であれば特に制限しないが、振動を付加する場合には泡
立ち等のないものが望ましい。こうした点ではフッ化炭
化水素系湿潤剤が優れている。Further, the diameter of the blind via hole is 0.
When the thickness is 3 mm or less, particularly 100 μm or less, it is preferable to add a surfactant to the aqueous solution to reduce the surface tension of the aqueous solution in order to sufficiently infiltrate the aqueous solution into the blind via hole. The surfactant is not particularly limited as long as it has an effect of lowering the surface tension of the aqueous solution, but it is desirable that it does not cause foaming when vibration is applied. The fluorohydrocarbon wetting agent is excellent in this respect.
【００１６】ブラインドビアホール内に露出した内層回
路の表面は、一般に絶縁層の形成時にその破片等が残渣
樹脂となって部分的に付着しているものが多い。これを
除去するには、上記無機酸の水溶液に過硫酸アンモニウ
ム塩、塩化第二銅、塩化第二鉄、過酸化水素水の１種以
上を溶解したものを用いることにより内層回路の溶解度
を高めて処理することができる。即ち、残渣樹脂付着部
の下層にある内層回路が溶解され、その結果、付着して
いた残渣樹脂が剥離されて取り除かれる。On the surface of the inner layer circuit exposed in the blind via hole, in general, fragments and the like are partially adhered as residual resin when the insulating layer is formed. In order to remove this, the solubility of the inner layer circuit can be increased by using one obtained by dissolving one or more of ammonium persulfate, cupric chloride, ferric chloride, and hydrogen peroxide in the aqueous solution of the inorganic acid. Can be processed. That is, the inner layer circuit in the lower layer of the residual resin adhering portion is dissolved, and as a result, the adhering residual resin is peeled off and removed.
【００１７】なお、希硫酸水溶液の場合は過硫酸アンモ
ニウム塩を２０〜２５０ｇ／ｌまたは／および３６％過
酸化水素水１０〜１００ｍｌ／ｌ溶解して用いる。希塩
酸水溶液の場合は、塩化第二銅または塩化第二鉄を１０
ｇ／ｌ以上溶解して用いる。また、前記界面活性剤を添
加するとその効力は増大する。In the case of dilute sulfuric acid aqueous solution, ammonium persulfate is used by dissolving it in an amount of 20 to 250 g / l or / and 10 to 100 ml / l of 36% hydrogen peroxide solution. In the case of dilute hydrochloric acid solution, add 10 parts of cupric chloride or ferric chloride.
g / l or more is dissolved before use. Further, the addition of the above-mentioned surfactant increases its efficacy.
【００１８】次に、上記の各処理を行うに際し、振動を
加える方法がある。その際には、基板を８０〜５００サ
イクル／秒で微振動させるとよい。特に、絶縁層が０.
１ｍｍ以上と厚い場合や、ブラインドビアホールの直径
が１００μｍ以下の場合に有効である。振動によって、
ブラインドビアホール内に付着している気泡等が取り除
かれ、処理液が十分に浸入すると云う効果がある。ま
た、内層回路の溶解により発生するガスの付着を防止す
ることができ、処理液の循環にも効果があり、内層回路
表面をより均一に活性化することができる。Next, there is a method of applying vibration when performing each of the above processes. At that time, the substrate may be slightly vibrated at 80 to 500 cycles / second. In particular, the insulation layer is
This is effective when the thickness is 1 mm or more and the diameter of the blind via hole is 100 μm or less. By vibration,
There is an effect that bubbles and the like adhering to the inside of the blind via hole are removed, and the processing solution is sufficiently infiltrated. In addition, it is possible to prevent the gas generated by the dissolution of the inner layer circuit from adhering, it is effective for the circulation of the treatment liquid, and the surface of the inner layer circuit can be activated more uniformly.
【００１９】また、上記の各処理を行うに先立ちプラズ
マアッシング処理を行って、ブラインドビアホール底部
の内層回路の表面にある絶縁層の残渣を除去してもよ
い。特に、内層回路表面に比較的強固に付着している残
渣樹脂の除去にはプラズマアッシングが効果的である。
プラズマアッシングのガスにはＣＦ4、Ｏ2、Ｎ2の混合
ガスが好ましく、体積比でＣＦ4が１０〜３０％、Ｏ2が
６０〜８０％、Ｎ2が１０〜３０％のものが望ましい。
プラズマアッシングの処理時間は１０〜４０分でよい。
プラズマアッシングで残渣樹脂を除去した後、前記の方
法で内層回路の表面を活性化面することによりめっき膜
との接着性をより向上することができる。Further, the plasma ashing process may be performed prior to the above-mentioned processes to remove the residue of the insulating layer on the surface of the inner layer circuit at the bottom of the blind via hole. Particularly, plasma ashing is effective for removing the residual resin that is relatively strongly attached to the surface of the inner layer circuit.
As a gas for plasma ashing, a mixed gas of CF4 , O2 and N2 is preferable, and a volume ratio of CF4 is 10 to 30%, O2 is 60 to 80%, and N2 is 10 to 30%. .
The processing time for plasma ashing may be 10 to 40 minutes.
After removing the residual resin by plasma ashing, the surface of the inner layer circuit is activated by the method described above, whereby the adhesiveness to the plating film can be further improved.
【００２０】次に、本発明の多層配線板の製造例を図１
に基づき説明する。Next, an example of manufacturing the multilayer wiring board of the present invention is shown in FIG.
It will be explained based on.
【００２１】図１（Ａ）は、両面銅張り積層板１を用
い、エッチングによって内層回路２を形成し、この内層
回路表面を希硫酸と過硫酸アンモニウム塩とからなる水
溶液で処理して粗化し、更に、リン酸三ナトリウムと過
塩素酸ナトリウムを溶解したアルカリ性水溶液で処理し
て粗化面上に超微粒子状の酸化膜を形成し、次いで、ジ
メチルアミンボランを溶解したアルカリ性水溶液で酸化
膜を還元して銅の還元膜３を形成した状態を示す。In FIG. 1A, a double-sided copper-clad laminate 1 is used to form an inner layer circuit 2 by etching, and the surface of the inner layer circuit is roughened by treating it with an aqueous solution of dilute sulfuric acid and ammonium persulfate. Further, it is treated with an alkaline aqueous solution containing trisodium phosphate and sodium perchlorate to form an ultrafine particulate oxide film on the roughened surface, and then the oxide film is reduced with an alkaline aqueous solution containing dimethylamine borane. The state where the copper reduced film 3 is formed is shown.
【００２２】これによって、後述の内層回路２と絶縁層
４との接着力を向上することができる。また、ブライン
ドビアホール６の形成後に行う無電解めっき時の反応電
位が伝播しても、内層回路２と絶縁層４との界面でのハ
ローイングの発生を抑制することができる。As a result, the adhesive force between the inner layer circuit 2 and the insulating layer 4, which will be described later, can be improved. Further, even if the reaction potential is propagated during the electroless plating performed after forming the blind via hole 6, it is possible to suppress the occurrence of haloing at the interface between the inner layer circuit 2 and the insulating layer 4.
【００２３】図１（Ｂ）は、上記（Ａ）で形成した内層
回路１の表面に絶縁層４及び接着層５を形成した状態を
示す。絶縁層４は熱硬化性樹脂のフィルムや、光硬化性
樹脂のフィルムが用いられる。これらはホットロールに
よるラミネート法や、ホットプレスによる圧着法が適用
できる。そして加熱や紫外線照射により絶縁層４を硬化
し、更に接着層５を形成する。接着層５も熱硬化性や光
硬化型の樹脂またはそれらのフィルムを用いることがで
き、加熱や紫外線照射により硬化する。FIG. 1B shows a state in which the insulating layer 4 and the adhesive layer 5 are formed on the surface of the inner layer circuit 1 formed in the above (A). As the insulating layer 4, a thermosetting resin film or a photocurable resin film is used. A laminating method using a hot roll or a pressure bonding method using a hot press can be applied to these. Then, the insulating layer 4 is cured by heating or ultraviolet irradiation, and the adhesive layer 5 is further formed. The adhesive layer 5 can also use a thermosetting or photo-curing resin or a film thereof, and is cured by heating or ultraviolet irradiation.
【００２４】図１（Ｃ）は、上記（Ｂ）で絶縁層４及び
接着層５を形成したものにブラインドビアホール６を形
成した状態を示す。絶縁層４や接着層５が熱硬化性樹脂
の場合は、レーザーによりブラインドビアホール６を形
成することができる。また、絶縁層４と接着層５が光硬
化性樹脂の場合は、ブラインドビアホールの形成部分の
みをマスクで遮蔽して紫外線を露光し、溶剤で現像する
ことによって露光されなかった部分の樹脂が溶解除去さ
れてブラインドビアホール６が形成される。もちろん、
レーザーでブラインドビアホール６を形成することもで
きる。ブラインドビアホール６を形成したとき、露出し
た還元済みの内層回路が空気にさらされて再び酸化され
酸化膜７が形成される。そして、その表面には絶縁層の
残渣樹脂８が残留している。FIG. 1C shows a state in which the blind via hole 6 is formed on the insulating layer 4 and the adhesive layer 5 formed in the above (B). When the insulating layer 4 and the adhesive layer 5 are thermosetting resins, the blind via holes 6 can be formed by laser. When the insulating layer 4 and the adhesive layer 5 are made of a photo-curing resin, only the portion where the blind via hole is formed is shielded with a mask, exposed to ultraviolet rays, and developed with a solvent to dissolve the resin in the unexposed portion. The blind via hole 6 is formed by removing. of course,
It is also possible to form the blind via hole 6 with a laser. When the blind via hole 6 is formed, the exposed reduced inner layer circuit is exposed to air and is oxidized again to form the oxide film 7. The residual resin 8 of the insulating layer remains on the surface.
【００２５】図１（Ｄ）は、上記（Ｃ）で形成した酸化
膜７や残渣樹脂８を取り除いた状態である。これは、前
記水溶液等による処理を行うことによって達成され、内
層回路表面に新たな活性化面９が得られる。FIG. 1D shows a state in which the oxide film 7 and the residual resin 8 formed in the above (C) are removed. This is achieved by performing the treatment with the above-mentioned aqueous solution or the like, and a new activated surface 9 is obtained on the surface of the inner layer circuit.
【００２６】図１（Ｅ）は、無電解めっきのための公知
の処理を行なった状態を示す。即ち、接着層５の表面を
粗化して粗化面１０を形成し、全表面を清浄化後、めっ
き触媒１１の付与とその活性化等の処理を行なった状態
である。FIG. 1E shows a state in which a known process for electroless plating is performed. That is, the surface of the adhesive layer 5 is roughened to form the roughened surface 10, and after the entire surface is cleaned, the plating catalyst 11 is applied and its activation and the like are performed.
【００２７】図１（Ｆ）は、無電解めっきや電解めっき
により最外層回路１２を形成した状態を示す。この時、
ブラインドビアホール内にもめっき膜が形成される。め
っき方法は、無電解銅めっきのみで厚付けを行ってもよ
いし、また、無電解銅めっき膜を薄く形成した上に電解
銅めっきで厚付けしてもよい。なお、これらは公知のエ
ッチング法で配線回路を形成することができる。FIG. 1F shows a state in which the outermost layer circuit 12 is formed by electroless plating or electrolytic plating. At this time,
A plating film is also formed in the blind via hole. As the plating method, thickening may be performed only by electroless copper plating, or thickening may be performed by electrolytic copper plating after forming a thin electroless copper plating film. A wiring circuit can be formed by a known etching method.
【００２８】また、無電解銅めっき膜を薄く形成し、配
線回路形成部以外をめっきレジストで覆い、電解銅めっ
きを施して回路部を厚付けし、めっきレジストを除去し
た後、露出した薄い無電解銅めっき膜をエッチング除去
して回路を形成する、いわゆるセミアディティブ法を適
用することができる。更にまた、接着層５の表面の回路
形成部以外をめっきレジストで覆い、回路形成部のみを
無電解銅めっきで厚付けするフルアディティブ法も適用
できる。Further, the electroless copper plating film is thinly formed, the portions other than the wiring circuit forming portion are covered with a plating resist, electrolytic copper plating is performed to thicken the circuit portion, and the plating resist is removed. A so-called semi-additive method in which the electrolytic copper-plated film is removed by etching to form a circuit can be applied. Furthermore, a full additive method in which the surface of the adhesive layer 5 other than the circuit forming portion is covered with a plating resist and only the circuit forming portion is thickened by electroless copper plating can be applied.
【００２９】なお、本発明は図１で示した工程に限定さ
れるものではなく、例えば、接着剤層を粗化した後にブ
ラインドビアホールを形成してもよい。The present invention is not limited to the process shown in FIG. 1, and for example, the blind via hole may be formed after roughening the adhesive layer.
【００３０】また、前記図１の工程を繰り返すことによ
って、接続信頼性の高い、より多層の多層配線板あるい
は各種モジュール基板を提供することができる。By repeating the process shown in FIG. 1, it is possible to provide a multilayer wiring board or various module boards having higher connection reliability and more layers.
【００３１】[0031]
【作用】本発明において、ブラインドビアホールの内層
回路と無電解めっき膜との接着力が向上し、接続信頼性
が高められる理由は次の作用によるものと考える。In the present invention, the reason why the adhesive force between the inner layer circuit of the blind via hole and the electroless plating film is improved and the connection reliability is enhanced is considered to be as follows.
【００３２】希硫酸、希塩酸、希釈王水などの水溶液、
またはこれらに過硫酸アンモニウム塩、塩化第二銅、塩
化第二鉄、過酸化水素水等を溶解した水溶液で処理する
と、内層回路表面の酸化膜や付着残渣樹脂が取り除かれ
ると同時に、内層回路表面がの極く薄くエッチングされ
て新たな金属面が露出する。その上に、該表面に微細な
凹凸が形成されるために、無電解めっき膜との結合が強
固になるものと推定される。An aqueous solution of diluted sulfuric acid, diluted hydrochloric acid, diluted aqua regia, etc.,
Alternatively, treatment with an aqueous solution in which ammonium persulfate, cupric chloride, ferric chloride, hydrogen peroxide solution, etc. are dissolved removes the oxide film on the surface of the inner layer circuit and the residual resin attached and at the same time Is etched very thinly to expose a new metal surface. It is presumed that since the fine irregularities are formed on the surface, the bond with the electroless plating film is strengthened.
【００３３】例えば、希硫酸水溶液で処理して無電解銅
めっき（膜厚３０μｍ）を行った場合は、そのピール強
度（接着力）は８〜１２ｋｇ／ｃｍで、そのバラツキも
小さい。更に、希塩酸水溶液に塩化第二鉄及び界面活性
剤を添加した水溶液で処理した場合には、そのピール強
度はめっき膜の引張強度（３０ｋｇ／ｃｍ）を超え、め
っき膜が切断して真のピール強度が測定できないほどで
ある。For example, when electroless copper plating (film thickness 30 μm) is performed by treatment with a dilute sulfuric acid aqueous solution, the peel strength (adhesive strength) is 8 to 12 kg / cm, and the variation is small. Furthermore, when treated with an aqueous solution of ferric chloride and a surfactant added to a dilute hydrochloric acid aqueous solution, the peel strength exceeds the tensile strength (30 kg / cm) of the plating film, and the plating film is cut to give a true peeling strength. The strength cannot be measured.
【００３４】これに対して、無処理の内層回路銅表面に
無電解銅めっき（膜厚３０μｍ）を行った場合のピール
強度は２〜１０ｋｇ／ｃｍと低く、そのバラツキも大き
い。On the other hand, the peel strength when electroless copper plating (film thickness 30 μm) is performed on the untreated inner layer circuit copper surface is as low as 2 to 10 kg / cm, and its variation is large.
【００３５】また、プラズマアッシングを施すことによ
り、絶縁層の内層回路表面に付着した残渣樹脂が除去さ
れ、その後に行う内層回路表面の酸化膜の除去が十分に
行われるために、内層回路と無電解めっき膜との接着力
はより向上し、接続信頼性を更に向上することができ
る。Further, by performing the plasma ashing, the residual resin adhered to the surface of the inner layer circuit of the insulating layer is removed, and the oxide film on the surface of the inner layer circuit is sufficiently removed thereafter, so that the inner layer circuit is not removed. The adhesive force with the electrolytic plated film is further improved, and the connection reliability can be further improved.
【００３６】[0036]
【実施例】〔実施例 １〕紫外線不透過タイプで１８μ
ｍ厚の銅箔貼り積層板（日立化成工業社製；ＭＣＬ−６
７Ｎｗ）を用い、所定のエッチングにより内層電源回路
を形成した。該回路の銅箔表面を３０℃の粗化液（硫酸
７ｍｌ／ｌ＋過硫酸アンモニウム塩１８０ｇ／ｌ）で２
分間処理して微細な凹凸を形成した。これを水洗後、７
０℃の酸化膜形成液（リン酸三ナトリウム３５ｇ／ｌ＋
過塩素酸ナトリウム１００ｇ／ｌ＋水酸化ナトリウム１
０ｇ／ｌ）で５分間処理して前記の凹凸面に超微粒子状
の酸化膜を形成し、水洗後、４０℃の還元液（ジメチル
アミンボラン１０ｇ／ｌ＋水酸化ナトリウム７ｇ／ｌ）
で２分間処理して還元した。これを水洗後、窒素ガスを
吹き付けて水切りを行い乾燥した。[Embodiment] [Embodiment 1] Ultraviolet opaque type 18 μm
m-thick copper foil laminated board (Made by Hitachi Chemical Co., Ltd .; MCL-6)
7 Nw) was used to form the inner layer power supply circuit by predetermined etching. The surface of the copper foil of the circuit is treated with a roughening liquid (sulfuric acid 7 ml / l + ammonium persulfate 180 g / l) at 30 ° C.
It was processed for a minute to form fine irregularities. After washing this with water, 7
Oxide film forming solution at 0 ° C (trisodium phosphate 35g / l +
Sodium perchlorate 100g / l + sodium hydroxide 1
0 g / l) for 5 minutes to form an ultra-fine oxide film on the uneven surface, and after washing with water, a reducing solution at 40 ° C. (dimethylamine borane 10 g / l + sodium hydroxide 7 g / l)
And reduced for 2 minutes. This was washed with water, then blown with nitrogen gas to drain water and dried.
【００３７】この内層回路板の両面に、絶縁層として厚
さ７０μｍの光硬化性絶縁フィルム（日立化成工業社
製；ＳＲ−２３００）をラミネートしホットプレスし
た。これに紫外線を２.０Ｊ／ｃｍ2照射した後、１５０
℃で３０分加熱硬化した。A 70 μm thick photo-curable insulating film (manufactured by Hitachi Chemical Co., Ltd .; SR-2300) was laminated as an insulating layer on both sides of this inner layer circuit board and hot pressed. After irradiating this with ultraviolet rays of 2.0 J / cm2 , 150
It was heat-cured at 30 ° C. for 30 minutes.
【００３８】次に、上記絶縁層表面に接着層として厚さ
３０μｍの光硬化性接着フィルム（日立化成工業社製；
ＡＰ−１５３０）をホットロールでラミネートし、紫外
線を１.５Ｊ／ｃｍ2照射後、１５０℃で３０分加熱硬化
した。Next, a photocurable adhesive film having a thickness of 30 μm (manufactured by Hitachi Chemical Co., Ltd.) as an adhesive layer on the surface of the insulating layer.
AP-1530) was laminated with a hot roll, irradiated with ultraviolet rays at 1.5 J / cm2 , and then heat-cured at 150 ° C. for 30 minutes.
【００３９】次に、クロム硫酸混液で接着層表面を粗
化，水洗後、５０℃の湯洗を行い、更に５０℃のアルカ
リ水溶液（水酸化ナトリウム４ｇ／ｌ）で１０分処理
し、接着層表面に付着している粗化残渣物を除去した。
水洗乾燥後、エキシマレーザーで直径２００μｍのブラ
インドビアホールを片面にそれぞれ５０個（両面で１０
０個）形成した試片を作製した。Next, the surface of the adhesive layer is roughened with a mixed solution of chromium and sulfuric acid, washed with water, washed with hot water at 50 ° C., and further treated with an alkaline aqueous solution (sodium hydroxide 4 g / l) at 50 ° C. for 10 minutes to form an adhesive layer. The roughening residue adhering to the surface was removed.
After washing with water and drying, 50 blind via holes with a diameter of 200 μm were formed on each side using an excimer laser (10 on each side).
(0 pieces) formed specimens were produced.
【００４０】上記試片のブラインドビアホール底部に露
出した内層回路表面の残渣樹脂と、酸化膜を除去するた
め、表１に示す処理液を調製した。なお、界面活性剤と
しては、フッ化炭化水素系湿潤剤 ＦＬＵＯＲＡＤ Ｆ
Ｃ−９５（住友３Ｍ社製）を用いた。本実施例では各処
理液での処理は空気攪拌しながら行った。Treatment liquids shown in Table 1 were prepared in order to remove the residual resin and the oxide film on the surface of the inner layer circuit exposed on the bottom of the blind via hole of the above-mentioned sample. As the surfactant, a fluorohydrocarbon-based wetting agent FLUORAD F
C-95 (Sumitomo 3M) was used. In this example, the treatment with each treatment liquid was performed while stirring with air.
【００４１】上記の処理後、ブラインドビアホール底部
の内層回路表面への残渣樹脂の付着の有無を光学顕微鏡
（５００倍）で観測し、残渣樹脂が付着しているブライ
ンドビアホールの数を全ブラインドビアホール数に対す
る比を、残渣残存率（％）で表１に示した。After the above treatment, the presence or absence of the residual resin on the surface of the inner layer circuit at the bottom of the blind via hole was observed with an optical microscope (500 times), and the number of blind via holes to which the residual resin was adhered was determined as the total number of blind via holes. Is shown in Table 1 as a residual residue rate (%).
【００４２】次に、上記処理後の試片を水洗し、更に、
湯洗してブラインドビアホール内に残留している処理液
を十分に洗浄した後、公知の方法でめっき触媒の付与と
活性化を行った。Next, the sample after the above treatment is washed with water, and further,
After washing with hot water to sufficiently wash the treatment liquid remaining in the blind via holes, the plating catalyst was applied and activated by a known method.
【００４３】次に、硫酸銅１０ｇ／ｌ，ＥＤＴＡ３５ｇ
／ｌ，３７％ＨＣＨＯ２.５ｍｌ／ｌ，ポリエチレング
リコール（分子量約６００）２０ｍｌ／ｌ，α,α'−ジ
ピリジル３０ｍｇ／ｌを配合しｐＨ１２.６（at ２０
℃）に調整した７０℃の無電解銅めっき液で、接着層の
全表面及びブラインドビアホール内に厚さ約３０μｍの
銅めっき膜を形成し、水洗後，８０℃で乾燥した。Next, copper sulfate 10 g / l, EDTA 35 g
/ L, 37% HCHO 2.5 ml / l, polyethylene glycol (molecular weight about 600) 20 ml / l, and α, α'-dipyridyl 30 mg / l were added to pH 12.6 (at 20
A copper plating film having a thickness of about 30 μm was formed on the entire surface of the adhesive layer and in the blind via holes with a 70 ° C. electroless copper plating solution adjusted to (° C.), washed with water, and then dried at 80 ° C.
【００４４】これの回路形成部分にエッチングレジスト
を被覆して、回路部以外の銅めっき膜を溶解除去後、該
エッチングレジストを除き最外層回路を形成した。水洗
後、１４０℃で３０分間乾燥し、図１（Ｆ）で示すよう
なブラインドビアホールを有する４層の多層配線板を完
成した。The circuit forming portion was covered with an etching resist, the copper plating film other than the circuit portion was dissolved and removed, and then the etching resist was removed to form an outermost layer circuit. After washing with water and drying at 140 ° C. for 30 minutes, a four-layer multilayer wiring board having blind via holes as shown in FIG. 1 (F) was completed.
【００４５】表１に、ブラインドビアホール内に形成し
た銅めっき膜と内層回路との接着力を示す。該接着力の
測定は、ブラインドビアホール内の銅めっき膜に直径１
３０μｍのニッケル−鉄合金線を挿入して半田で固定
し、５ｍｍ／分の速度で垂直方向に引張り測定した。Table 1 shows the adhesive force between the copper plating film formed in the blind via hole and the inner layer circuit. The adhesive strength was measured by measuring the diameter of the copper plating film in the blind via hole with a diameter of 1
A 30 μm nickel-iron alloy wire was inserted, fixed with solder, and pulled in the vertical direction at a speed of 5 mm / min for measurement.
【００４６】更に、（−６０℃／３０分）⇔（＋１２０
℃／３０分）のヒートサイクル試験を実施し、５０サイ
クル毎にブラインドビアホール部を切断してその断面を
観察し、銅めっき膜と内層回路との接続状態を調べた。
この試験で剥離が１個所でも認められた時までのサイク
ル数を接続信頼性として示した。Further, (-60 ° C / 30 minutes) ⇔ (+120
A heat cycle test (° C / 30 minutes) was performed, the blind via hole portion was cut every 50 cycles, and the cross section was observed to examine the connection state between the copper plating film and the inner layer circuit.
In this test, the connection reliability is represented by the number of cycles until peeling is recognized even at one place.
【００４７】表１から明らかなように、本発明の処理を
施したものは残渣残存率が低い。また、めっき膜と内層
回路との接着力が高く、接続信頼性も優れていた。な
お、希硫酸水溶液または希塩酸水溶液のみで処理した場
合より、該水溶液に前記添加剤や界面活性剤を配合した
水溶液で処理した場合は、更に残渣残存率が低くなり、
接着力や接続信頼性も向上していることが分かる。As is clear from Table 1, those treated with the present invention have a low residual residue rate. Further, the adhesion between the plated film and the inner layer circuit was high, and the connection reliability was excellent. In addition, the residual residue rate becomes lower when treated with an aqueous solution containing the additive or the surfactant in the aqueous solution than when treated with only the diluted sulfuric acid aqueous solution or the diluted hydrochloric acid aqueous solution.
It can be seen that the adhesive strength and connection reliability are also improved.
【００４８】[0048]
【表１】[Table 1]
【００４９】〔実施例 ２〕ブラインドビアホール底部
の内層回路表面の残渣樹脂の除去効率を見るため、処理
液は実施例１と同じものを用い、これに振動を組合せ
た。振動機としては、ＶＩＢＬＥＸ ＰＳ−２（ＰＬＡ
ＮＴＥＸ社製）を用いた。その結果を表２に示す。[Example 2] In order to check the removal efficiency of the residual resin on the surface of the inner layer circuit at the bottom of the blind via hole, the same treatment liquid as in Example 1 was used, and this was combined with vibration. As a vibrator, VIBLEX PS-2 (PLA
NTEX) was used. The results are shown in Table 2.
【００５０】めっき膜と内層回路との接着力や接続信頼
性は実施例１とそれほど差はないが、振動を加えること
により樹脂の残渣残存率が０％と優れた除去効率を示す
ことが分かった。Although the adhesive strength and connection reliability between the plating film and the inner layer circuit are not so different from those in Example 1, it was found that the residual residue rate of the resin was 0% and excellent removal efficiency was obtained by applying vibration. It was
【００５１】[0051]
【表２】[Table 2]
【００５２】〔実施例 ３〕実施例１と同じ条件で内層
回路板を作製した。この内層回路板の両面に絶縁層とし
て厚さ８０μｍの光硬化性絶縁フィルム（日立化成社
製；ＳＡ−７０７０）をホットロールでラミネートし
た。次に、直径６０μｍのブラインドビアホールを形成
する部分のみを光遮蔽できるマスクを設けてその上から
紫外線を２.５Ｊ／ｃｍ2照射し、硬化した。更に、１,
１,１−トリクロロエタンを用いて現像し、ブラインド
ビアホールを形成した試片を作製した。Example 3 An inner layer circuit board was manufactured under the same conditions as in Example 1. An 80 [mu] m-thick photocurable insulating film (manufactured by Hitachi Chemical Co., Ltd .; SA-7070) as an insulating layer was laminated on both surfaces of this inner layer circuit board with hot rolls. Next, a mask that can shield light only in the portion where a blind via hole having a diameter of 60 μm is provided was irradiated with ultraviolet rays at 2.5 J / cm2 and cured. Furthermore, 1,
It was developed using 1,1-trichloroethane to prepare a test piece in which a blind via hole was formed.
【００５３】次に、ＣＦ4：２０％，Ｏ2：７０％，
Ｎ2：１０％の混合ガス内で２０分プラズマアッシング
処理を行なった後、絶縁層表面をクロム硫酸混液で粗化
した。水洗，湯洗してブラインドビアホール内の残留ク
ロム硫酸混液を除去した。Next, CF4 : 20%, O2 : 70%,
After plasma ashing treatment was performed for 20 minutes in a mixed gas of N2 : 10%, the surface of the insulating layer was roughened with a mixed solution of chromium and sulfuric acid. It was washed with water and hot water to remove the residual chromium-sulfuric acid mixture in the blind via hole.
【００５４】ブラインドビアホール底部の露出内層回路
の表面の残渣樹脂（現像残り）を実施例１と同様にして
観察した。The residual resin (development residue) on the surface of the exposed inner layer circuit at the bottom of the blind via hole was observed in the same manner as in Example 1.
【００５５】また、上記試片を公知の手法でめっき触媒
の付与と活性化を行い、水洗後Ｎ2ガスで水分を吹き飛
ばし、直ちに厚さ３５μｍのめっきレジストフィルム
（日立化成社製；ＳＲ−３２００）をラミネートし、マ
スクを介して回路形成部以外に紫外線を０.２５Ｊ／ｃ
ｍ2照射した。次いで、１,１,１−トリクロロエタンで
現像して回路形成部のめっきレジストフィルムを除去し
た。Further, a plating catalyst was applied and activated by a known method on the above test piece, and after washing with water, water was blown off with N2 gas, and immediately a plating resist film having a thickness of 35 μm (manufactured by Hitachi Chemical Co., Ltd .; SR-3200) was used. ) Is laminated, and ultraviolet rays are applied to the area other than the circuit forming portion through a mask at 0.25 J / c.
m2 irradiation. Then, it was developed with 1,1,1-trichloroethane to remove the plating resist film in the circuit forming portion.
【００５６】次に、実施例１と同様に無電解銅めっきを
行い、回路形成部分とブラインドビアホール内にめっき
膜を形成し、４層の多層配線板を作製した。Next, electroless copper plating was carried out in the same manner as in Example 1 to form a plating film in the circuit forming portion and the blind via hole, to produce a four-layer multilayer wiring board.
【００５７】上記多層配線板の接続信頼性を１０００サ
イクル実施した。その結果を表３に示す。ブラズマアッ
シングを施した場合は、残渣残存率は０％で、めっき膜
と内層回路との接続信頼性は１０００サイクル後でも異
常は認めらなかった。The connection reliability of the above multilayer wiring board was carried out for 1000 cycles. The results are shown in Table 3. When the plasma ashing was performed, the residual residue rate was 0%, and no abnormality was found in the connection reliability between the plating film and the inner layer circuit even after 1000 cycles.
【００５８】本実施例によれば、回路幅を８０μｍと
し、この回路中に直径５０μｍのブラインドビアホール
を形成することが可能である。According to this embodiment, it is possible to form a blind via hole having a circuit width of 80 μm and a diameter of 50 μm in this circuit.
【００５９】[0059]
【表３】[Table 3]
【００６０】[0060]
【発明の効果】本発明によれば、ブラインドビアホール
の内層回路と配線回路との接続信頼性が向上し、ブライ
ンドビアホールの直径が１００μｍ以下のものを提供で
きる。従って、配線の回路幅及びその間隔も共に１００
μｍ以下とすることができ高密度実装が可能な多層配線
板を提供できる。According to the present invention, the connection reliability between the inner layer circuit of the blind via hole and the wiring circuit is improved, and the blind via hole having a diameter of 100 μm or less can be provided. Therefore, the circuit width of the wiring and its interval are both 100
It is possible to provide a multi-layer wiring board which can have a thickness of μm or less and which enables high-density mounting.
【００６１】また、内層にランドのない回路を形成する
ことも可能であり、最外層も部品を接続するランド以外
にランドのない回路も同様に形成することができる。It is also possible to form a circuit having no land in the inner layer, and a circuit having no land in the outermost layer can be similarly formed in addition to the land connecting the components.
【図１】本発明の多層配線板の製造工程に示す模式断面
図である。FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a multilayer wiring board of the present invention.
１…積層板、２…内層回路、３…還元膜、４…絶縁層、
５…接着層、６…ブラインドビアホール、７…酸化膜、
８…残渣樹脂、９…活性化面、１０…粗化面、１１…め
っき触媒、１２…最外層回路。1 ... Laminated board, 2 ... Inner layer circuit, 3 ... Reduction film, 4 ... Insulating layer,
5 ... Adhesive layer, 6 ... Blind via hole, 7 ... Oxide film,
8 ... Residual resin, 9 ... Activated surface, 10 ... Roughened surface, 11 ... Plating catalyst, 12 ... Outermost layer circuit.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5042535AJP2790956B2 (en) | 1993-03-03 | 1993-03-03 | Manufacturing method of multilayer wiring board |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5042535AJP2790956B2 (en) | 1993-03-03 | 1993-03-03 | Manufacturing method of multilayer wiring board |
| Publication Number | Publication Date |
|---|---|
| JPH06260766Atrue JPH06260766A (en) | 1994-09-16 |
| JP2790956B2 JP2790956B2 (en) | 1998-08-27 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5042535AExpired - Fee RelatedJP2790956B2 (en) | 1993-03-03 | 1993-03-03 | Manufacturing method of multilayer wiring board |
| Country | Link |
|---|---|
| JP (1) | JP2790956B2 (en) |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |