【０００１】[0001]
【産業上の利用分野】本発明は、ＩＶ族半導体単結晶基
板上に形成された高品質なＩＩＩ−Ｖ族化合物半導体単
結晶層を有する金属膜／ＩＩＩ−Ｖ族化合物半導体積層
構造およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal film / group III-V compound semiconductor laminated structure having a high-quality group III-V compound semiconductor single crystal layer formed on a group IV semiconductor single crystal substrate, and manufacturing thereof. Regarding the method.
【０００２】[0002]
【従来の技術】現在、Ｓｉに代表されるＩＶ族半導体単
結晶基板上にＧａＡｓに代表されるＩＩＩ−Ｖ族化合物
半導体単結晶薄膜を形成する試みが活発に行われてい
る。これは、このような薄膜構造が形成できると、ＩＩ
Ｉ−Ｖ族化合物半導体高機能素子を安価なＳｉ基板上に
作製でき、またＳｉの高い熱伝導率によって光素子等の
性能向上が期待できるためである。さらにＳｉ基板上に
選択的にＩＩＩ−Ｖ族化合物単結晶薄膜を形成できれ
ば、Ｓｉ超高集積回路とＩＩＩ−Ｖ族化合物半導体超高
速素子や光素子を同一基板上に形成できるため、新しい
高機能素子の開発が予測されるからである。2. Description of the Related Art At present, active attempts are being made to form a group III-V compound semiconductor single crystal thin film represented by GaAs on a group IV semiconductor single crystal substrate represented by Si. This means that when such a thin film structure can be formed, II
This is because a high-performance I-V compound semiconductor device can be produced on an inexpensive Si substrate, and the high thermal conductivity of Si can be expected to improve the performance of optical devices and the like. Furthermore, if the III-V compound single crystal thin film can be selectively formed on the Si substrate, the Si ultra-high integrated circuit and the III-V compound semiconductor ultra-high-speed device or optical device can be formed on the same substrate. This is because the development of the device is predicted.
【０００３】しかしながら、ＩＩＩ−Ｖ族化合物半導体
結晶はＩＩＩ族とＶ族の２種類の元素から成る有極性結
晶であるのに対し、ＩＶ族半導体単結晶基板は単一元素
から成る無極性結晶である。従って、通常用いられる
（１００）面方位を有するＩＶ族半導体単結晶基板上に
ＩＩＩ−Ｖ族化合物半導体単結晶薄膜をエピタキシャル
成長させようとする場合、ＩＩＩ族とＶ族の配列の位相
がずれ、極性が反転した領域、いわゆるアンチ・フェイ
ズ・ドメインができやすく、全基板面内でＩＩＩ族とＶ
族の配列の位相がそろったいわゆるシングル・ドメイン
単結晶薄膜を確実に得ることは最近までは困難であっ
た。However, the group III-V compound semiconductor crystal is a polar crystal composed of two kinds of elements of group III and group V, whereas the group IV semiconductor single crystal substrate is a nonpolar crystal composed of a single element. is there. Therefore, when a group III-V compound semiconductor single crystal thin film is epitaxially grown on a group IV semiconductor single crystal substrate having a (100) plane orientation that is usually used, the phases of the groups III and V are out of phase and the polarities are different. It is easy to form a so-called anti-phase domain, which is a region in which the group is inverted.
Until recently, it has been difficult to reliably obtain a so-called single-domain single-crystal thin film in which the phases of the groups are aligned.
【０００４】この問題を解決するために考えられたのが
雑誌「ジャパニーズ・ジャーナル・オブ・アプライド・
フィジクス（Jpn.J.Appl.Phys.）」第２４巻第６号（１
９８５年）の第Ｌ３９１−３９３頁に説明されている
「二段階成長法」と呼ばれる方法である。すなわち、Ｓ
ｉ単結晶基板の温度を４５０℃以下の低温としてまず２
０ｎｍ程度の微細な多結晶もしくは非晶質状のＧａＡｓ
バッファ層を堆積した後、Ｓｉ単結晶基板の温度を通常
の成長温度、上記文献の場合は６００℃としてＧａＡｓ
単結晶薄膜を成長させる方法である。この方法によって
シングル・ドメイン単結晶薄膜を確実に得ることができ
るようになった。微細な多結晶もしくは非晶質状のＧａ
Ａｓ薄膜は温度を６００℃に昇温する間にアニールされ
て単結晶化する。上記文献の結果はＭＯＣＶＤ法による
ものであったが、以後ＭＢＥ法でも同様に二段階成長法
が有効であることが確認された。To solve this problem, the magazine "Japanese Journal of Applied."
Physics (Jpn.J.Appl.Phys.) "Vol. 24, No. 6 (1
985), page L391-393, referred to as the "two-step growth method". That is, S
First, set the temperature of the i single crystal substrate to a low temperature of 450 ° C or lower
Fine polycrystalline or amorphous GaAs of about 0 nm
After depositing the buffer layer, the temperature of the Si single crystal substrate is set to a normal growth temperature, 600 ° C. in the case of the above document, and GaAs
This is a method of growing a single crystal thin film. By this method, a single domain single crystal thin film can be surely obtained. Fine polycrystalline or amorphous Ga
The As thin film is annealed while raising the temperature to 600 ° C. to be single crystallized. Although the results of the above-mentioned documents were based on the MOCVD method, it was confirmed that the two-step growth method is also effective for the MBE method thereafter.
【０００５】ところで半導体薄膜の素子応用の観点から
はシングル・ドメイン化とともに結晶品質の向上が重要
である。しかし、通常Ｓｉ基板上にＧａＡｓなどのＩＩ
Ｉ−Ｖ族化合物半導体を成長すると、ＳｉとＧａＡｓの
界面には基板と成長層との格子不整合から予想されるよ
りはるかに多くの転位や積層欠陥が発生し、さらにその
一部は容易に上層まで伸びて貫通転位となる。二段階成
長法で成長したＧａＡｓ層の転位密度は数ｎｍ厚の成長
表面で約１０8ｃｍ-2達する。そこで導入されたのが歪
超格子中間層や熱サイクルアニール法で、これらによっ
て約１０6ｃｍ-2まで転位密度は急速に改善された（雑
誌「アプライド・フィジクス・レター（Appl. Phys.Let
t.）」第５４巻第１号（１９８９年）の第２４−２６
頁）。From the viewpoint of device application of semiconductor thin films, it is important to improve the crystal quality as well as single domain. However, on a Si substrate, II such as GaAs is usually used.
When a group IV compound semiconductor is grown, much more dislocations and stacking faults are generated at the interface between Si and GaAs than expected due to the lattice mismatch between the substrate and the growth layer. It extends to the upper layer and becomes threading dislocation. The dislocation density of the GaAs layer grown by the two-step growth method reaches about 108 cm-2 on the growth surface having a thickness of several nm. The strain superlattice intermediate layer and the thermal cycle annealing method were introduced there, and the dislocation density was rapidly improved to about 106 cm-2 by these methods (Journal "Appl. Phys. Let.
t.) ", Vol. 54, No. 1 (1989), 24-26.
page).
【０００６】[0006]
【発明が解決しようとする課題】Ｓｉ基板上に良質のＩ
ＩＩ−Ｖ族化合物半導体薄膜を得るために採用された上
記従来構造の問題点を考えてみる。[Problems to be Solved by the Invention]
Consider the problems of the above-mentioned conventional structure adopted to obtain a II-V group compound semiconductor thin film.
【０００７】歪超格子中間層の挿入や熱リサイクルアニ
ールによる方法では、約１０6ｃｍ-2の転位密度を大き
な壁としてその後は進展が見られない状態にある。この
原因としてＳｉ基板とＩＩＩ−Ｖ族化合物半導体との熱
膨張係数差の問題が最近指摘された（雑誌「アプライド
・フィジクス・レター（Appl. Phys.Lett.）」第５６巻
第２２号（１９９０年）の第２２２５−２２２７頁）。
即ち熱サイクルアニールの導入などによって成長温度
（６５０℃）においては１０5ｃｍ-2以下まで転位密度
は減少しているが、成長後の冷却中（４５０℃程度以
下）に熱膨張係数差によるストレスによって１０6ｃｍ
-2台の転位が導入されるというものである。これはＳｉ
基板との界面付近に多数残留する転位が熱歪によって上
昇してくるためと考えられている。成長中に上昇してく
る転位に対しては、これを横方向に曲げて上層部への到
達を防ぐ目的で一般に歪格子中間層にが挿入され、大き
な効果を上げている。しかし熱歪によって上昇してくる
転位に対しては、歪格子中間層の挿入効果が十分に得ら
れないという問題があった。In the method of inserting the strained superlattice intermediate layer and the thermal recycling annealing, the dislocation density of about 106 cm-2 is used as a large wall and no further progress is observed thereafter. As a cause of this, a problem of a difference in thermal expansion coefficient between a Si substrate and a III-V group compound semiconductor has recently been pointed out (Magazine "Appl. Phys. Lett.", Vol. 56, No. 22 (1990). 2225-2227).
That is, the dislocation density decreases to 105 cm-2 or less at the growth temperature (650 ° C.) due to the introduction of thermal cycle annealing, but stress due to the difference in thermal expansion coefficient during cooling after growth (about 450 ° C.). By 106 cm
-Two dislocations are introduced. This is Si
It is considered that many dislocations remaining near the interface with the substrate rise due to thermal strain. With respect to dislocations that rise during growth, dislocations are generally inserted in the strained lattice intermediate layer in order to prevent the dislocations from reaching the upper layer portion by bending them in the lateral direction, and a great effect is obtained. However, there is a problem that the effect of inserting the strained lattice intermediate layer cannot be sufficiently obtained with respect to dislocations that rise due to thermal strain.
【０００８】本発明の目的はこのような従来技術の欠点
を克服し、ＩＶ族半導体単結晶基板上に高品質なＩＩＩ
−Ｖ族単半導体単結晶層を有する金属膜／ＩＩＩ−Ｖ族
化合物半導体積層構造を提供することにある。The object of the present invention is to overcome such drawbacks of the prior art and to provide a high quality III-group semiconductor on a group IV semiconductor single crystal substrate.
A metal film / group III-V compound semiconductor laminated structure having a group-V single semiconductor single crystal layer is provided.
【０００９】[0009]
【課題を解決するための手段】本発明によれば、ＩＶ族
単結晶基板上に金属膜およびＩＩＩ−Ｖ族化合物半導体
単結晶薄膜が交互に積層されていることを基本とする構
造において、デバイス活性層として利用するＩＩＩ−Ｖ
族化合物半導体層より下方に少なくとも１層以上の金属
膜層が積層されていることを特徴とする元素半導体基板
上の金属膜／化合物半導体積層構造が得られる。さらに
前記金属膜層が特に金属Ｉｎ層であることを特徴とする
元素半導体基板上の金属膜／化合物半導体積層構造が得
られる。According to the present invention, there is provided a device having a structure in which a metal film and a III-V compound semiconductor single crystal thin film are alternately laminated on a group IV single crystal substrate. III-V used as active layer
A metal film / compound semiconductor laminated structure on an elemental semiconductor substrate is obtained in which at least one metal film layer is laminated below the group compound semiconductor layer. Further, a metal film / compound semiconductor laminated structure on an elemental semiconductor substrate is obtained, wherein the metal film layer is a metal In layer.
【００１０】また本発明によれば、ＩＶ族単結晶基板上
の一部分に直接、またはＧａ若しくはＡｌ系ＩＩＩ−Ｖ
族化合物半導体バッファ層を挟んでＩｎ系ＩＩＩ−Ｖ族
化合物半導体単結晶層を選択成長する工程と、さらにそ
の上にＧａまたはＡｌ系ＩＩＩ−Ｖ族化合物半導体層を
選択成長する工程と、以上の工程で得られたメサ状選択
成長層の側部ファセット面に露出した前記Ｉｎ系ＩＩＩ
−Ｖ族化合物半導体単結晶層断面部分からＶ族元素を熱
敵に蒸発させることで前記Ｉｎ系ＩＩＩ−Ｖ族化合物半
導体単結晶層を金属Ｉｎ層に変換する工程を少なくとも
含むことを特徴とする元素半導体基板上の金属膜／化合
物半導体積層構造の製造方法が得られる。さらに前記Ｉ
ｎ系ＩＩＩ−Ｖ族化合物半導体単結晶層が特にＩｎＰ単
結晶層であることを特徴とする元素半導体基板上の金属
膜／化合物半導体積層構造の製造方法が得られる。Further, according to the present invention, directly on a part of the group IV single crystal substrate, or Ga or Al type III-V.
A step of selectively growing an In-based III-V group compound semiconductor single crystal layer sandwiching a group-group compound semiconductor buffer layer, and a step of selectively growing a Ga or Al-based III-V group compound semiconductor layer thereon. The In-based III exposed on the side facets of the mesa-like selective growth layer obtained in the step
At least a step of converting the In-based III-V compound semiconductor single crystal layer into a metal In layer by thermally evaporating a Group V element from the cross-section of the group-V compound semiconductor single crystal layer. A method of manufacturing a metal film / compound semiconductor laminated structure on an elemental semiconductor substrate is obtained. Furthermore, I
A method for producing a metal film / compound semiconductor laminated structure on an elemental semiconductor substrate, wherein the n-type III-V group compound semiconductor single crystal layer is particularly an InP single crystal layer.
【００１１】[0011]
【作 用】Ｓｉ基板とＩＩＩ−Ｖ族化合物半導体との熱
膨張係数差による熱歪みの発生を避けるには、これを容
易に緩和できる様な十分に柔らかい物質を中間層として
挿入すればよい。例えば金属、中でも金属Ｉｎは弾性率
が小さく、さらに融点が約１５７℃と非常に低いため理
想的である。高温での結晶成長中、さらに成長後の冷却
時も融点付近まで液状の金属Ｉｎ中間層によって熱歪を
ほぼ１００％吸収できる。[Operation] In order to avoid the occurrence of thermal strain due to the difference in thermal expansion coefficient between the Si substrate and the III-V group compound semiconductor, a sufficiently soft substance capable of easily relaxing this can be inserted as an intermediate layer. For example, metals, especially metal In, are ideal because they have a low elastic modulus and a melting point of about 157 ° C. which is extremely low. Almost 100% of thermal strain can be absorbed by the liquid metal In intermediate layer up to near the melting point during crystal growth at high temperature and during cooling after growth.
【００１２】次に金属Ｉｎ中間層の形成方法であるが、
少なくとも液状の金属Ｉｎ層上に後から目的のＩＩＩ−
Ｖ族化合物半導体単結晶層を成長することは原理的に不
可能である。ところでＩｎＰやＩｎＡｓなどＩｎ系結晶
では、表面からのＰやＡｓの脱離が極めて容易に起こ
る。中でもＩｎＰ表面からのＰの脱離では、例えばＧａ
Ａｓ表面からのＡｓの脱離に比べてその脱離速度定数が
２〜３桁も大きい。そのためＩｎＰ結晶の成長時にはＰ
の脱離を防止するため通常大きなＶ族／ＩＩＩ族原料ガ
ス供給比が必要となる。この点を考慮することで本発明
の製造方法が得られた。即ち、例えばＩｎＰ単結晶層を
挟んで例えばＧａＡｓ単結晶層をまず成長する。この
時、例えば熱サイクルアニールを行い、またＧａ系の歪
み超格子層を導入すれば成長温度での転位密度は十分減
らすことができる。その後にＩｎＰ表面からのＰの脱離
は十分大きく、しかしＧａＡｓ表面からのＡｓの脱離は
十分小さい温度に設定してＶ族原料ガスの供給を停止す
る。この時ＩｎＰ単結晶層の一部を露出しておければ、
そこからＰは脱離するためＩｎＰ単結晶層を金属Ｉｎ層
に変換することができる。例えばメサ形状を有する選択
成長層を形成すればその側部ファセット面にＩｎＰ単結
晶層の断面部分を露出することができる。金属Ｉｎ層に
変換後冷却すれば、融点付近までは液状の金属Ｉｎ層が
熱歪をほぼ１００％吸収し、新たな転位の上昇も起こら
ない。Next, regarding the method of forming the metal In intermediate layer,
At least on the liquid metal In layer, the target III-
In principle, it is impossible to grow a group V compound semiconductor single crystal layer. Incidentally, in In-based crystals such as InP and InAs, desorption of P and As from the surface occurs extremely easily. In particular, when desorbing P from the InP surface, for example, Ga
The desorption rate constant is as much as two to three orders of magnitude higher than the desorption of As from the As surface. Therefore, when growing an InP crystal, P
A large group V / group III source gas supply ratio is usually required in order to prevent desorption. Taking this point into consideration, the manufacturing method of the present invention was obtained. That is, for example, a GaAs single crystal layer is first grown with an InP single crystal layer interposed therebetween. At this time, if thermal cycle annealing is performed and a Ga-based strained superlattice layer is introduced, the dislocation density at the growth temperature can be sufficiently reduced. After that, the desorption of P from the InP surface is sufficiently large, but the desorption of As from the GaAs surface is set to a sufficiently small temperature, and the supply of the group V source gas is stopped. At this time, if a part of the InP single crystal layer is exposed,
Since P is desorbed from there, the InP single crystal layer can be converted into a metal In layer. For example, if a selective growth layer having a mesa shape is formed, the cross-sectional portion of the InP single crystal layer can be exposed on the side facet surface thereof. If it is cooled after being converted into the metal In layer, the liquid metal In layer absorbs almost 100% of the thermal strain up to the vicinity of the melting point, and no new dislocation rises.
【００１３】[0013]
【実施例】以下、本発明の実施例について図面を参照し
て詳細に説明する。図１（ａ）〜（ｅ）には本発明の一
例としての構造を得るための一例としての製造工程を各
段階における断面図で示した。Embodiments of the present invention will now be described in detail with reference to the drawings. 1A to 1E are cross-sectional views showing an example manufacturing process for obtaining a structure as an example of the present invention.
【００１４】図１（ａ）に示すようにまずＳｉ（１０
０）２゜ｏｆｆ基板１の全表面に厚さ２００ｎｍのＳｉ
Ｏ2膜２を形成後、Ｓｉ基板１まで貫通する［０１１］
方向の例えば巾８ｕｍのストライプ状の開口部を設け
る。As shown in FIG. 1A, first, Si (10
0) Si of 200 nm thickness on the entire surface of 2 ° off substrate 1
After forming the O2 film 2, penetrates to the Si substrate 1 [011]
For example, a striped opening having a width of 8 μm is provided.
【００１５】次に、図１（ｂ）に示すようにＳｉ基板１
に貫通する開口部に例えば１ｕｍ厚の第一のＧａＡｓ選
択成長層３を通常の二段階成長法で形成し、さらに例え
ば１ｕｍ厚のＩｎＰ選択成長層４を形成する。この時、
成長条件を選べばストライプに沿った成長側面（１１
１）Ｂファセット面で終端することができ、ファセット
面上での成長速度を０にすることができる。即ち選択成
長層の側面には成長断面構造がそのまま露出される。Ｇ
ａＡｓの成長には例えばＩＩＩ族有機金属原料としてジ
エチルガリウムクロライド（ＤＥＧａＣｌ）、Ｖ族原料
としてはアルシン（ＡｓＨ3）を用いたＭＯＣＶＤ法を
用いることができる。またＩｎＰの成長には例えばジメ
チルインジウムクロライド（ＤＭＩｎＣｌ）と例えばホ
スフィン（ＰＨ3）を用いることができる。この方法は
以下でＧａＡｓ、ＩｎＧａＡｓ等を選択成長する場合に
も適用することができる。Next, as shown in FIG. 1B, the Si substrate 1
A first GaAs selective growth layer 3 having a thickness of, for example, 1 μm is formed by an ordinary two-step growth method in an opening penetrating the substrate, and an InP selective growth layer 4 having a thickness of, for example, 1 μm is further formed. At this time,
If the growth conditions are chosen, the growth side along the stripe (11
1) It can be terminated at the B facet plane, and the growth rate on the facet plane can be made zero. That is, the growth cross-section structure is exposed as it is on the side surface of the selective growth layer. G
For the growth of aAs, for example, a MOCVD method using diethylgallium chloride (DEGaCl) as a group III organic metal raw material and arsine (AsH3 ) as a group V raw material can be used. Further, for growing InP, for example, dimethylindium chloride (DMInCl) and, for example, phosphine (PH3 ) can be used. This method can also be applied to the case of selectively growing GaAs, InGaAs or the like below.
【００１６】次に図１（ｃ）に示すように例えば１ｕｍ
厚の第二のＧａＡｓ選択成長層５を、途中９００℃〜４
５０℃の熱サイクルアニールを２回ほど行いながら形成
する。Next, as shown in FIG. 1C, for example, 1 um
The thick second GaAs selective growth layer 5 is formed at 900 ° C. to 4
It is formed by performing thermal cycle annealing at 50 ° C. twice.
【００１７】次に図１（ｄ）に示すようにＩｎＧａＡｓ
／ＧａＡｓ歪超格子層６（Ｉｎ0.2Ｇａ0.8Ａｓ：１０
ｎｍ，ＧａＡｓ：２０ｎｍ，X１０周期）を形成し、さ
らに例えば１ｕｍ厚の第三のＧａＡｓ選択成長層７を形
成する。Next, as shown in FIG. 1D, InGaAs
/ GaAs strained superlattice layer 6 (In0.2 Ga0.8 As: 10
nm, GaAs: 20 nm,X 10 cycles), and further a third GaAs selective growth layer 7 having a thickness of, for example, 1 μm is formed.
【００１８】最後に、図１（ｅ）に示すように６００℃
以下、４５０℃以上の適当な基板温度でＶ族原料ガスの
供給を一定時間停止し、ＩｎＰ選択成長層４の断面露出
部分からＰを蒸発させてＩｎＰ選択成長層４を金属Ｉｎ
層８に変換する。Ｖ族原料ガスの供給を停止している間
は第三のＧａＡｓ選択成長層７の表面からも多少Ａｓが
抜けるので、あまり高すぎない適当な基板温度を選ぶ。Finally, as shown in FIG. 1 (e), 600 ° C.
After that, the supply of the group V source gas is stopped for a certain period of time at an appropriate substrate temperature of 450 ° C. or higher, and P is evaporated from the exposed cross-section of the InP selective growth layer 4 so that the InP selective growth layer 4 is made of metal In.
Convert to layer 8. While the supply of the group V source gas is stopped, some As escapes from the surface of the third GaAs selective growth layer 7, so an appropriate substrate temperature that is not too high is selected.
【００１９】得られたＧａＡｓ層の結晶品質を調べるた
め行ったホトルミネッセンス（ＰＬ）測定からはＧａＡ
ｓ基板成長層と遜色のない発光強度が得られ、また発光
波長のシフトもなく歪みは完全に緩和されていることが
分かった。またＴＥＭ観察の結果、転位密度も多くて１
０3〜１０4ｃｍ-2と極めて良好な結晶品質が得られて
いることが分かった。From the photoluminescence (PL) measurement performed to investigate the crystal quality of the obtained GaAs layer, GaA
It was found that an emission intensity comparable to that of the s substrate growth layer was obtained, and the strain was completely relaxed without any shift in the emission wavelength. Also, as a result of TEM observation, the dislocation density is high, which is 1
It was found that extremely good crystal quality of 03 to 104 cm-2 was obtained.
【００２０】以上の実施例では絶縁膜としてＳｉＯ2膜
を用いたが、これ以外の例えばＡｌＮやＳｉ3Ｎ4など
の非晶質膜を用いても良い。また絶縁膜の代わりに（１
１１）ファセット面を有するＶ字型の溝を化学エッヂン
グで形成しておけばその上には成長しないので、マスク
として用いることができる。Although the SiO2 film is used as the insulating film in the above embodiments, an amorphous film other than this, such as AlN or Si3 N4 , may be used. Instead of the insulating film (1
11) If a V-shaped groove having a facet surface is formed by chemical edging, it will not grow on it and can be used as a mask.
【００２１】また実施例ではＧａＡｓ選択成長法として
塩素系原料であるＤＥＧａＣｌを用いたＭＯＣＶＤを用
いた。これは塩素系原料を用いた方が通常のトリメチル
ガリウム（ＴＭＧ）を用いた場合より選択性が良いため
である。同様の理由から選択成長にハロゲン輸送法も適
している。また真空中で成長を行う有機金属分子線エピ
タキシャル成長法（ＭＯＭＢＥ法）などを適用すること
もできる。In the example, MOCVD using DEGaCl, which is a chlorine-based material, was used as the GaAs selective growth method. This is because the use of a chlorine-based material has better selectivity than the case of using normal trimethylgallium (TMG). For the same reason, the halogen transport method is also suitable for selective growth. Further, a metalorganic molecular beam epitaxial growth method (MOMBE method) or the like, which grows in a vacuum, can also be applied.
【００２２】また真空中で分子線を照射して成長を行う
場合には、例えば適当なマスクを用いて側壁がほぼ垂
直、あるいは逆メサ状のＳｉストライプメサをドライエ
ッチングで形成しておき、マスクを除去した後に成長を
行っても良い。分子線の異方性によってＳｉメサの側壁
には成長しないためメサ上に同様の構造が成長できる。When growing by irradiating a molecular beam in a vacuum, for example, an appropriate mask is used to form Si stripe mesas having substantially vertical sidewalls or inverted mesas by dry etching. Growth may be performed after removing the. Due to the anisotropy of the molecular beam, it does not grow on the side wall of the Si mesa, so that a similar structure can grow on the mesa.
【００２３】また実施例では成長領域が［０１１］方向
のストライプ状の場合を例に説明したが、他の方向のス
トライプ、或いは矩形や円形などの場合でも成長速度０
のファセット面が得られれば良い。In the embodiment, the case where the growth region has a stripe shape in the [011] direction has been described as an example, but the growth rate is 0 even in the case of a stripe in another direction, a rectangle or a circle.
It is only necessary to obtain the facet surface of.
【００２４】さらに実施例ではＳｉ基板上の金属Ｉｎ／
（Ｉｎ）ＧａＡｓ積層構造を例に説明したが、ＩＶ族基
板がＧｅの場合、またＩＩＩ−Ｖ族化合物半導体が他の
ＡｌＡｓやＧａＰ、またＡｌＧａやＩｎＧａＰなどの混
晶の場合、さらに積層構造中に複数種類のＩＩＩ−Ｖ族
化合物半導体層（超格子構造を含む）が混在する場合に
も広く本発明を適用することができる。Further, in the embodiment, metal In / on the Si substrate
Although the (In) GaAs laminated structure has been described as an example, when the group IV substrate is Ge, or when the group III-V compound semiconductor is another AlAs or GaP, or a mixed crystal of AlGa or InGaP, the layered structure is further increased. The present invention can be widely applied to the case where a plurality of kinds of III-V group compound semiconductor layers (including a superlattice structure) are mixed in.
【００２５】[0025]
【発明の効果】以上のように本発明によれば、ＩＶ族単
結晶基板とＩＩＩ−Ｖ族エピタキシャル層の熱膨張係数
差による熱歪みをほぼ完全に緩和でき、従って熱歪みに
よる新たな転位の発生もないため、ＩＶ族半導体単結晶
基板上に高品質なＩＩＩ−Ｖ族化合物半導体単結晶層を
有する金属膜／ＩＩＩ−Ｖ族化合物半導体積層構造が実
現でき、発明の効果が示された。As described above, according to the present invention, the thermal strain due to the difference in thermal expansion coefficient between the group IV single crystal substrate and the group III-V epitaxial layer can be almost completely relaxed, so that new dislocations due to thermal strain can be generated. Since no generation occurs, a metal film / III-V compound semiconductor laminated structure having a high-quality III-V compound semiconductor single crystal layer on a IV semiconductor single crystal substrate can be realized, and the effect of the invention was shown.
【図１】本発明の実施例に係る一例としての構造および
工程を示す断面図である。FIG. 1 is a cross-sectional view showing an exemplary structure and process according to an embodiment of the present invention.
１ Ｓｉ基板 ２ ＳｉＯ2膜 ３ 第一のＧａＡｓ選択成長層 ４ ＩｎＰ選択成長層 ５ 第二のＧａＡｓ選択成長層 ６ ＩｎＧａＡｓ／ＧａＡｓ歪超格子層 ７ 第三のＧａＡｓ選択成長層 ８ 金属Ｉｎ層1 Si substrate 2 SiO2 film 3 First GaAs selective growth layer 4 InP selective growth layer 5 Second GaAs selective growth layer 6 InGaAs / GaAs strained superlattice layer 7 Third GaAs selective growth layer 8 Metal In layer
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19473692AJPH0620968A (en) | 1992-06-29 | 1992-06-29 | Metal film/compound semiconductor laminated structure on element semiconductor substrate and manufacture thereof |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19473692AJPH0620968A (en) | 1992-06-29 | 1992-06-29 | Metal film/compound semiconductor laminated structure on element semiconductor substrate and manufacture thereof |
| Publication Number | Publication Date |
|---|---|
| JPH0620968Atrue JPH0620968A (en) | 1994-01-28 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19473692AWithdrawnJPH0620968A (en) | 1992-06-29 | 1992-06-29 | Metal film/compound semiconductor laminated structure on element semiconductor substrate and manufacture thereof |
| Country | Link |
|---|---|
| JP (1) | JPH0620968A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016004942A (en)* | 2014-06-18 | 2016-01-12 | 富士通株式会社 | Manufacturing method of semiconductor nanowire and manufacturing method of semiconductor nanowire element |
| JP2018073999A (en)* | 2016-10-28 | 2018-05-10 | 国立大学法人名古屋大学 | Group III nitride semiconductor device manufacturing method |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016004942A (en)* | 2014-06-18 | 2016-01-12 | 富士通株式会社 | Manufacturing method of semiconductor nanowire and manufacturing method of semiconductor nanowire element |
| JP2018073999A (en)* | 2016-10-28 | 2018-05-10 | 国立大学法人名古屋大学 | Group III nitride semiconductor device manufacturing method |
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| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination | Free format text:JAPANESE INTERMEDIATE CODE: A300 Effective date:19990831 |