Movatterモバイル変換


[0]ホーム

URL:


JPH0537511A - Unique word detection circuit - Google Patents

Unique word detection circuit

Info

Publication number
JPH0537511A
JPH0537511AJP21276991AJP21276991AJPH0537511AJP H0537511 AJPH0537511 AJP H0537511AJP 21276991 AJP21276991 AJP 21276991AJP 21276991 AJP21276991 AJP 21276991AJP H0537511 AJPH0537511 AJP H0537511A
Authority
JP
Japan
Prior art keywords
unique word
data string
detection circuit
word detection
correlation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21276991A
Other languages
Japanese (ja)
Inventor
Haruya Iwasaki
玄弥 岩崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC CorpfiledCriticalNEC Corp
Priority to JP21276991ApriorityCriticalpatent/JPH0537511A/en
Priority to EP96114081Aprioritypatent/EP0750411B1/en
Priority to EP92112922Aprioritypatent/EP0526833B1/en
Priority to DE69233096Tprioritypatent/DE69233096T2/en
Priority to AU20663/92Aprioritypatent/AU656098B2/en
Priority to DE69224687Tprioritypatent/DE69224687T2/en
Priority to CA002074889Aprioritypatent/CA2074889C/en
Priority to US07/921,711prioritypatent/US5276710A/en
Publication of JPH0537511ApublicationCriticalpatent/JPH0537511A/en
Pendinglegal-statusCriticalCurrent

Links

Classifications

Landscapes

Abstract

PURPOSE:To detect a unique word immediately even when a large frequency error is present in an input data string by taking correlation between a delayed data string and a data string not subjected to delay. CONSTITUTION:A delay circuit 1 delays an input data string Dn by nF-bit and a correlation device 2 takes correlation between the delayed data string Dn-nF and the inputted data string Dn and outputs a correlation value Cn expressed in equation I. A comparator 3 compares the absolute value ¦Cn¦ of the correlation value Cn with a predetermined threshold level A in terms of the quantity and decides to be n=no in the case of ¦Cn¦>=A, thereby outputting a unique word detection signal. At this time, since the relation of ¦Cno¦=K is satisfied, the unique word is detected surely and immediately even if a frequency error is present thereon.

Description

Translated fromJapanese
【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、連続するフレーム信号
からなるPSK受信信号に含まれるユニークワードを検
出するユニークワード検出回路に係り、特に受信信号周
波数に大きな誤差がある時のユニークワード検出方式に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a unique word detection circuit for detecting a unique word included in a PSK reception signal composed of continuous frame signals, and particularly to a unique word detection system when there is a large error in the reception signal frequency. Regarding

【0002】[0002]

【従来の技術】本発明が対象とするユニークワード検出
回路は、各フレームの先頭に配置されるユニークワード
を検出する回路であるが、この種のユニークワード検出
回路としては、従来、例えば図2に示すものが知られて
いる。
2. Description of the Related Art A unique word detection circuit to which the present invention is directed is a circuit for detecting a unique word placed at the beginning of each frame. As a unique word detection circuit of this kind, a conventional one, for example, FIG. The ones shown in are known.

【0003】図2において、相関器21は、PSK受信
信号をディジタルサンプルした入力データ列Dn ′とユ
ニークワードパターンUk ′(1≦k≦K)との相互相
関値Cn ′を計算し、それを比較器22へ出力する。
In FIG. 2, a correlator 21 calculates a cross-correlation value Cn ′ between an input data string Dn ′ obtained by digitally sampling a PSK received signal and a unique word pattern Uk ′ (1 ≦ k ≦ K). , And outputs it to the comparator 22.

【0004】ここで、入力データ列Dn ′は、PSK受
信信号が直交検波されたものであるので、搬送波位相同
期のとられた複素信号である。そして、入力データ列D
n ′は、信号成分(即ち、送信信号)Sn ′と雑音成分
n とからなるが、信号成分Sn ′には長さKビットの
ユニークワード(そのビットパターンをUk ′とする)
が含まれている。今、ユニークワードがn=n0 の時点
まで挿入されているとすると、信号成分とユニークワー
ドとの関係は次の数式2で表せる。
Here, the input data sequence Dn ′ is a complex signal in which the carrier phase is locked because the PSK received signal is obtained by quadrature detection. Then, the input data string D
n ′ is composed of a signal component (that is, a transmission signal) Sn ′ and a noise component Nn, and the signal component Sn ′ has a unique word of length K bits (the bit pattern is Uk ′).
It is included. Now, assuming that the unique word is inserted up to the point of n = n0 , the relationship between the signal component and the unique word can be expressed by the following mathematical formula 2.

【0005】[0005]

【数2】[Equation 2]

【0006】一方、相関器21の出力(相互相関値)C
n ′は次の数式3で表せる。
On the other hand, the output (cross-correlation value) C of the correlator 21
n ′ can be expressed by the following Equation 3.

【0007】[0007]

【数3】[Equation 3]

【0008】従って、n=n0 の時の相互相関値Cn0
は、雑音成分Nn を無視すれば、次の数式4で示され、
極大値Kをとる。
Therefore, the cross-correlation value Cn0 ′ when n = n0
Is given by Equation 4 below, ignoring the noise component Nn :
Take the maximum value K.

【0009】[0009]

【数4】[Equation 4]

【0010】そこで、比較器22では、相互相関値C
n ′の絶対値│Cn ′│と予め定めた閾値A′とを比較
し、│Cn ′│≧A′となった時、n=n0 であると判
定し、ユニークワード検出信号を出力する。
Therefore, in the comparator 22, the cross-correlation value C
'comparing the, │Cn' threshold A determined in advance and │ 'absolute value │Cn of'n when he became │ ≧ A ', is determined that the n = n0, the unique word detection signal Output.

【0011】[0011]

【発明が解決しようとする課題】上述した従来のユニー
クワード検出回路では、入力データ列Dn ′の搬送波同
期がとれていない時、即ち、入力データ列Dn ′に周波
数誤差Δfがある時、相互相関値Cn0は、次の数式5と
なり、│Cn0′│は極大値とならないので、ユニークワ
ードを検出できない。
In the conventional unique word detection circuit described above, when the carrier wave of the input data string Dn ′ is not synchronized, that is, when there is a frequency error Δf in the input data string Dn ′, The cross-correlation value Cn0 is given by the following expression 5, and | Cn0 ′ | does not have the maximum value, so that the unique word cannot be detected.

【0012】[0012]

【数5】[Equation 5]

【0013】つまり、従来のユニークワード検出回路で
は、入力データ列Dn ′は予め搬送波同期が確立されて
いることが必要である。従って、周波数誤差Δfが大き
い時には、搬送波同期に相当の時間を要するので、ユニ
ークワードの検出に長時間を要するという問題がある。
That is, in the conventional unique word detection circuit, it is necessary that carrier synchronization is established in advance for the input data string Dn ′. Therefore, when the frequency error Δf is large, it takes a considerable time to synchronize the carrier wave, and thus it takes a long time to detect the unique word.

【0014】本発明の目的は、入力データ列に大きな周
波数誤差があるときでも即時にユニークワードの検出を
行うことのできるユニークワード検出回路を提供するこ
とにある。
It is an object of the present invention to provide a unique word detection circuit which can immediately detect a unique word even when there is a large frequency error in an input data string.

【0015】[0015]

【課題を解決するための手段】前記目的を達成するため
に、本発明のユニークワード検出回路は次の如き構成を
有する。即ち、本発明のユニークワード検出回路は、連
続するフレーム信号からなるPSK受信信号中のユニー
クワード(各フレームの先頭に配置される)を検出する
ユニークワード検出回路であって; このユニークワー
ド検出回路は、フレームの長さをnF ビット、ユニーク
ワードの長さをKビットとし、隣接する2つのフレーム
におけるユニークワードの各ビットをUk1、Uk2(1≦
k≦K)としたとき、前記PSK受信信号をディジタル
サンプルしたデータ列Dn をnF ビット遅延させたデー
タ列Dn-nFを出力する遅延回路と; 前記データ列Dn
と前記遅延回路の出力Dn-nFとを受けて
In order to achieve the above object, the unique word detection circuit of the present invention has the following configuration. That is, the unique word detection circuit of the present invention is a unique word detection circuit that detects a unique word (arranged at the beginning of each frame) in a PSK reception signal composed of continuous frame signals. Has a frame length of nF bits and a unique word length of K bits, and each bit of the unique words in two adjacent frames is Uk1 , Uk2 (1 ≦
When k ≦ K), a delay circuit for outputting a data string Dn- nF obtained by delaying the data string Dn obtained by digitally sampling the PSK received signal by nF bits; and the data string Dn.
And the output Dn-nF of the delay circuit

【0016】[0016]

【数6】[Equation 6]

【0017】で表される相関値Cn を出力する相関器
と; 前記相関値Cn が予め定められた閾値を越えたと
きユニークワード検出信号を出力する比較器と; を備
えることを特徴とするものである。
A correlator that outputs a correlation value Cn represented by: a comparator that outputs a unique word detection signal when the correlation value Cn exceeds a predetermined threshold value; To do.

【0018】[0018]

【作用】次に、前記の如く構成される本発明のユニーク
ワード検出回路の作用を説明する。本発明では、データ
列Dn をnF ビット遅延させたデータ列Dn-nFと遅延し
ていないデータ列Dn との相関をとる。その結果、相関
値の絶対値は周波数誤差の影響を全く受けないものとな
る。
Next, the operation of the unique word detection circuit of the present invention constructed as described above will be described. In the present invention, the data string Dn-nF obtained by delaying the data string Dn by nF bits is correlated with the data string Dn which is not delayed. As a result, the absolute value of the correlation value is completely unaffected by the frequency error.

【0019】従って、本発明によれば、データ列Dn
大きな周波数誤差があるときでも即時にユニークワード
の検出ができる。
Therefore, according to the present invention, the unique word can be detected immediately even when the data string Dn has a large frequency error.

【0020】[0020]

【実施例】以下、本発明の実施例を図面を参照して説明
する。図1(a)は、本発明の一実施例に係るユニーク
ワード検出回路を示す。本発明では、遅延回路1を設
け、遅延回路1にて遅延した遅延データ列と遅延してい
ない本来のデータ列とを相関器2に入力させるようにし
てある。図1(b)は伝送フレームのフォーマットを示
すが、フレームの長さをnF ビット、ユニークワードの
長さをKビットとし、隣接する2つのフレームにおける
ユニークワードの各ビットパターンをUk1、Uk2(1≦
k≦K)とし、以下本発明のユニークワード検出回路の
動作を説明する。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A shows a unique word detection circuit according to an embodiment of the present invention. In the present invention, the delay circuit 1 is provided, and the delayed data string delayed by the delay circuit 1 and the original data string not delayed are input to the correlator 2. FIG. 1B shows the format of a transmission frame. The frame length is nF bits, the unique word length is K bits, and each unique word bit pattern in two adjacent frames is Uk1 , Uk2 (1 ≦
The operation of the unique word detection circuit of the present invention will be described below with k ≦ K).

【0021】まず、信号成分(送信信号)Sn とユニー
クワードとの関係は、2つ目のユニークワードUk2の最
終ビットの時刻をn=n0 とすると、次の数式7、同8
と表せる。
First, regarding the relationship between the signal component (transmission signal) Sn and the unique word, when the time of the last bit of thesecond unique word Uk2 is n = n0 , the following equations 7 and 8 are given.
Can be expressed as

【0022】[0022]

【数7】[Equation 7]

【0023】[0023]

【数8】[Equation 8]

【0024】また、周波数誤差Δfを持つ入力データ列
n は、次の数式9で表せる。
The input data string Dn having the frequency error Δf can be expressed by the following equation 9.

【0025】[0025]

【数9】[Equation 9]

【0026】遅延回路1は、入力データ列Dn をnF
ット遅延させるので、相関器2は遅延データ列Dn-nF
入力データ列Dn との相関をとり、前記数式6で表され
る相関値Cn を出力する。
Since the delay circuit 1 delays the input data sequence Dn by nF bits, the correlator 2 correlates the delay data sequence Dn-nF with the input data sequence Dn and is expressed by the above equation (6). And outputs a correlation value Cn .

【0027】ここで、数式6に同9を代入すると、次の
数式10のようになる。
Here, by substituting the same 9 into the equation 6, the following equation 10 is obtained.

【0028】[0028]

【数10】[Equation 10]

【0029】そして、n=n0 のときは、数式10に前
記数式7、同8を代入すると、Cn0は次の数式11とな
る。
When n = n0 , substituting the equations 7 and 8 into the equation 10, Cn0 becomes the following equation 11.

【0030】[0030]

【数11】[Equation 11]

【0031】すると、比較器3は、前述したように相関
値Cn の絶対値│Cn │と予め定められた閾値Aとの大
小関係を比較し、│Cn │≧Aの時、n=n0 と判定し
て、ユニークワード検出信号を出力するが、│Cn0│=
Kであるから、周波数誤差があってもそれとは無関係に
確実に、且つ、即時にユニークワードを検出できる。
Then, the comparator 3 compares the absolute value | Cn | of the correlation value Cn with the predetermined threshold value A as described above, and when | Cn | ≧ A, n is satisfied. = N0 , a unique word detection signal is output, but | Cn0 | =
Since it is K, even if there is a frequency error, the unique word can be detected reliably and immediately regardless of it.

【0032】[0032]

【発明の効果】以上説明したように、本発明のユニーク
ワード検出回路によれば、入力データ列Dn をnF ビッ
ト遅延させた遅延データ列Dn-nFと遅延していない本来
の入力データ列Dn との相関をとり、その相関値の絶対
値が周波数誤差の影響を全く受けないものとなるように
したので、入力データ列Dn に大きな周波数誤差がある
ときでも確実且つ即時にユニークワードを検出できる効
果がある。
As described above, according to the unique word detection circuit of the present invention, the input data string Dn is delayed by nF bits and the delayed data string Dn-nF is not delayed from the original input data. Correlation with the column Dn is performed so that the absolute value of the correlation value is completely unaffected by the frequency error. Therefore, even when the input data sequence Dn has a large frequency error, it can be surely and immediately unique. It has the effect of detecting words.

【図面の簡単な説明】[Brief description of drawings]

【図1】図(a)は本発明の一実施例に係るユニークワ
ード検出回路の構成ブロック図、図(b)は伝送フレー
ムのフォーマットである。
FIG. 1A is a configuration block diagram of a unique word detection circuit according to an embodiment of the present invention, and FIG. 1B is a format of a transmission frame.

【図2】従来のユニークワード検出回路の構成ブロック
図である。
FIG. 2 is a configuration block diagram of a conventional unique word detection circuit.

【符号の説明】[Explanation of symbols]

1 遅延回路 2 相関器 3 比較器 1 Delay circuit 2 Correlator 3 Comparator

Claims (1)

Translated fromJapanese
【特許請求の範囲】【請求項1】 連続するフレーム信号からなるPSK受
信信号中のユニークワード(各フレームの先頭に配置さ
れる)を検出するユニークワード検出回路であって;
このユニークワード検出回路は、フレームの長さをnF
ビット、ユニークワードの長さをKビットとし、隣接す
る2つのフレームにおけるユニークワードの各ビットを
k1、Uk2(1≦k≦K)としたとき、前記PSK受信
信号をディジタルサンプルしたデータ列Dn をnF ビッ
ト遅延させたデータ列Dn-nFを出力する遅延回路と;
前記データ列Dn と前記遅延回路の出力Dn-nFとを受け
て【数1】で表される相関値Cn を出力する相関器と; 前記相関
値Cnが予め定められた閾値を越えたときユニークワー
ド検出信号を出力する比較器と; を備えることを特徴
とするユニークワード検出回路。
Claim: What is claimed is: 1. A unique word detection circuit for detecting a unique word (arranged at the beginning of each frame) in a PSK reception signal composed of continuous frame signals;
This unique word detection circuit determines the frame length to be nF
When the bit and the length of the unique word are K bits and each bit of the unique word in two adjacent frames is Uk1 and Uk2 (1 ≦ k ≦ K), the PSK received signal is digitally sampled. A delay circuit that outputs a data string Dn-nF by delaying the data string Dn by nF bits;
Receiving the data string Dn and the output Dn-nF of the delay circuit, A correlator that outputs a correlation value Cn represented by: a comparator that outputs a unique word detection signal when the correlation value Cn exceeds a predetermined threshold value; Detection circuit.
JP21276991A1991-07-301991-07-30Unique word detection circuitPendingJPH0537511A (en)

Priority Applications (8)

Application NumberPriority DateFiling DateTitle
JP21276991AJPH0537511A (en)1991-07-301991-07-30Unique word detection circuit
EP96114081AEP0750411B1 (en)1991-07-301992-07-29Unique word detector for use in a coherent demodulator
EP92112922AEP0526833B1 (en)1991-07-301992-07-29Carrier frequency error detector capable of accurately detecting a carrier frequency error
DE69233096TDE69233096T2 (en)1991-07-301992-07-29 Single word detector circuit for use in a coherent demodulator
AU20663/92AAU656098B2 (en)1991-07-301992-07-29Carrier frequency error detector capable of accurately detecting a carrier frequency error
DE69224687TDE69224687T2 (en)1991-07-301992-07-29 Carrier frequency error detector circuit for accurate detection of a carrier frequency error
CA002074889ACA2074889C (en)1991-07-301992-07-29Carrier frequency error detector capable of accurately detecting a carrier frequency error
US07/921,711US5276710A (en)1991-07-301992-07-30Carrier frequency error detector capable of accurately detecting a carrier frequency error

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP21276991AJPH0537511A (en)1991-07-301991-07-30Unique word detection circuit

Publications (1)

Publication NumberPublication Date
JPH0537511Atrue JPH0537511A (en)1993-02-12

Family

ID=16628096

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP21276991APendingJPH0537511A (en)1991-07-301991-07-30Unique word detection circuit

Country Status (1)

CountryLink
JP (1)JPH0537511A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
EP0660561A1 (en)*1993-12-231995-06-28STMicroelectronics S.A.Circuit for recognition of a sequence of words in a modem
US6111922A (en)*1994-12-202000-08-29Sgs-Thomson Microelectronics S.A.Circuit for detecting word sequences in a modem
EP1237319A1 (en)*2001-02-262002-09-04Juniper Networks, Inc.Methods and apparatus for efficient and accurate coarse timing synchronization in burst demodulators
JP2003244763A (en)*2002-02-142003-08-29Ntt Docomo Inc Mobile communication system, channel synchronization establishment method, and mobile station
USRE38391E1 (en)1993-12-232004-01-20Stmicroelectronics S.A.Circuit for detecting word sequences in a modem
JP2007135230A (en)*1995-10-312007-05-31Thomson Multimedia SaMethod for cascading detachable conditional access modules, circuit for inserting predetermined sequence and circuit for detecting said sequence in order to implement the method
WO2010023843A1 (en)2008-08-272010-03-04日野自動車株式会社Cross member-integrated trunnion bracket

Citations (3)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS49114309A (en)*1973-02-121974-10-31
JPS63196129A (en)*1987-02-101988-08-15Matsushita Electric Ind Co Ltd Spread spectrum communication receiver
JPH04346532A (en)*1991-05-241992-12-02Kokusai Denshin Denwa Co Ltd <Kdd> Frame synchronization method and device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS49114309A (en)*1973-02-121974-10-31
JPS63196129A (en)*1987-02-101988-08-15Matsushita Electric Ind Co Ltd Spread spectrum communication receiver
JPH04346532A (en)*1991-05-241992-12-02Kokusai Denshin Denwa Co Ltd <Kdd> Frame synchronization method and device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
USRE38391E1 (en)1993-12-232004-01-20Stmicroelectronics S.A.Circuit for detecting word sequences in a modem
FR2714558A1 (en)*1993-12-231995-06-30Sgs Thomson Microelectronics Circuit for recognizing a sequence of words in a modem.
US5661752A (en)*1993-12-231997-08-26Sgs-Thomson Microelectronics S.A.Circuit for detecting word sequences in a modem
EP0660561A1 (en)*1993-12-231995-06-28STMicroelectronics S.A.Circuit for recognition of a sequence of words in a modem
US6111922A (en)*1994-12-202000-08-29Sgs-Thomson Microelectronics S.A.Circuit for detecting word sequences in a modem
JP2007135230A (en)*1995-10-312007-05-31Thomson Multimedia SaMethod for cascading detachable conditional access modules, circuit for inserting predetermined sequence and circuit for detecting said sequence in order to implement the method
EP1237319A1 (en)*2001-02-262002-09-04Juniper Networks, Inc.Methods and apparatus for efficient and accurate coarse timing synchronization in burst demodulators
US7154967B2 (en)2001-02-262006-12-26Juniper Networks, Inc.Methods and apparatus for efficient and accurate coarse timing synchronization in burst demodulators
US7616717B2 (en)2001-02-262009-11-10Juniper Networks, Inc.Coarse timing synchronization
US7957494B2 (en)2001-02-262011-06-07Juniper Networks, Inc.Coarse timing synchronization
US8451958B2 (en)2001-02-262013-05-28Juniper Networks, Inc.Coarse time synchronization
JP2003244763A (en)*2002-02-142003-08-29Ntt Docomo Inc Mobile communication system, channel synchronization establishment method, and mobile station
WO2010023843A1 (en)2008-08-272010-03-04日野自動車株式会社Cross member-integrated trunnion bracket
US8342565B2 (en)2008-08-272013-01-01Hino Motors, Ltd.Cross member-integrated trunnion bracket

Similar Documents

PublicationPublication DateTitle
US5099477A (en)Phase matching circuit
WO2007088773A1 (en)Radio receiving apparatus and radio receiving method
US5754606A (en)Clock signal regenerating circuit
JPH09135234A (en)Short burst trapping circuit for direct sequence spread spectrum link
JP2003051743A (en)Data recovery circuit and method thereof
JPH0537511A (en)Unique word detection circuit
JPH09186734A (en) Synchronizer
KR100998773B1 (en) System and method for generating deserialization timing signals
EP1078471A1 (en)Method and apparatus for accurate synchronization using symbol decision feedback
US6337650B1 (en)System and method for regenerating clock signal
US6104435A (en)Apparatus and method for generating data segment sync signal for HDTV
JPH11261547A (en)Over sampling clock recovery circuit
KR100900277B1 (en) Method and apparatus for recovering synchronization on a signal transmitted to a mobile telephone receiver
US11146432B2 (en)Radio signal detection
KR100392312B1 (en)Tdma system receiver
JP3412558B2 (en) Clock frequency control method and receiving device used therefor
KR100725486B1 (en) Timing synchronization detecting device and method for communication device and communication device using same
JPS5912644A (en)Synchronizing system of spread spectrum communication device
JPH10190619A (en) Synchronizer
JP2950351B2 (en) Pulse signal generation circuit
US20040146124A1 (en)Algorithm for timing recovery in a fsk correlation receiver and fsk correlation receiver therewith
JP2522398B2 (en) Phase control device
JP3447882B2 (en) Synchronizer
JP3047627B2 (en) Synchronization maintenance device
US7020795B2 (en)Operating method for detecting and solving underflow and overflow by using oversampling

[8]ページ先頭

©2009-2025 Movatter.jp