【０００１】[0001]
【産業上の利用分野】本発明はインジウムバンプの製造
方法に係り、半導体基板の電極上に設けられて他の半導
体基板上もしくは回路基板上の電極と圧接接続して両者
の電気的、機械的接続を得るインジウムバンプの製造に
提供されるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an indium bump, which is provided on an electrode of a semiconductor substrate and is pressure-connected to another semiconductor substrate or an electrode on a circuit board to electrically and mechanically connect both electrodes. It is intended for the manufacture of indium bumps for obtaining connections.
【０００２】[0002]
【従来の技術】図４〜図７に従来のインジウムバンプの
製造方法を示す。なお、実際の素子では、複数のインジ
ウムバンプが一次元又は二次元に配列され形成される
が、説明を簡単にする為に１バンプ分を抽出してある。2. Description of the Related Art FIGS. 4 to 7 show a conventional method for manufacturing an indium bump. In an actual device, a plurality of indium bumps are arranged and formed one-dimensionally or two-dimensionally, but one bump is extracted for simplicity of explanation.
【０００３】まず、シリコン基板１１に形成された機能
素子（図示は省略）、基板上の絶縁膜１２の信号入力部
又は出力部に対応した位置に設けられた貫通孔、そして
この貫通孔を介して信号入力部又は出力部と電気的に接
続されて成る電極１３を有するウェファ（図４（ａ））
上にチタン層１４、銅層１５を各々０．１μｍ、１μｍ
の厚さに真空蒸着法により被着する（図４（ｂ））。First, a functional element (not shown) formed on a silicon substrate 11, a through hole provided at a position corresponding to a signal input portion or an output portion of the insulating film 12 on the substrate, and the through hole are provided. Having an electrode 13 electrically connected to a signal input section or an output section (FIG. 4 (a))
A titanium layer 14 and a copper layer 15 are formed on top of each of 0.1 μm and 1 μm.
Is deposited by the vacuum vapor deposition method to the thickness (FIG. 4B).
【０００４】次にフォーミングガス中にて４２０℃２０
分程度の熱処理を施し、上記電極１３とチタン膜１４と
をシンターする。Next, at a temperature of 420 ° C. in forming gas at 20 ° C.
Heat treatment is performed for about a minute to sinter the electrode 13 and the titanium film 14.
【０００５】次に、ポジ型厚膜レジストであるＴＦ−２
０ １６（商品名、東京応化製）を５μｍ〜７μｍスピ
ンコートし、光蝕刻プロセスによって信号入力部又は、
出力部に対応した部分のレジストに開孔１６ａを設ける
（図５（ａ））。Next, TF-2 which is a positive type thick film resist.
0 16 (trade name, manufactured by Tokyo Ohka) is spin-coated on a surface of 5 μm to 7 μm, and a signal input portion or a photo-etching process is performed.
An opening 16a is provided in the resist corresponding to the output portion (FIG. 5A).
【０００６】次に、上記銅膜１５を陰極電極としてレジ
ストの開孔部１６ａに電気めっきによって５〜７μｍ厚
に銅めっき層２５を選択的に形成しペデスタル状にする
（図５（ｂ））。次いでニッケル層１７を０．５〜１μ
ｍ厚に電気めっきを施し（図５（ｃ））、更にインジウ
ムを約７μｍ厚電気めっきを施してインジウムバンプ１
８を形成する（図６（ａ））。なお、ここでのＮｉめっ
きはインジウムと銅のバリヤとして作用する。Next, using the copper film 15 as a cathode electrode, a copper plating layer 25 having a thickness of 5 to 7 .mu.m is selectively formed by electroplating on the opening 16a of the resist to form a pedestal shape (FIG. 5B). .. Then, the nickel layer 17 is 0.5 to 1 μm.
Indium bump 1 was electroplated to a thickness of m (FIG. 5C), and indium was further electroplated to a thickness of about 7 μm.
8 is formed (FIG. 6A). The Ni plating here acts as a barrier between indium and copper.
【０００７】次に、選択めっきに用いたレジスト１６を
除去し、銅の蒸着膜１５を露出し、この銅の膜１５及び
その下のチタン膜１４をエッチ除去する事により電気的
に独立した複数のインジウムバンプを得る（図６
（ｂ））。Next, the resist 16 used for the selective plating is removed, the copper vapor deposition film 15 is exposed, and the copper film 15 and the titanium film 14 thereunder are removed by etching to form a plurality of electrically independent films. Indium bumps of
(B)).
【０００８】次にダイシング等の手段によりチップとし
た後、チップ表面全体にロジン系フラックスを塗布し、
熱板上で１８０℃〜１９０℃の加熱を施してインジウム
を溶融し、インジウムの表面張力を利用し球状化する。
次いで有機溶剤によりフラックスを洗浄除去し、圧接接
続に供される球状化インジウムバンプ２８を形成する
（図７）。Next, after dicing or the like to form a chip, a rosin flux is applied to the entire surface of the chip,
The indium is melted by heating at 180 ° C to 190 ° C on the hot plate, and the surface tension of the indium is used to make it spherical.
Then, the flux is washed away with an organic solvent to form spheroidal indium bumps 28 to be used for pressure contact connection (FIG. 7).
【０００９】以上説明した従来法によるインジウムバン
プ製造法には、最終形状が銅のペデスタル上にＮｉバリ
ヤを介してインジウムバンプが球状化されるという利点
がある。すなわち蒸着した銅の厚さに加えめっき法によ
り形成した銅の厚さ分はインジウムと半導体基板間のス
ペーサーとしての作用を有し、圧接時にインジウムが変
形してもインジウムと半導体基板と接触することがな
く、いたずらに電気容量を増すという事態を回避出来
る。The indium bump manufacturing method according to the conventional method described above has an advantage that the indium bump is spheroidized through the Ni barrier on the pedestal whose final shape is copper. That is, in addition to the thickness of the vapor-deposited copper, the thickness of the copper formed by the plating method acts as a spacer between the indium and the semiconductor substrate, so that even if the indium is deformed during press contact, it can contact the indium and the semiconductor substrate. Therefore, it is possible to avoid the situation where the electric capacity is unnecessarily increased.
【００１０】[0010]
【発明が解決しようとする課題】上記従来の製造法には
次に述べるインジウム電気めっきの特異性による不具合
がしばしば発生する欠点がある。上記製造法のうち銅、
ニッケルの電気めっきは非常にスムーズに進行するが、
インジウム電気めっきはめっきの核の形成が一様に速や
かに形成されず、下地金属から上方（厚みの増す方向）
へのめっき進行よりも下地金属の周辺部から外方向へ進
行する方が早い。しかも必ずしも等方性は有しない。従
ってめっきされたインジウム量の個々のバラツキが大き
いという結果を生じる。従って、後工程でのインジウム
の球状化のバンプ径、高さも必然的にバラツキを有し、
圧接時の単位面積当りの圧力、インジウム変形量にも波
及し、圧接（着）性に大きな影響をもたらす。極端な場
合、バンプ径が小さい（必然的にバンプ高さも低い）も
のは電気的接続が不十分もしくは動作中に接触劣化を生
じるという致命的な不具合がある。The above-mentioned conventional manufacturing method has a drawback that the following problems often occur due to the peculiarities of indium electroplating. Copper in the above manufacturing method,
Nickel electroplating proceeds very smoothly,
In the case of indium electroplating, the formation of plating nuclei is not uniformly and rapidly, and the plating metal is formed above the base metal (in the direction of increasing thickness).
It is faster to proceed outward from the periphery of the base metal than to the plating process. Moreover, it is not necessarily isotropic. This results in large individual variations in the amount of plated indium. Therefore, the bump diameter and the height of the spheroidized indium in the post-process inevitably have variations,
It also affects the pressure per unit area during press contact and the amount of indium deformation, which has a great effect on the press contact (bonding) property. In an extreme case, a bump having a small diameter (necessarily also having a low bump height) has a fatal defect that electrical connection is insufficient or contact deterioration occurs during operation.
【００１１】また、上記インジウム電気めっきはやり直
しが困難であるので、歩留低下、ロットアウト等の経済
的損失が大きい欠点がある。Further, since the above-mentioned indium electroplating is difficult to be redone, there is a drawback that economic loss such as yield reduction and lot-out is large.
【００１２】本発明は上記事情を考慮してなされたもの
で、インジウムバンプ直下のペデスタル構造の利点を損
うことなくバンプ径、バンプ高さが均一に形成できるイ
ンジウムバンプの製造方法を提供する事を目的とする。The present invention has been made in consideration of the above circumstances, and provides a method for manufacturing an indium bump in which the bump diameter and bump height can be formed uniformly without impairing the advantages of the pedestal structure directly below the indium bump. With the goal.
【００１３】[0013]
【課題を解決するための手段】本発明に係るペデスタル
付インジウムバンプの製造方法は、複数の電極を備えた
半導体基板の一主面上にレジスト厚膜を塗布し前記電極
に対応する部位に開孔を設ける工程と、前記開孔にペデ
スタル状に金属をめっき形成する工程と、真空蒸着法に
よって全面にインジウム層を形成する工程と、前記イン
ジウム層の一部を前記ペデスタル上に残置パターニング
する工程と、前記ペデスタル上のインジウム層を溶融し
球状化する工程を具備することを特徴とする。また、ペ
デスタルを形成するめっき金属が基板側から銅、ニッケ
ルであることを特徴とする。A method of manufacturing an indium bump with a pedestal according to the present invention comprises applying a resist thick film on one main surface of a semiconductor substrate having a plurality of electrodes, and opening a portion corresponding to the electrodes. Forming a hole, forming a pedestal-like metal in the opening, forming an indium layer on the entire surface by vacuum deposition, and partially patterning the indium layer on the pedestal. And melting the indium layer on the pedestal to make it spherical. The plating metal forming the pedestal is copper or nickel from the substrate side.
【００１４】[0014]
【作用】本発明によれば、ペデスタル構造で均一性に優
れたインジウムバンプを得ることができる。According to the present invention, an indium bump having a pedestal structure and excellent uniformity can be obtained.
【００１５】[0015]
【実施例】（実施例１）以下、本発明の一実施例につい
て一部の図２、および図１を参照して説明する。(Embodiment 1) An embodiment of the present invention will be described below with reference to some of FIG. 2 and FIG.
【００１６】本発明では従来の銅、ニッケルの電気めっ
きまでの工程、すなわち図４（ａ）〜５（ｃ）によって
説明された従来の工程を援用し、説明を省略する。In the present invention, the conventional steps up to the electroplating of copper and nickel, that is, the conventional steps described with reference to FIGS.
【００１７】上記ニッケル電気めっき終了後、真空蒸着
装置にウェファをセットし、インジウム層８を約５μｍ
の厚さ全面蒸着する（図１（ａ））。この時インジウム
層８はレジスト上にも蒸着されるが、レジストの劣化の
恐れは皆無である。After completion of the nickel electroplating, the wafer is set in a vacuum vapor deposition apparatus to form an indium layer 8 having a thickness of about 5 μm.
Is vapor-deposited on the entire surface (FIG. 1A). At this time, the indium layer 8 is vapor-deposited on the resist, but there is no possibility of deterioration of the resist.
【００１８】次にレジスト層２６を塗布し光蝕刻プロセ
スによって、バンプ形成に必要な部分を除きエッチング
を施し、インジウム層３８を形成する（図１（ｂ））。Next, a resist layer 26 is applied, and an indium layer 38 is formed by a photo-etching process, except for portions required for bump formation, and etching is performed (FIG. 1B).
【００１９】次に選択めっきに用いた厚いレジスト層１
６を除去する（図２（ａ））。Next, a thick resist layer 1 used for selective plating
6 is removed (FIG. 2 (a)).
【００２０】次に銅層１５およびチタン層１４にエッチ
ングを施しペデスタル部分以外の部分を除去する（図２
（ｂ））。Next, the copper layer 15 and the titanium layer 14 are etched to remove portions other than the pedestal portion (FIG. 2).
(B)).
【００２１】次にダイシング等の手段によりチップとし
た後、チップ表面全体にロジン系フラックスを塗布し、
熱板上で１８０℃〜１９０℃の加熱を施してインジウム
を溶融し、インジウムの表面張力を利用して球状化す
る。次いで有機溶剤によりフラックスを洗浄除去し、圧
接接続に供される球状化インジウムバンプ２８を形成す
る（図３）。Next, after dicing or the like to form a chip, a rosin-based flux is applied to the entire surface of the chip,
The indium is melted by heating it on a hot plate at 180 ° C to 190 ° C, and is spheroidized by utilizing the surface tension of indium. Next, the flux is washed away with an organic solvent to form the spheroidal indium bumps 28 to be used for pressure contact connection (FIG. 3).
【００２２】本発明のインジウムバンプの製造法では、
問題の多いインジウムメッキを避け、蒸着−パターニン
グというプロセスで形成する為に、パンプの体積を均一
なものとする事が出来る、従って球状化後のインジウム
バンプの径、高さも必然的に均一となる特徴があり、従
来法の欠点を除去出来る。In the method for manufacturing an indium bump according to the present invention,
Since the problem of indium plating is avoided and it is formed by a process of vapor deposition-patterning, it is possible to make the volume of the pump uniform, and therefore the diameter and height of the indium bump after spheroidization are inevitably uniform. It has features and can eliminate the drawbacks of the conventional method.
【００２３】そして、蒸着−パターニング法で得られる
インジウムの体積で球状化した後のバンプの必要な寸法
が得られる可否について、以下説明する。Then, whether or not the necessary dimension of the bump after spheroidizing with the volume of indium obtained by the vapor deposition-patterning method can be obtained will be described below.
【００２４】例えば球状化したバンプが真球であると仮
定すると、真球の体積はFor example, assuming that the spherical bump is a true sphere, the volume of the true sphere is
【数１】である。今、真球とした球の直径（高さも）が３０μｍ
必要であるとするとインジウムの体積は[Equation 1] Is. Now, the diameter (and height) of a true sphere is 30 μm.
If it is necessary, the volume of indium is
【数２】である。一方、バンプピッチが６０μｍであるとする
と、光蝕刻技術で問題なく実施出来るスペース（レジス
トとレジストの間隔）は５μｍあれば十分であり、イン
ジウムを残すパターン寸法は５５μｍの正方形が可能で
ある。従って、上記した真球の体積を５５μｍの面積で
割ると、インジウムの厚さ（ｔ：次式）が得られ[Equation 2] Is. On the other hand, if the bump pitch is 60 μm, the space (resist-to-resist space) that can be implemented without problems by the photo-etching technique is 5 μm, and the pattern dimension for leaving indium is 55 μm square. Therefore, when the volume of the above-mentioned true sphere is divided by the area of 55 μm, the thickness of indium (t: the following equation) is obtained.
【数３】となる。結局、約５μｍ厚にインジウム層を蒸着し、一
辺が５５μｍの正方形の残置パターンを形成する事が必
要となるが、これらは現在の公知の技術で十分達成出来
るものであり、本発明の実施は極めて容易に達成できる
ことが明らかである。[Equation 3] Becomes After all, it is necessary to deposit an indium layer with a thickness of about 5 μm to form a remaining pattern of a square with a side of 55 μm, but these can be sufficiently achieved by the currently known technique, and the present invention can be implemented. It is clear that this can be achieved very easily.
【００２５】なお、実際にはインジウム直下には下地金
属（本発明の場合は銅ペデスタル上のニッケル）がある
面積をもって存在する為、真球にはならないが、球状化
バンプの高さは上記寸法を当てはめても２０μｍ以上に
得られるので、バンプ圧接には十分である。In reality, since the underlying metal (nickel on the copper pedestal in the present invention) is present immediately below the indium, it does not become a true sphere, but the height of the spheroidized bump is the above-mentioned dimension. Even if it is applied, it is possible to obtain 20 μm or more, which is sufficient for bump pressure welding.
【００２６】[0026]
【発明の効果】本発明によれば、新規な設備、技術を必
要としないで均一性の良いインジウムバンプを提供出来
る。しかも従来法の利点であるペデスタル構造を損う事
もない。According to the present invention, an indium bump having good uniformity can be provided without requiring new equipment and technology. Moreover, the pedestal structure, which is an advantage of the conventional method, is not damaged.
【図１】（ａ）および（ｂ）は本発明の一実施例につき
その一部を工程順に示すいずれも断面図、1A and 1B are cross-sectional views each showing a part of the process order according to an embodiment of the present invention,
【図２】（ａ）および（ｂ）は本発明の一実施例につき
「図１」に続いてその一部を工程順に示すいずれも断面
図、2 (a) and 2 (b) are cross-sectional views each showing a part of the process sequence in the order of "FIG. 1" following one embodiment of the present invention;
【図３】本発明の一実施例につき「図２」に続いてその
一部を工程順に示す断面図、FIG. 3 is a cross-sectional view showing a part of the process sequence in the order of “FIG. 2” according to one embodiment of the present invention;
【図４】（ａ）および（ｂ）は従来例につきその一部を
工程順に示すいずれも断面図、4A and 4B are cross-sectional views each showing a part of the conventional example in the order of steps,
【図５】（ａ）ないし（ｃ）は従来例につき「図４」に
続いてその一部を工程順に示すいずれも断面図、5 (a) to 5 (c) are cross-sectional views each showing a part in the order of steps following "FIG. 4" for a conventional example,
【図６】（ａ）および（ｂ）は従来例につき「図５」に
続いてその一部を工程順に示すいずれも断面図、6 (a) and 6 (b) are cross-sectional views each showing a part in the order of steps following "FIG. 5" for a conventional example,
【図７】従来例につき「図６」に続いてその一部を工程
順に示す断面図。FIG. 7 is a cross-sectional view showing part of the process in the order of steps subsequent to “FIG. 6” in the conventional example.
８ インジウム層 １１ シリコン半導体基板 １２ 絶縁膜 １３ 電極 １４ チタン層 １５ 銅層 １６ （厚膜）レジスト １６ａ レジストの開孔 ２５ めっき層（めっき）銅層 １７ （めっき）ニッケル層 １８ インジウムバンプ ２８ 球状化したインジウムバンプ ３８ インジウムの蒸着層 8 indium layer 11 silicon semiconductor substrate 12 insulating film 13 electrode 14 titanium layer 15 copper layer 16 (thick film) resist 16a opening of resist 25 plating layer (plating) copper layer 17 (plating) nickel layer 18 indium bump 28 spheroidized Indium bump 38 Indium vapor deposition layer
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04137353AJP3078646B2 (en) | 1992-05-29 | 1992-05-29 | Method for manufacturing indium bump |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04137353AJP3078646B2 (en) | 1992-05-29 | 1992-05-29 | Method for manufacturing indium bump |
| Publication Number | Publication Date |
|---|---|
| JPH05335313Atrue JPH05335313A (en) | 1993-12-17 |
| JP3078646B2 JP3078646B2 (en) | 2000-08-21 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04137353AExpired - LifetimeJP3078646B2 (en) | 1992-05-29 | 1992-05-29 | Method for manufacturing indium bump |
| Country | Link |
|---|---|
| JP (1) | JP3078646B2 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7135770B2 (en) | 2002-02-07 | 2006-11-14 | Nec Corporation | Semiconductor element with conductive columnar projection and a semiconductor device with conductive columnar projection |
| JP2006332694A (en)* | 2006-07-24 | 2006-12-07 | Megic Corp | Method for forming metal bumps on semiconductor surface |
| JP2008277677A (en)* | 2007-05-07 | 2008-11-13 | Sony Corp | Semiconductor chip, and manufacturing method thereof |
| JP2008547207A (en)* | 2005-06-14 | 2008-12-25 | キュービック・ウエハ・インコーポレーテッド | Electronic chip contact structure |
| US8569897B2 (en) | 2009-09-14 | 2013-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection layer for preventing UBM layer from chemical attack and oxidation |
| US8569887B2 (en) | 2009-11-05 | 2013-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post passivation interconnect with oxidation prevention layer |
| US8581400B2 (en) | 2011-10-13 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-passivation interconnect structure |
| US8609526B2 (en) | 2009-10-20 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Preventing UBM oxidation in bump formation processes |
| US8610285B2 (en) | 2011-05-30 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC packaging structures and methods with a metal pillar |
| US8664760B2 (en) | 2011-05-30 | 2014-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connector design for packaging integrated circuits |
| US8716858B2 (en) | 2011-06-24 | 2014-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure with barrier layer on post-passivation interconnect |
| US8841766B2 (en) | 2009-07-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
| US8846445B2 (en) | 2005-06-14 | 2014-09-30 | Cufer Asset Ltd. L.L.C. | Inverse chip connector |
| US8847387B2 (en) | 2009-10-29 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust joint structure for flip-chip bonding |
| US8922004B2 (en) | 2010-06-11 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump structures having sidewall protection layers |
| US8952534B2 (en) | 2010-02-09 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and semiconductor assembly with lead-free solder |
| US9018758B2 (en) | 2010-06-02 | 2015-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall spacer and metal top cap |
| US9024431B2 (en) | 2009-10-29 | 2015-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die contact structure and method |
| US9190348B2 (en) | 2012-05-30 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scheme for connector site spacing and resulting structures |
| US9214428B2 (en) | 2009-09-01 | 2015-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned protection layer for copper post structure |
| US9287171B2 (en) | 2010-04-29 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a conductive pillar bump with non-metal sidewall protection structure |
| US9385076B2 (en) | 2011-12-07 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with bump structure on an interconncet structure |
| US9472521B2 (en) | 2012-05-30 | 2016-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scheme for connector site spacing and resulting structures |
| US9524945B2 (en) | 2010-05-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
| US9607936B2 (en) | 2009-10-29 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump joint structures with improved crack resistance |
| US9613914B2 (en) | 2011-12-07 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-passivation interconnect structure |
| CN112635433A (en)* | 2020-12-18 | 2021-04-09 | 中国电子科技集团公司第四十四研究所 | Indium column structure for large-area array hybrid focal plane and manufacturing method |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7749888B2 (en) | 2002-02-07 | 2010-07-06 | Nec Corporation | Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same |
| US7135770B2 (en) | 2002-02-07 | 2006-11-14 | Nec Corporation | Semiconductor element with conductive columnar projection and a semiconductor device with conductive columnar projection |
| US7268438B2 (en) | 2002-02-07 | 2007-09-11 | Nec Corporation | Semiconductor element including a wet prevention film |
| US7449406B2 (en) | 2002-02-07 | 2008-11-11 | Nec Corporation | Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same |
| US9147635B2 (en) | 2005-06-14 | 2015-09-29 | Cufer Asset Ltd. L.L.C. | Contact-based encapsulation |
| JP2008547207A (en)* | 2005-06-14 | 2008-12-25 | キュービック・ウエハ・インコーポレーテッド | Electronic chip contact structure |
| US9324629B2 (en) | 2005-06-14 | 2016-04-26 | Cufer Asset Ltd. L.L.C. | Tooling for coupling multiple electronic chips |
| US10340239B2 (en) | 2005-06-14 | 2019-07-02 | Cufer Asset Ltd. L.L.C | Tooling for coupling multiple electronic chips |
| US9754907B2 (en) | 2005-06-14 | 2017-09-05 | Cufer Asset Ltd. L.L.C. | Tooling for coupling multiple electronic chips |
| US8846445B2 (en) | 2005-06-14 | 2014-09-30 | Cufer Asset Ltd. L.L.C. | Inverse chip connector |
| JP2006332694A (en)* | 2006-07-24 | 2006-12-07 | Megic Corp | Method for forming metal bumps on semiconductor surface |
| JP2008277677A (en)* | 2007-05-07 | 2008-11-13 | Sony Corp | Semiconductor chip, and manufacturing method thereof |
| US8841766B2 (en) | 2009-07-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
| US9214428B2 (en) | 2009-09-01 | 2015-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned protection layer for copper post structure |
| US8569897B2 (en) | 2009-09-14 | 2013-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection layer for preventing UBM layer from chemical attack and oxidation |
| US8609526B2 (en) | 2009-10-20 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Preventing UBM oxidation in bump formation processes |
| US10163785B2 (en) | 2009-10-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die contact structure and method |
| US9607936B2 (en) | 2009-10-29 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump joint structures with improved crack resistance |
| US9536811B2 (en) | 2009-10-29 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die contact structure and method |
| US8847387B2 (en) | 2009-10-29 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust joint structure for flip-chip bonding |
| US11515272B2 (en) | 2009-10-29 | 2022-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die contact structure and method |
| US9024431B2 (en) | 2009-10-29 | 2015-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die contact structure and method |
| US8569887B2 (en) | 2009-11-05 | 2013-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post passivation interconnect with oxidation prevention layer |
| US8952534B2 (en) | 2010-02-09 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and semiconductor assembly with lead-free solder |
| US9136167B2 (en) | 2010-03-24 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a pillar structure having a non-metal sidewall protection structure |
| US11257714B2 (en) | 2010-03-24 | 2022-02-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same |
| US9287171B2 (en) | 2010-04-29 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a conductive pillar bump with non-metal sidewall protection structure |
| US10163837B2 (en) | 2010-05-18 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
| US9524945B2 (en) | 2010-05-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
| US9018758B2 (en) | 2010-06-02 | 2015-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall spacer and metal top cap |
| US9685372B2 (en) | 2010-06-02 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming Cu pillar bump with non-metal sidewall spacer and metal top cap |
| US9093314B2 (en) | 2010-06-11 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump structures having sidewall protection layers |
| US8922004B2 (en) | 2010-06-11 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump structures having sidewall protection layers |
| US9508666B2 (en) | 2011-05-30 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging structures and methods with a metal pillar |
| US8610285B2 (en) | 2011-05-30 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC packaging structures and methods with a metal pillar |
| US8901735B2 (en) | 2011-05-30 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connector design for packaging integrated circuits |
| US8664760B2 (en) | 2011-05-30 | 2014-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connector design for packaging integrated circuits |
| US8716858B2 (en) | 2011-06-24 | 2014-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure with barrier layer on post-passivation interconnect |
| US8581400B2 (en) | 2011-10-13 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-passivation interconnect structure |
| US9006891B2 (en) | 2011-10-13 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a semiconductor device having a post-passivation interconnect structure |
| US9385076B2 (en) | 2011-12-07 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with bump structure on an interconncet structure |
| US10121749B2 (en) | 2011-12-07 | 2018-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a post-passivation interconnect structure |
| US9613914B2 (en) | 2011-12-07 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-passivation interconnect structure |
| US9484317B2 (en) | 2012-05-30 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scheme for connector site spacing and resulting structures |
| US9472521B2 (en) | 2012-05-30 | 2016-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scheme for connector site spacing and resulting structures |
| US9190348B2 (en) | 2012-05-30 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scheme for connector site spacing and resulting structures |
| CN112635433A (en)* | 2020-12-18 | 2021-04-09 | 中国电子科技集团公司第四十四研究所 | Indium column structure for large-area array hybrid focal plane and manufacturing method |
| CN112635433B (en)* | 2020-12-18 | 2023-05-23 | 中国电子科技集团公司第四十四研究所 | Indium column structure for large area array hybrid focal plane and manufacturing method |
| Publication number | Publication date |
|---|---|
| JP3078646B2 (en) | 2000-08-21 |
| Publication | Publication Date | Title |
|---|---|---|
| JP3078646B2 (en) | Method for manufacturing indium bump | |
| US3952404A (en) | Beam lead formation method | |
| KR100264479B1 (en) | Bump Electrode Structure and Formation Method | |
| CN101728347B (en) | Package structure and manufacture method thereof | |
| US8901733B2 (en) | Reliable metal bumps on top of I/O pads after removal of test probe marks | |
| TW494557B (en) | Flip chip type semiconductor device and method of manufacturing the same | |
| US6528350B2 (en) | Method for fabricating a metal plated spring structure | |
| US20020005568A1 (en) | Semiconductor device and method for manufacturing | |
| US4032058A (en) | Beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads | |
| US6258705B1 (en) | Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip | |
| US20030073300A1 (en) | Method of forming a bump on a copper pad | |
| JP2001044357A (en) | Semiconductor device and method of manufacturing the same | |
| US7134199B2 (en) | Fluxless bumping process | |
| US5607877A (en) | Projection-electrode fabrication method | |
| US10134701B2 (en) | Solder bump for ball grid array | |
| US6767818B1 (en) | Method for forming electrically conductive bumps and devices formed | |
| US6319846B1 (en) | Method for removing solder bodies from a semiconductor wafer | |
| US20070273025A1 (en) | Device Comprising Circuit Elements Connected By Bonding Bump Structure | |
| JP2005057264A (en) | Packaged electric structure and its manufacturing method | |
| CN115566080A (en) | A kind of bump structure and preparation method thereof | |
| JPH08195397A (en) | Semiconductor device with bump and manufacturing method thereof | |
| JPH0638417B2 (en) | Semiconductor device | |
| JPH0629296A (en) | Bump pad-equipped semiconductor device | |
| JPH0590271A (en) | Bump forming method | |
| JPH01238044A (en) | Semiconductor device |