JPH05129473A - Resin-sealed surface-mounting semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the size and thickness of the title semiconductor device while a mechanism which prevents the deformation of external electrodes or fluctuation of the electrodes at the machining time is secured by using the rear sections of inner leads connected to internal wiring as external electrodes at the time of directly mounting the semiconductor device. CONSTITUTION:A semiconductor chip 1 is placed on the die pad 2 of a lead frame. After electrically connecting the chip 1 to inner leads 6, the rear of which become external electrodes 8, through bonding wires 3, the upper part is sealed with a resin. Similarly, the chip 1 is electrically connected to the leads through bumps 4. In other words, the rear of the electrically connected inner leads 6 are used as the electrical connecting sections 8 of the semiconductor device to the outside. Therefore, the size of the semiconductor device can be reduced to nearly the same size as that of the chip 1. In addition, the thickness of the semiconductor device can also be reduced.

Description

Translated fromJapanese

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は樹脂封止された表面実
装型半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed surface mount semiconductor device.

【０００２】[0002]

【従来の技術】従来、表面実装型半導体装置は図１０に
その一例の断面図で示すように、金属（例えば、４２％
Ｎｉ／Ｆｅ合金で、板厚０．１〜０．３ｍｍ）でできた
リードフレームのダイパッド２に半導体チップ１を搭載
し、図１０Ａに示すように、ボンディングワイヤ３によ
り内部導出リード６に電気的に接続するか、あるいは図
１０Ｂに示すように、バンプ４と呼ばれる接続電極によ
って直接内部導出リード６に電気的に接続する。そし
て、これらをエポキシ樹脂などの封止材５で封止した
後、外部導出リード７および外部電極８を所要の形状に
曲げ形成している。2. Description of the Related Art Conventionally, a surface mount type semiconductor device has a metal (for example, 42%) as shown in a sectional view of an example in FIG.
A semiconductor chip 1 is mounted on a die pad 2 of a lead frame made of a Ni / Fe alloy and having a plate thickness of 0.1 to 0.3 mm, and electrically connected to an internal lead 6 by a bonding wire 3 as shown in FIG. 10A. 10B, or as shown in FIG. 10B, it is electrically connected directly to the internal lead-out lead 6 by a connection electrode called a bump 4. Then, after encapsulating these with an encapsulating material 5 such as an epoxy resin, the external lead 7 and the external electrode 8 are formed into a desired shape by bending.

【０００３】そして、図１１Ａに側面図で示すように、
基板１２のパターンに半田ペースト１３を、あるいは図
１１Ｂに示すように、基板１２に接着剤１４を塗布して
おき、これに表面実装型半導体装置を位置合わせして載
せる。この基板１２を、図１１Ａのように半田ペースト
１３を使用した場合には、熱風あるいは赤外線などによ
り加熱し半田付けする。一方、図１１Ｂのように接着剤
１４を使用した場合には、半田槽に浸漬して半田付けを
行う。Then, as shown in the side view of FIG. 11A,
Solder paste 13 is applied to the pattern of the substrate 12, or adhesive 14 is applied to the substrate 12 as shown in FIG. 11B, and the surface-mounted semiconductor device is aligned and placed on this. When the solder paste 13 is used as shown in FIG. 11A, the substrate 12 is heated and soldered by hot air or infrared rays. On the other hand, when the adhesive 14 is used as shown in FIG. 11B, it is dipped in a solder bath and soldered.

【０００４】しかしながら、前述した表面実装型半導体
装置は、図１０Ａ、Ｂに示す封止材５の外側において、
外部導出リード７および外部電極８を曲げ加工している
ため、この加工精度のバラツキおよび成形後の外部から
の力により、図１２Ａの斜視図に示すように、半導体装
置の封止材５の底面に対する外部電極８の下面の高さ方
向の位置のバラツキおよび図１２Ｂの平面図に示すよう
に、横方向への外部導出リード７および外部電極８の変
形が生じやすい。これらが原因となって前述の基板実装
時、好適な表面実装ができなくなる。または、電気的に
導通できなくなるという課題が発生した。However, the above-mentioned surface mount semiconductor device has the following problem with the outside of the sealing material 5 shown in FIGS. 10A and 10B.
Since the external lead 7 and the external electrode 8 are bent, the bottom surface of the encapsulating material 5 of the semiconductor device is, as shown in the perspective view of FIG. 12A, due to the variation in the processing accuracy and the external force after molding. As shown in the plan view of FIG. 12B and the variation in the height direction of the lower surface of the external electrode 8 with respect to, the external lead 7 and the external electrode 8 are easily deformed in the lateral direction. Due to these factors, suitable surface mounting cannot be performed during the above-mentioned board mounting. Alternatively, there has been a problem that electrical connection cannot be established.

【０００５】そこで、この課題を解消するため、図１３
に示した特開平３−３３５４号公報に開示されている半
導体装置のように、外部電極８を封止材５の底面と同一
面で、かつ底面と並行に導出した形状が提案されてい
る。Therefore, in order to solve this problem, FIG.
As in the semiconductor device disclosed in Japanese Unexamined Patent Publication No. 3-3354 shown in FIG. 1, there is proposed a shape in which the external electrode 8 is led out on the same surface as the bottom surface of the sealing material 5 and in parallel with the bottom surface.

【０００６】[0006]

【発明が解決しようとする課題】ところで、近年、電子
機器が小型化、薄型化されるにしたっがって、使用され
る半導体装置もできるだけ小型化、薄型化をはかるよう
に要求され、現在では封止材の大きさが内部に搭載され
ている半導体チップの大きさと近くなってきており、ま
た、厚みも１．０ｍｍ以下の薄型半導体装置が実用化さ
れてきている。しかし、このような小型、薄型半導体装
置において、前述の図１３に示す特開平３−３３５４号
公報に記載されているような形状では、大きさも半導体
チップサイズよりはるかに大きくなってしまうばかり
か、厚さも厚くなってしまうという課題が発生した。こ
の発明は、外部電極の変形あるいは加工時のバラツキを
防止する機構を保ちながら、しかも、小型化、薄型化可
能な樹脂封止表面実装型半導体装置を提供することを目
的とする。By the way, in recent years, as electronic devices have become smaller and thinner, it has been demanded that semiconductor devices used be as small and thin as possible. The size of the encapsulating material has become close to the size of the semiconductor chip mounted inside, and a thin semiconductor device having a thickness of 1.0 mm or less has been put into practical use. However, in such a small and thin semiconductor device, the shape as described in Japanese Patent Laid-Open No. 3-3354 shown in FIG. 13 not only makes the size much larger than the semiconductor chip size, There was a problem that the thickness also increased. It is an object of the present invention to provide a resin-sealed surface-mounted semiconductor device that can be downsized and thinned while maintaining a mechanism for preventing deformation of external electrodes or variation during processing.

【０００７】[0007]

【課題を解決するための手段】先に述べたような課題を
解決するために、この発明は、内部導出リードとダイパ
ッドが同一平面にあるリードフレームを用い、半導体チ
ップとボンディングワイヤあるいはバンプにより電気的
に接続される内部導出リードの裏面を、半導体装置の外
部との電気的接続部分すなわち外部電極とした。In order to solve the above-mentioned problems, the present invention uses a lead frame in which the internal lead-out lead and the die pad are on the same plane, and uses a semiconductor chip and a bonding wire or a bump for electrical connection. The back surfaces of the internal lead-out leads that are electrically connected to each other are used as electrical connection portions with the outside of the semiconductor device, that is, external electrodes.

【０００８】[0008]

【作用】したがってこの発明の樹脂封止表面実装型半導
体装置は、内部導出リードとダイパッドが同一平面にあ
るリードフレームを用い、半導体チップとボンディング
ワイヤあるいはバンプにより電気的に接続される内部導
出リードの裏面を半導体装置の外部との電気的接続部分
すなわち外部電極としたので、半導体装置の大きさを半
導体チップの大きさとほぼ同じ大きさまで小さくするこ
とができる。また、半導体装置の厚みを薄くすることが
できる。Therefore, the resin-sealed surface-mount type semiconductor device of the present invention uses the lead frame in which the internal lead and the die pad are on the same plane, and the internal lead is electrically connected to the semiconductor chip by the bonding wire or the bump. Since the back surface serves as an electrical connection portion to the outside of the semiconductor device, that is, an external electrode, the size of the semiconductor device can be reduced to almost the same size as the size of the semiconductor chip. Moreover, the thickness of the semiconductor device can be reduced.

【０００９】[0009]

【実施例】以下、この発明の実施例の樹脂封止表面実装
型半導体装置を図面とともに詳述する。図１に第１の実
施例の断面図を示す。まず、図１Ａは、厚さ０．１〜
０．３ｍｍのリードフレームのダイパッド２に半導体チ
ップ１を載置し、半導体チップ１と裏面が外部電極８と
なる内部導出リード６とをボンディングワイヤ３で電気
的に接続させて、その上部を樹脂封止した構造となって
いる。図１Ｂは、同様に半導体チップ１と内部導出リー
ド６とをバンプ４で電気的に接続をさせている例を示
す。ボンディングワイヤ３による電気的接続法よりバン
プ４による電気的接続の方が、その構造上封止材５の大
きさをさらに小さくできるという利点があるが、リード
フレームの板厚が薄いほど半導体チップ１の下面の樹脂
の厚みも薄くなるため、樹脂封止時のボイド（気泡）な
どの不具合が発生しやすくなる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A resin-sealed surface mount type semiconductor device according to an embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a sectional view of the first embodiment. First, FIG.
The semiconductor chip 1 is placed on the die pad 2 of the lead frame of 0.3 mm, the semiconductor chip 1 and the internal lead-out 6 having the back surface serving as the external electrode 8 are electrically connected by the bonding wire 3, and the upper portion thereof is made of resin. It has a sealed structure. FIG. 1B shows an example in which the semiconductor chip 1 and the internal lead-out 6 are similarly electrically connected by the bump 4. The electrical connection using the bumps 4 has an advantage that the size of the sealing material 5 can be further reduced because of its structure, as compared with the electrical connection method using the bonding wires 3. However, the thinner the lead frame is, the smaller the semiconductor chip 1 is. Since the thickness of the resin on the lower surface of the resin is also thin, defects such as voids (air bubbles) during resin sealing are likely to occur.

【００１０】第１の実施例の半導体装置の作成方法を図
２、図３の断面図を用いて簡単に説明する。まず、第１
の作成方法を図２の断面図で説明する。図２Ａに示すよ
うに、従来と同様の方法でダイパッド２と内部導出リー
ド６が同一平面上にあるリードフレームを用い、半導体
チップ１を載置後その半導体チップ１と内部導出リード
６とをボンディングワイヤ３により電気的に接続を行
う。つぎに、エポキシ樹脂などの封止材５を用いて封止
する。そして、半導体装置の裏面樹脂部を削り取り図２
Ｂに示す形状にする。その後、基板実装を行う際の半田
付け性をよくするために、外部電極８の露出した部分に
半田などの外装メッキ９を施すことにより図２Ｃのよう
になる。こうしてできた半導体装置の外部導出リード７
の外側の余分な部分を金型などを用いて切断すると図２
Ｄに示す本実施例の半導体装置が得られる。つぎに、第
２の作成方法を図３の断面図で説明する。第１の作成方
法と同様に、半導体チップ１を載置して電気的に接続し
た後、上面にのみキャビティ（堀り混み）のある金型で
樹脂封止を行うことにより、図３Ａに示す形状となる。
この後、第１の作成方法と同様に、外装メッキ９および
外部導出リード７の切断を行うことにより、図３Ｂに示
す本実施例の半導体装置が得られる。この作成方法の場
合、樹脂封止時のバリなどが外装メッキ９を施そうとし
ている部分に付着していることがあるため、外装メッキ
９を施す前に高圧水などによるバリ取りという前処理が
必要となるが、第１の作成方法のような硬い封止樹脂を
削り取るという作業は省略できる。A method of manufacturing the semiconductor device of the first embodiment will be briefly described with reference to the sectional views of FIGS. First, the first
A method of making the above will be described with reference to the sectional view of FIG. As shown in FIG. 2A, a lead frame in which the die pad 2 and the internal lead 6 are on the same plane is used in the same manner as the conventional method, and after mounting the semiconductor chip 1, the semiconductor chip 1 and the internal lead 6 are bonded. Electrical connection is made by the wire 3. Next, sealing is performed using a sealing material 5 such as epoxy resin. Then, the resin portion on the back surface of the semiconductor device is scraped off and shown in FIG.
The shape shown in B is used. Then, in order to improve solderability when mounting on a substrate, exterior plating 9 such as solder is applied to the exposed portions of the external electrodes 8 to obtain a state as shown in FIG. 2C. External lead 7 of the semiconductor device thus formed
When the extra part of the outside of the is cut using a mold etc.,
The semiconductor device of this embodiment shown in D is obtained. Next, the second manufacturing method will be described with reference to the sectional view of FIG. Similar to the first manufacturing method, the semiconductor chip 1 is placed and electrically connected to each other, and then resin sealing is performed with a mold having a cavity (dense crowd) only on the upper surface, as shown in FIG. 3A. It becomes a shape.
Thereafter, similarly to the first manufacturing method, the exterior plating 9 and the external lead 7 are cut to obtain the semiconductor device of this embodiment shown in FIG. 3B. In the case of this preparation method, since burrs or the like at the time of resin sealing may be attached to the portion where the exterior plating 9 is to be applied, a pretreatment such as deburring with high pressure water or the like is required before applying the exterior plating 9. Although necessary, the work of scraping off the hard sealing resin as in the first manufacturing method can be omitted.

【００１１】図４に第２の実施例の断面図を示す。構造
的には第１の実施３例とほどんど変わらないが、半導体
チップを載置するダイパッド２および外部電極８の厚み
が銅箔などの非常に薄い（約１０〜３０μｍ）導体で構
成されている。本実施例の構造は第１の実施例に比べ半
導体装置の厚みを数百μｍも薄くすることが可能とな
る。また、半導体チップ１の裏面が、直接あるいは金属
部分を介して外部に露出している構造となっているの
で、基板実装後、使用時に半導体装置から発生する熱を
逃がしやすいという利点もある。この第２の実施例の半
導体装置の作成方法を図５の断面図を用いて簡単に説明
する。前述した第１の実施例では、リードフレームを使
用するが、本実施例では図５Ａに示すような部分的に穴
の開いたポリイミドなどのフィルム１０に銅箔などの薄
い導体をラミネートしてダイパッド２、内部導出リード
６および外部配線１１を形成し、この導体付いたフィル
ム１０に、前述の方法と同様に半導体チップ１を載置し
て電気的に接続を行い、樹脂封止および外装メッキ９を
施すと図５Ｂにその断面図を示す構造になる。さらに、
加熱などを施しながらフィルム１０を剥離すると図５Ｃ
に示すような本実施例の構造となる。なお、本実施例に
用いられる外部電極８の外側に、フィルム１０を剥離す
る際に導体の余分な部分が同時に切断してしまうよう
に、図５Ｄの平面図に示したように外部電極に接続され
る外部配線１１をあらかじめ細くしておくとよい。FIG. 4 shows a sectional view of the second embodiment. Although the structure is almost the same as that of the first embodiment, the thickness of the die pad 2 on which the semiconductor chip is mounted and the external electrode 8 is made of a very thin (about 10 to 30 μm) conductor such as copper foil. There is. With the structure of this embodiment, it is possible to reduce the thickness of the semiconductor device by several hundreds of μm as compared with the first embodiment. Further, since the back surface of the semiconductor chip 1 is exposed to the outside directly or through the metal part, there is an advantage that heat generated from the semiconductor device can be easily released during use after mounting on the substrate. A method of manufacturing the semiconductor device according to the second embodiment will be briefly described with reference to the sectional view of FIG. In the first embodiment described above, a lead frame is used, but in this embodiment, a die pad is formed by laminating a thin conductor such as copper foil on a film 10 such as polyimide having partially holes as shown in FIG. 5A. 2, the internal lead 6 and the external wiring 11 are formed, and the semiconductor chip 1 is mounted on the film 10 with the conductor and electrically connected in the same manner as the above-described method, and the resin sealing and the exterior plating 9 The resulting structure is shown in FIG. 5B. further,
When the film 10 is peeled off while applying heat or the like, FIG.
The structure of this embodiment is as shown in FIG. It should be noted that the external electrode 8 used in this example is connected to the external electrode as shown in the plan view of FIG. 5D so that the excess portion of the conductor is cut off at the same time when the film 10 is peeled off. The external wiring 11 to be formed may be thinned in advance.

【００１２】図６に第３の実施例の断面図を示す。第３
の実施例では半導体チップ１を載置するダイパッド２の
下にポリイミドなどのフィルム１０を有する。その外に
は前述してきた実施例と変わるところはないが、本実施
例の場合、基板実装時の接続部分となる外部電極８の底
面の高さに対し、外部電極８の厚さの分だけ高いところ
にフィルム１０があるため、基板実装後のフラックスの
洗浄効果があるという利点がある。また、半導体装置の
中央に半導体チップ１の裏面と電気的に接続される部分
がないので、基板実装時に発生するショートなどの不具
合をまねかないという利点もある。なお、本実施例では
ダイパッド２が存在する図で説明してきたが、実施に際
しては必ずしも必要とは限らない。第３の実施例の半導
体装置の作成方法を図７の断面図を用いて簡単に説明す
る。第３の実施例では、図７Ａに示すような部分的に穴
の開いたポリイミドなどのフィルム１０に銅箔などの薄
い導体をラミネートしてダイパッド２、内部導出リード
６および外部配線１１を形成し、この導体の付いたフィ
ルム１０に、前述の方法と同様に半導体チップ１を載置
して電気的に接続を行い、樹脂封止および外装メッキ９
を施すと図７Ｂにその断面を示す構造になる。さらに、
加熱などを施しながら半導体装置周辺のフィルム１０を
剥離すると図７Ｃに示すような本実施例の構造となる。
なお、第２の実施例と同様に外部電極８の外側の外部配
線１１を、フィルム１０を剥離する際、切断しやすいよ
うにあらかじめ細くしておくとよい。FIG. 6 shows a sectional view of the third embodiment. Third
In this embodiment, a film 10 made of polyimide or the like is provided under the die pad 2 on which the semiconductor chip 1 is placed. Other than that, there is no difference from the embodiment described above, but in the case of this embodiment, the height of the bottom surface of the external electrode 8 which is the connecting portion at the time of mounting on the substrate is equal to the thickness of the external electrode 8. Since the film 10 is located at a high place, there is an advantage that there is a cleaning effect of the flux after mounting on the board. In addition, since there is no portion electrically connected to the back surface of the semiconductor chip 1 in the center of the semiconductor device, there is an advantage that a defect such as a short circuit that occurs when mounting on a substrate is not caused. Although the present embodiment has been described with reference to the figure in which the die pad 2 is present, it is not always necessary for implementation. A method of manufacturing the semiconductor device of the third embodiment will be briefly described with reference to the sectional view of FIG. In the third embodiment, the die pad 2, the internal lead 6 and the external wiring 11 are formed by laminating a thin conductor such as a copper foil on a film 10 such as polyimide having a partial hole as shown in FIG. 7A. The semiconductor chip 1 is placed on the film 10 with the conductor in the same manner as in the above-described method to make electrical connection, and the resin sealing and the exterior plating 9
Is applied, a structure whose cross section is shown in FIG. 7B is obtained. further,
When the film 10 around the semiconductor device is peeled off while heating or the like, the structure of this embodiment is obtained as shown in FIG. 7C.
Note that, similarly to the second embodiment, the external wiring 11 outside the external electrode 8 may be thinned in advance so that it can be easily cut when the film 10 is peeled off.

【００１３】さらに、第４および第５の実施例として、
図８に断面図を示すように、外部電極８を２重に配置し
た構造も、前述してきた実施例より容易に作成される。
本実施例の構造の場合、前述の実施例より半導体装置の
大きさは少し大きくなるが、外部電極８同士の間隔が広
くできるために基板実装時の半田によるブリッジ（電極
間ショート）が発生しにくいという利点がある。Further, as the fourth and fifth embodiments,
As shown in the sectional view of FIG. 8, the structure in which the external electrodes 8 are doubly arranged is also easier to manufacture than the above-described embodiment.
In the case of the structure of this embodiment, the size of the semiconductor device is slightly larger than that of the above-mentioned embodiment, but since the distance between the external electrodes 8 can be widened, a bridge (short-circuit between electrodes) due to solder when mounting on a substrate occurs. It has the advantage of being difficult.

【００１４】また、第６の実施例として図６の断面図に
示した第３の実施例において、完成した半導体装置の中
央部にあるフィルム１０を除去することにより、図９に
断面図に示すように、半導体チップ１の裏面部あるいは
封止材５以外の樹脂材料を介した面が、外部電極８の下
面よりさらに高くできるので、第３の実施例のところで
述べた地盤実装時の洗浄効果がよりあがるという利点が
ある。Further, in the third embodiment shown in the sectional view of FIG. 6 as the sixth embodiment, the film 10 in the central portion of the completed semiconductor device is removed to show the sectional view in FIG. As described above, since the back surface of the semiconductor chip 1 or the surface of the semiconductor chip 1 other than the sealing material 5 via the resin material can be made higher than the lower surface of the external electrode 8, the cleaning effect at the time of ground mounting described in the third embodiment. Has the advantage that

【００１５】[0015]

【発明の効果】以上の説明から明らかなように、この発
明の半導体装置では内部導出リードの接続点の裏面を半
導体装置の外部電極としたので、半導体チップの大きさ
に近い寸法の半導体装置を提供できる。また、厚みに関
しても、約０．５ｍｍ前後の厚みの半導体装置を提供で
きる。As is apparent from the above description, in the semiconductor device of the present invention, the back surface of the connection point of the internal lead-out is the external electrode of the semiconductor device. Can be provided. Further, regarding the thickness, it is possible to provide a semiconductor device having a thickness of about 0.5 mm.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明の第１の実施例の断面図。FIG. 1 is a sectional view of a first embodiment of the present invention.

【図２】第１の実施例の半導体装置の第１の作成方法を
説明する断面図。2A and 2B are cross-sectional views illustrating a first manufacturing method of the semiconductor device of the first embodiment.

【図３】第１の実施例の半導体装置の第２の作成方法を
説明する断面図。3A and 3B are cross-sectional views illustrating a second manufacturing method of the semiconductor device of the first embodiment.

【図４】この発明の第２の実施例の断面図。FIG. 4 is a sectional view of the second embodiment of the present invention.

【図５】第２の実施例の半導体装置の作成方法を説明す
る断面図。5A and 5B are cross-sectional views illustrating a method for manufacturing a semiconductor device of a second embodiment.

【図６】この発明の第３の実施例の断面図。FIG. 6 is a sectional view of a third embodiment of the present invention.

【図７】第３の実施例の半導体装置の作成方法を説明す
る断面図。7A and 7B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment.

【図８】この発明の第４および第５の実施例の断面図
で、Ａは第４の実施例、Ｂは第５の実施例である。FIG. 8 is a sectional view of the fourth and fifth embodiments of the present invention, where A is the fourth embodiment and B is the fifth embodiment.

【図９】この発明の第６の実施例の断面図。FIG. 9 is a sectional view of a sixth embodiment of the present invention.

【図１０】従来例の表面実装型半導体装置の断面図。FIG. 10 is a cross-sectional view of a conventional surface mount semiconductor device.

【図１１】従来例の表面実装型半導体装置を基板に実装
した状態の断面図。FIG. 11 is a cross-sectional view of a conventional surface mount semiconductor device mounted on a substrate.

【図１２】従来例の表面実装型半導体装置の外部導出リ
ードの変形状態を示した説明図で、Ａは斜視図、Ｂは平
面図である。12A and 12B are explanatory views showing a deformed state of an external lead-out of a conventional surface mount semiconductor device, wherein A is a perspective view and B is a plan view.

【図１３】従来例の表面実装型半導体装置の断面図であ
る。FIG. 13 is a cross-sectional view of a conventional surface mount semiconductor device.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ ダイパッド ３ ボンディングワイヤ ４ バンプ ５ 封止材 ６ 内部導出リード ７ 外部導出リード ８ 外部電極 ９ 外装メッキ １０ フィルム １１ 外部配線 1 Semiconductor Chip 2 Die Pad 3 Bonding Wire 4 Bump 5 Sealant 6 Internal Lead-out 7 External Lead-out 8 External Electrode 9 Exterior Plating 10 Film 11 External Wiring

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.⁵ 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/50 Ｇ 9272−4Ｍ Ｒ 9272−4Ｍ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl.⁵ Identification code Internal reference number FI Technical display location H01L 23/50 G 9272-4M R 9272-4M

Claims (3)

Translated fromJapanese

【特許請求の範囲】[Claims]【請求項１】 半導体素子を搭載し、その素子表面の電
極を内部導出リードに配線し、その配線部および前記半
導体素子部を樹脂封止してなる樹脂封止表面実装型半導
体装置において、 前記内部配線の接続される内部導出リードの裏面部が、
直接半導体装置を実装する際の外部電極となることを特
徴とする樹脂封止表面実装型半導体装置。1. A resin-sealed surface-mount type semiconductor device comprising a semiconductor element, electrodes on the element surface thereof being wired to internal leads, and the wiring part and the semiconductor element part being resin-sealed, The back surface of the internal lead wire to which the internal wiring is connected
A resin-sealed surface-mount type semiconductor device, which serves as an external electrode when directly mounting a semiconductor device.【請求項２】 半導体素子の裏面が直接あるいは封止樹
脂以外の樹脂材料を介して、半導体装置の外側に露出し
ていることを特徴とする請求項１記載の樹脂封止表面実
装型半導体装置。2. The resin-sealed surface-mount type semiconductor device according to claim 1, wherein the back surface of the semiconductor element is exposed to the outside of the semiconductor device directly or through a resin material other than the sealing resin. ..【請求項３】 半導体素子の裏面部あるいは封止樹脂以
外の樹脂材料を介した面が、外部電極の面よりも一段高
く形成されていることを特徴とする請求項１記載の樹脂
封止表面実装型半導体装置。3. The resin-sealed surface according to claim 1, wherein the back surface of the semiconductor element or the surface through which a resin material other than the sealing resin is interposed is formed higher than the surface of the external electrode. Mounted semiconductor device.