【発明の詳細な説明】〔産業上の利用分野〕 この発明は太陽電池等の光電変換半導体装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to photoelectric conversion semiconductor devices such as solar cells.
第２図は例えば第16回IEEE Photovltaic
Specialists Conf，のダイジエストのp692に示さ
れた従来の光電変換半導体装置を示す断面図であ
り、図において、１はｎ形シリコン基板（以下ｎ
−Si基板と略記）、２はｎ−Si基板１上に形成さ
れたｐ形シリコン層（以下ｐ−Si層と略記）、３
はｐ−Si層２上に形成されたゲルマニウム層（以
下Ge層と略記）、４はGe層３上に形成されたｎ
形砒化がリウム層（以下ｎ−GaAs層と略記）、
５はｎ−GaAs層４上に形成されたｐ形砒化ガリ
ウム層（以下ｐ−GaAs層と略記）、６はｐ−
GaAs層５上に形成された膜厚600〜800Åの窒化
シリコン膜７，８はそれぞれｐ−GaAs層５、ｎ
−Si基板１にオーミツク接続された電極である。 Figure 2 is an example of the 16th IEEE Photovltaic.
1 is a sectional view showing a conventional photoelectric conversion semiconductor device shown on page 692 of Digest of Specialists Conf. In the figure, 1 is an n-type silicon substrate (hereinafter referred to as n
-Si substrate), 2 is a p-type silicon layer formed on the n-Si substrate 1 (hereinafter abbreviated as p-Si layer), 3
4 is a germanium layer (hereinafter abbreviated as Ge layer) formed on the p-Si layer 2, and 4 is an n layer formed on the Ge layer 3.
The arsenide layer is a lium layer (hereinafter abbreviated as n-GaAs layer),
5 is a p-type gallium arsenide layer (hereinafter abbreviated as p-GaAs layer) formed on the n-GaAs layer 4, and 6 is a p-type gallium arsenide layer (hereinafter abbreviated as p-GaAs layer).
Silicon nitride films 7 and 8 with a film thickness of 600 to 800 Å formed on the GaAs layer 5 are p-GaAs layers 5 and n-GaAs layers 5 and 8, respectively.
- It is an electrode that is ohmicly connected to the Si substrate 1.
従来の光電変換半導体装置は上記のように構成
され、第２図紙面上から入射した太陽光等が比較
的短波長成分がｎ−GaAs層４とｐ−GaAs層５
間で長波長成分が、ｎ−Si基板１とｐ−Si層２間
で、それぞれ光電変換された光電流はGe層３を
経て、電極７，８から取り出すようになつてい
る。 A conventional photoelectric conversion semiconductor device is constructed as described above, and sunlight, etc. that enter from the top of the page in FIG.
The long wavelength component is photoelectrically converted between the n-Si substrate 1 and the p-Si layer 2, and the photocurrent is extracted from the electrodes 7 and 8 via the Ge layer 3.
上記のような従来の光電変換装置では、ｐ−Si
層２上に直接、ｎ−GaAs層４を形成したのでは
結晶性の良いものが得られないため、これらの間
に緩衝層として、Ge層３が用いられているが、
その禁制帯幅がシリコンより狭く、（Ge、Siそれ
ぞれの禁制帯幅は0.66eV、1.11eV）ｎ−Si基板
１とｐ−Si層２のダイオードが変換しうる波長領
域の光を遮断するので、このダイオードの光電変
換が行われないという問題点があつた。 In the conventional photoelectric conversion device as described above, p-Si
If the n-GaAs layer 4 is formed directly on the layer 2, good crystallinity cannot be obtained, so the Ge layer 3 is used as a buffer layer between them.
Its forbidden band width is narrower than that of silicon (the forbidden band widths of Ge and Si are 0.66 eV and 1.11 eV, respectively), and the diodes in the n-Si substrate 1 and p-Si layer 2 block light in the wavelength range that can be converted. However, there was a problem in that the photoelectric conversion of this diode was not performed.
なお、上記のGe層３はｐ−Si層２上に蒸着等
によりアモルフアス状の膜として領域されるが、
レーザアニール等の再結晶化技術により極めて結
晶性の良いものが得られ、さらに、格子定数がほ
とんど等しいことからこの上に形成されるｎ−
GaAs層４の結晶性を良好なものにする。 Note that the above Ge layer 3 is formed as an amorphous film on the p-Si layer 2 by vapor deposition, etc.
By recrystallization techniques such as laser annealing, crystals with extremely good crystallinity can be obtained, and furthermore, since the lattice constants are almost the same, the n-
The crystallinity of the GaAs layer 4 is improved.
この発明はかゝる問題点を解決するためになさ
れたもので、ｎ−GaAs層４等の結晶性を良くす
るということを満たすと共に必要な波長域の透過
性の高い緩衝層を用いてより総合効率の高い光電
変換半導体装置を得ることを目的としている。 This invention was made to solve these problems, and it satisfies the need to improve the crystallinity of the n-GaAs layer 4, etc., and uses a buffer layer that is highly transparent in the necessary wavelength range. The aim is to obtain a photoelectric conversion semiconductor device with high overall efficiency.
この発明に係る光電変換半導体装置はpn接合
を有するシリコン領域とpn接合を有し、ガリウ
ムと砒素を含む族化合物半導体領域との間に
セレン化亜鉛層を挿入し、両領域より光電流を取
り出す複数の電極を設けたものである。 A photoelectric conversion semiconductor device according to the present invention includes a silicon region having a pn junction and a zinc selenide layer having a pn junction and a group compound semiconductor region containing gallium and arsenic, and extracts a photocurrent from both regions. It is equipped with multiple electrodes.
この発明においてはセレン化亜鉛層は、シリコ
ン領域のpn接合が光電変換する光の波長域を良
く透過させるのと同時に、その上に形成されるガ
リウムと砒素を含む族化合物半導体の比較的
完全に近い結晶を得ることを可能にするので、こ
の装置の総合的な光電変換効率を向上させる。 In this invention, the zinc selenide layer allows the pn junction in the silicon region to transmit the wavelength range of light that is photoelectrically converted, and at the same time, the zinc selenide layer allows the gallium and arsenic group compound semiconductor formed thereon to be relatively completely transmitted. It makes it possible to obtain close crystals, thus improving the overall photoelectric conversion efficiency of this device.
第１図はこの発明の一実施例を示す断面図であ
り、１は基板であつてこの実施例ではｎ−Si基
板、２はｎ−Si基板１に例えばボロン拡散により
形成されたｐ−Si層、３Ａはｐ−Si層２上に分子
線エピタキシヤル法によつて堆積したのち、高圧
下においてレーザアニールし再結晶化した膜厚
0.1〜数μｍのセレン化亜鉛層（以下、ZnSe層と
略記）、４はZnSe層３Ａ上に気相エピタキシヤル
成長法あるいは液相エピタキシヤル成長法によつ
て形成されシリコン、あるいはセレン、硫黄テル
ルなどの族元素がドープされたｎ−GaAs層
（ZnSeの格子定数５，667オングストロームに
GaAsの格子定数が5.65オングストロームと近い
ため、このGaAs層の結晶性の良いものが得られ
る）、５はｎ−GaAs層４上にこれと同様の成長
法によつて形成され、亜鉛、ベリリウムマグネシ
ウムなどの族元素がドープされたｐ−GaAs
層、６はｐ−GaAs層５上にプラズマ気相成長法
等で形成され、必要な個所の穴明けが写真製版法
により行われた反射防止用の窒化シリコン膜、
７，８はそれぞれｐ−GaAs層５、ｎ−Si基板１
にオーミツク接触となる電極、９はシリコン領域
であつて、この実施例ではｎ−Si基板１とｐ−Si
層２とで構成されるもの、１０はガリウムと砒素
を含む族化合物半導体領域であつて、この実
施例はｎ−GaAs層４とｐ−GaAs層５とで構成
されるものである。 FIG. 1 is a cross-sectional view showing one embodiment of the present invention, in which 1 is a substrate, which is an n-Si substrate in this embodiment, and 2 is a p-Si substrate formed on the n-Si substrate 1 by, for example, boron diffusion. Layer 3A was deposited on p-Si layer 2 by molecular beam epitaxial method, then laser annealed under high pressure and recrystallized.
A zinc selenide layer (hereinafter abbreviated as ZnSe layer) of 0.1 to several μm, 4 is formed on the ZnSe layer 3A by vapor phase epitaxial growth method or liquid phase epitaxial growth method, and is made of silicon, selenium, sulfur tellurium. n-GaAs layer doped with group elements such as (ZnSe lattice constant 5,667 angstroms)
Since the lattice constant of GaAs is close to 5.65 angstroms, this GaAs layer has good crystallinity), 5 is formed on the n-GaAs layer 4 by a similar growth method, and contains zinc, beryllium magnesium p-GaAs doped with group elements such as
The layer 6 is a silicon nitride film for antireflection, which is formed on the p-GaAs layer 5 by a plasma vapor deposition method or the like, and holes are formed at necessary locations by a photolithography method.
7 and 8 are p-GaAs layer 5 and n-Si substrate 1, respectively.
The electrode 9 is a silicon region which is in ohmic contact with the n-Si substrate 1 and the p-Si substrate in this embodiment.
10 is a group compound semiconductor region containing gallium and arsenic, and in this embodiment is composed of an n-GaAs layer 4 and a p-GaAs layer 5.
この実施例の光電変換半導体装置は上記のよう
に達成したので第１図紙面上方から太陽光等の光
を照射すると、従来のものと同様にまずｎ−
GaAs層４とｐ−GaAs層５で構成されるpn接合
で比較的短波長域の光が吸収され電気に変換さ
れ、次にｎ−Si基板１とｐ−Si層２で構成される
ｐ−ｎ接合で前のGaAs層４，５、及びZnSe層３
Ａを透過した比較的長波長域の光が光電変換さ
れ、ZnSe層３Ａを経て、電極７，８から光電流
が取り出される。前述の従来のものではGe層３
がSi部分１，２が必要とする波長域の光を完全に
遮蔽してしまつたがこの実施例のZnSe層３Ａは、
その禁制帯幅が2.67eVとSiより大であるため問
題の波長域では透明であり、従つて、従来のもの
の如き欠点が解消されていることがわかる。 Since the photoelectric conversion semiconductor device of this example achieved the above-mentioned results, when light such as sunlight is irradiated from above the page of FIG.
Light in a relatively short wavelength range is absorbed by the p-n junction composed of the GaAs layer 4 and the p-GaAs layer 5 and converted into electricity, and then the p-n junction composed of the n-Si substrate 1 and the p-Si layer 2 GaAs layers 4, 5 and ZnSe layer 3 in front of n-junction
Light in a relatively long wavelength range that has passed through A is photoelectrically converted, and a photocurrent is extracted from electrodes 7 and 8 via ZnSe layer 3A. In the conventional method mentioned above, Ge layer 3
However, the ZnSe layer 3A of this example completely blocks the light in the required wavelength range by the Si parts 1 and 2.
Since its forbidden band width is 2.67 eV, which is larger than that of Si, it is transparent in the wavelength range of interest, and therefore, it can be seen that the drawbacks of conventional products have been eliminated.
また、従来のものと比べるとGaAs層４，５
が、ZnSe層３Ａ上に成長させられている点が異
なるが、これも上記の如くGaAs層４，５の結晶
性が良好なため従来のものに比して、このGaAs
部分の変換効率がほゞ同等になる。 Also, compared to the conventional one, the GaAs layers 4, 5
The difference is that it is grown on the ZnSe layer 3A, but this is also due to the good crystallinity of the GaAs layers 4 and 5, as described above, compared to the conventional one.
The conversion efficiency of the parts becomes almost the same.
以上のことをひつくるめてこの実施例の総合効
率は従来のものに比して高くなると云える。 Summarizing the above, it can be said that the overall efficiency of this embodiment is higher than that of the conventional one.
なお、上記実施例では、族化合物半導体領
域１０がGaAsである場合について述べたが、
GaAsとAlAsの任意の比率の混晶（AlxGa1-X
As、と書く。但し０＜Ｘ＜１ AlAsとGaAsの
比が、Ｘ＝１−Ｘであることを示す）としても、
ZnSe層３Ａ上に良好な結晶を形成できるのでこ
れに代替させてもよい。さらに第３図に示す如く
複数のAlxGa1-XAs領域１０Ａ，１０Ｂ，１０Ｃ
を、下から上に行くなどAlの組成比を大になる
ように形成し、それぞれの中に下から上へ、ｎ−
AlxGa1-XAs層４Ａ，４Ｂ，４Ｃ ｐ−
AlxGa1-XAs層５Ａ，５Ｂ，５Ｃとしてもよい。 Note that in the above embodiment, the case where the group compound semiconductor region 10 is made of GaAs is described;
Mixed crystal of any ratio of GaAs and AlAs (AlxGa1-X
Write As. However, even if 0<X<1 indicates that the ratio of AlAs and GaAs is X=1-X,
Since good crystals can be formed on the ZnSe layer 3A, this may be used instead. Furthermore, as shown in FIG. 3, a plurality of AlxGa1-X As regions 10A, 10B, 10C
are formed so that the Al composition ratio increases from bottom to top, and from bottom to top, n-
AlxGa1-X As layer 4A, 4B, 4C p-
AlxGa1-X As layers 5A, 5B, and 5C may also be used.
また、上記実施例変形例では全てのpn接合は
各図において上がｐ下がｎとなるようにしたが全
て逆にしても良い。 Further, in the above-mentioned modification of the embodiment, all the pn junctions are arranged so that the upper side is p and the lower side is n in each figure, but they may all be reversed.
また、上記実施例変形例では全てのpn接合は
直列に接続されていたが、例えば第４図の如く、
一部の層４，５に開口部１１を設け、新たに
ZnSe層３Ａに電極１２を設け、各ｐ−ｎ接合の
電流を別々にとり出るようにしてもよい。その際
には上記実施例、変形例中のpn接合の向きを同
一方向にする必要がなくなる。 In addition, in the modification of the above embodiment, all the pn junctions were connected in series, but for example, as shown in FIG.
Openings 11 are provided in some layers 4 and 5, and new
An electrode 12 may be provided on the ZnSe layer 3A to draw out the current from each pn junction separately. In this case, it is no longer necessary to orient the pn junctions in the above embodiments and modifications in the same direction.
また、これまでの例は全て、平坦なSi領域９、
GaAs領域１０、AlxGa1-XAs領域１０Ａ，１０
Ｂ，１０Ｃについて適用されたが、例えば第５図
の如く凹凸が有つてもよい。 In addition, in all the examples so far, the flat Si region 9,
GaAs region 10, Alx Ga1-X As region 10A, 10
Although this was applied to B and 10C, it may have irregularities as shown in FIG. 5, for example.
また、これまでの例は全て、基板１はシリコン
で、シリコンのpn接合の一部であつたが、例え
ば第６図の如くサフアイヤ等の基板１Ａ上に形成
されたｎ−Si層１Ｂ上に、後は第１図の例と同様
の事を行つた後、第４図のものと同様の方法で、
電極８を設けるようにしてもよい。 In addition, in all the examples so far, the substrate 1 is silicon and is part of a silicon pn junction, but for example, as shown in FIG. , after doing the same thing as the example in Figure 1, use the same method as in Figure 4,
An electrode 8 may also be provided.
また、これまでの例では全て、Si領域９が基板
１側に置かれたが、第７図の如く族化合物半
導体領域１０を基板１側にしてもよい。但し１は
例えばZnSeのようにGaAs、AlxGa1-XAs、Siよ
り光の吸収端が短波長側にある材料を用い太陽光
等の光は、紙面下部より照射される。また、この
製造方法の１例として、第７図のｎ−Si層１Ａは
最初は厚いｎ−Si基板であつて、その下部の層
２，３Ａ，４，５，１，６，７を形成した後、こ
のｎ−Si基板を削つて電極８を形成することによ
り得られる。 Further, in all the examples so far, the Si region 9 is placed on the substrate 1 side, but the group compound semiconductor region 10 may be placed on the substrate 1 side as shown in FIG. However, 1 uses a material, such as ZnSe, whose light absorption edge is on the shorter wavelength side than GaAs, Alx Ga1-X As, or Si, and light such as sunlight is irradiated from the bottom of the page. As an example of this manufacturing method, the n-Si layer 1A in FIG. 7 is initially a thick n-Si substrate, and the lower layers 2, 3A, 4, 5, 1, 6, and 7 are formed on it. After that, the electrode 8 is obtained by cutting this n-Si substrate.
また、これまでの例では、例えば第１図で電極
７はｐ−GaAs層５に直接、接続されているが、
電極７が存在しないｐ−GaAs層５の部分との間
に紙面横方向に抵抗が生じる。これを避けるため
に、例えば第８図の如く、ｐ−GaAs層５の上に
ｐ−AlxGa1-XAs層１３のように、層５よりも光
の吸収端が短波長側にある材料でしかも比抵抗の
小なる層を設けるようにしてもよい。 In addition, in the examples so far, for example in FIG. 1, the electrode 7 is directly connected to the p-GaAs layer 5;
Resistance occurs in the lateral direction of the paper between the p-GaAs layer 5 and the portion of the p-GaAs layer 5 where the electrode 7 is not present. In order to avoid this, for example, as shown in FIG. 8, a p-Alx Ga1-x As layer 13 is formed on the p-GaAs layer 5 so that the light absorption edge is on the shorter wavelength side than that of the layer 5. A layer made of a material with a low specific resistance may be provided.
この発明は以上説明したとおり、シリコン領域
と化合物半導体領域との間にセレン化亜鉛層を挿
入することにより、シリコン領域のｐ−ｎ接合に
必要な波長域の光を供給し、化合物半導体領域の
結晶性を改善するといつた２つの事を同時に達成
でき総合的な光電変換効率を向上させる効果があ
る。 As explained above, this invention supplies light in the wavelength range necessary for the p-n junction of the silicon region by inserting a zinc selenide layer between the silicon region and the compound semiconductor region, and By improving the crystallinity, two things can be achieved at the same time, which has the effect of improving the overall photoelectric conversion efficiency.
第１図はこの発明の一実施例を示す断面図、第
２図は従来の光電変換半導体装置を示す断面図、
第３図ないし第８図はいずれもこの発明の異なる
他の実施例を示す断面図である。 図において、１は基板、３Ａはセレン化亜鉛
層、７，８はいずれも電極、９はシリコン領域、
１０は族化合物半導体領域である。なお、各
図中同一符号は同一または相当部分を示す。 FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a sectional view showing a conventional photoelectric conversion semiconductor device,
3 to 8 are sectional views showing other different embodiments of the present invention. In the figure, 1 is a substrate, 3A is a zinc selenide layer, 7 and 8 are electrodes, 9 is a silicon region,
10 is a group compound semiconductor region. Note that the same reference numerals in each figure indicate the same or corresponding parts.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60097031AJPS61255074A (en) | 1985-05-08 | 1985-05-08 | Photoelectric conversion semiconductor device |
| DE19863615515DE3615515A1 (en) | 1985-05-08 | 1986-05-07 | SEMICONDUCTOR DEVICE FOR CONVERTING LIGHT INTO ELECTRICAL ENERGY |
| FR8606647AFR2581797B1 (en) | 1985-05-08 | 1986-05-07 | SEMICONDUCTOR DEVICE FOR CONVERTING LIGHT INTO ELECTRICITY |
| US06/860,799US4681982A (en) | 1985-05-08 | 1986-05-08 | Light-electricity conversion semiconductor device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60097031AJPS61255074A (en) | 1985-05-08 | 1985-05-08 | Photoelectric conversion semiconductor device |
| Publication Number | Publication Date |
|---|---|
| JPS61255074A JPS61255074A (en) | 1986-11-12 |
| JPH0511426B2true JPH0511426B2 (en) | 1993-02-15 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60097031AGrantedJPS61255074A (en) | 1985-05-08 | 1985-05-08 | Photoelectric conversion semiconductor device |
| Country | Link |
|---|---|
| US (1) | US4681982A (en) |
| JP (1) | JPS61255074A (en) |
| DE (1) | DE3615515A1 (en) |
| FR (1) | FR2581797B1 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5588994A (en)* | 1980-04-10 | 1996-12-31 | Massachusetts Institute Of Technology | Method of producing sheets of crystalline material and devices made therefrom |
| US4795501A (en)* | 1985-10-30 | 1989-01-03 | The Boeing Company | Single crystal, heteroepitaxial, GaAlAs/CuInSe2 tandem solar cell and method of manufacture |
| JP2527791B2 (en)* | 1988-08-05 | 1996-08-28 | 三菱電機株式会社 | MSM type semiconductor light receiving element |
| JPH02218174A (en)* | 1989-02-17 | 1990-08-30 | Mitsubishi Electric Corp | Photoelectric conversion semiconductor device |
| JPH0793452B2 (en)* | 1991-06-25 | 1995-10-09 | 株式会社日立製作所 | Method for manufacturing tandem hetero photoelectric conversion element |
| US5738731A (en)* | 1993-11-19 | 1998-04-14 | Mega Chips Corporation | Photovoltaic device |
| US6362097B1 (en) | 1998-07-14 | 2002-03-26 | Applied Komatsu Technlology, Inc. | Collimated sputtering of semiconductor and other films |
| US6693033B2 (en) | 2000-02-10 | 2004-02-17 | Motorola, Inc. | Method of removing an amorphous oxide from a monocrystalline surface |
| US6392257B1 (en) | 2000-02-10 | 2002-05-21 | Motorola Inc. | Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same |
| JP2004503920A (en) | 2000-05-31 | 2004-02-05 | モトローラ・インコーポレイテッド | Semiconductor device and method of manufacturing the semiconductor device |
| AU2001264987A1 (en)* | 2000-06-30 | 2002-01-14 | Motorola, Inc., A Corporation Of The State Of Delware | Hybrid semiconductor structure and device |
| WO2002009187A2 (en) | 2000-07-24 | 2002-01-31 | Motorola, Inc. | Heterojunction tunneling diodes and process for fabricating same |
| US6555946B1 (en) | 2000-07-24 | 2003-04-29 | Motorola, Inc. | Acoustic wave device and process for forming the same |
| US6638838B1 (en) | 2000-10-02 | 2003-10-28 | Motorola, Inc. | Semiconductor structure including a partially annealed layer and method of forming the same |
| US20020096683A1 (en) | 2001-01-19 | 2002-07-25 | Motorola, Inc. | Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate |
| US6673646B2 (en) | 2001-02-28 | 2004-01-06 | Motorola, Inc. | Growth of compound semiconductor structures on patterned oxide films and process for fabricating same |
| WO2002082551A1 (en) | 2001-04-02 | 2002-10-17 | Motorola, Inc. | A semiconductor structure exhibiting reduced leakage current |
| US6709989B2 (en) | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
| US6992321B2 (en) | 2001-07-13 | 2006-01-31 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials |
| US6646293B2 (en) | 2001-07-18 | 2003-11-11 | Motorola, Inc. | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates |
| US7019332B2 (en) | 2001-07-20 | 2006-03-28 | Freescale Semiconductor, Inc. | Fabrication of a wavelength locker within a semiconductor structure |
| US6693298B2 (en) | 2001-07-20 | 2004-02-17 | Motorola, Inc. | Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same |
| US6855992B2 (en) | 2001-07-24 | 2005-02-15 | Motorola Inc. | Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same |
| US6667196B2 (en) | 2001-07-25 | 2003-12-23 | Motorola, Inc. | Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method |
| US6639249B2 (en) | 2001-08-06 | 2003-10-28 | Motorola, Inc. | Structure and method for fabrication for a solid-state lighting device |
| US6589856B2 (en) | 2001-08-06 | 2003-07-08 | Motorola, Inc. | Method and apparatus for controlling anti-phase domains in semiconductor structures and devices |
| US20030034491A1 (en) | 2001-08-14 | 2003-02-20 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices for detecting an object |
| US6673667B2 (en) | 2001-08-15 | 2004-01-06 | Motorola, Inc. | Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials |
| US20030071327A1 (en) | 2001-10-17 | 2003-04-17 | Motorola, Inc. | Method and apparatus utilizing monocrystalline insulator |
| US7309832B2 (en)* | 2001-12-14 | 2007-12-18 | Midwest Research Institute | Multi-junction solar cell device |
| AU2002230804A1 (en)* | 2001-12-14 | 2003-06-30 | Midwest Research Institute | Multi-junction solar cell device |
| US6916717B2 (en) | 2002-05-03 | 2005-07-12 | Motorola, Inc. | Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate |
| US7169619B2 (en) | 2002-11-19 | 2007-01-30 | Freescale Semiconductor, Inc. | Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process |
| US6885065B2 (en) | 2002-11-20 | 2005-04-26 | Freescale Semiconductor, Inc. | Ferromagnetic semiconductor structure and method for forming the same |
| US7020374B2 (en) | 2003-02-03 | 2006-03-28 | Freescale Semiconductor, Inc. | Optical waveguide structure and method for fabricating the same |
| US6965128B2 (en) | 2003-02-03 | 2005-11-15 | Freescale Semiconductor, Inc. | Structure and method for fabricating semiconductor microresonator devices |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4094704A (en)* | 1977-05-11 | 1978-06-13 | Milnes Arthur G | Dual electrically insulated solar cells |
| US4295002A (en)* | 1980-06-23 | 1981-10-13 | International Business Machines Corporation | Heterojunction V-groove multijunction solar cell |
| US4400868A (en)* | 1980-12-29 | 1983-08-30 | Varian Associates, Inc. | Method of making a transparent and electrically conductive bond |
| US4387265A (en)* | 1981-07-17 | 1983-06-07 | University Of Delaware | Tandem junction amorphous semiconductor photovoltaic cell |
| JPS58220475A (en)* | 1982-06-17 | 1983-12-22 | Nippon Telegr & Teleph Corp <Ntt> | Monolithic cascade type solar battery |
| JPS59138387A (en) | 1983-01-28 | 1984-08-08 | Nippon Telegr & Teleph Corp <Ntt> | solar cells |
| US4547622A (en)* | 1984-04-27 | 1985-10-15 | Massachusetts Institute Of Technology | Solar cells and photodetectors |
| Publication number | Publication date |
|---|---|
| US4681982A (en) | 1987-07-21 |
| JPS61255074A (en) | 1986-11-12 |
| DE3615515C2 (en) | 1993-03-04 |
| DE3615515A1 (en) | 1986-11-13 |
| FR2581797A1 (en) | 1986-11-14 |
| FR2581797B1 (en) | 1988-10-21 |
| Publication | Publication Date | Title |
|---|---|---|
| JPH0511426B2 (en) | ||
| EP0084621B1 (en) | Semiconductor signal conversion device using photon coupling | |
| US4017332A (en) | Solar cells employing stacked opposite conductivity layers | |
| US9231135B2 (en) | Low-bandgap, monolithic, multi-bandgap, optoelectronic devices | |
| US4547622A (en) | Solar cells and photodetectors | |
| US8624103B2 (en) | Nitride-based multi-junction solar cell modules and methods for making the same | |
| US4633030A (en) | Photovoltaic cells on lattice-mismatched crystal substrates | |
| JP2015073130A (en) | Four-junction inversion-modified multijunction solar cell with two modified layers | |
| JP2010118666A (en) | Alternative substrate of inversion altered multi-junction solar battery | |
| JPH02218174A (en) | Photoelectric conversion semiconductor device | |
| JPS6359269B2 (en) | ||
| US20130081670A1 (en) | Photocell | |
| IL48996A (en) | Photovoltaic cells | |
| JPH0389564A (en) | Photodiode | |
| USH667H (en) | Patterned tunnel junction | |
| US5753050A (en) | Thermophotovoltaic energy conversion device | |
| JP2004521489A (en) | Modified long-wavelength high-speed photodiode | |
| JP2017055017A (en) | Inverted metamorphic multi-junction solar cell with multiple metamorphic layers | |
| JPH0955522A (en) | Tunnel diode | |
| JPH08204215A (en) | Series connected solar cells | |
| JPH06291341A (en) | Solar cell | |
| JPS63261882A (en) | Semiconductor element | |
| JP2788778B2 (en) | Photovoltaic element and method for manufacturing the same | |
| JPS58119679A (en) | solar cells | |
| JPH0448786A (en) | Semiconductor photodetector |