【０００１】0001
【産業上の利用分野】本発明は、受光素子の応答速度を
高速化する構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for increasing the response speed of a light receiving element.
【０００２】0002
【従来の技術】受光素子は、フォトカプラ、光ファイバ
等に広く用いられており、応答速度を高速化するために
、種々の構造が提案されている。2. Description of the Related Art Photodetectors are widely used in photocouplers, optical fibers, etc., and various structures have been proposed to increase response speed.
【０００３】図９はその一例のｐｉｎフォトダイオード
の略断面図である。このような装置は、以下のような工
程で作成される。まず、Ｎ型低比抵抗半導体基板１に、
たとえば、１００オームｃｍ程度のＮ型高比抵抗エピタ
キシャル層６が積層される。次にＮ型高比抵抗エピタキ
シャル層６の表面に、アノードとしてＰ型拡散層３が形
成される。受光素子を５ボルトの逆バイアスで使用する
とした場合、カソード側の空乏層の幅は、約１２ミクロ
ンとなるのでＮ型高比抵抗エピタキシャル層６の厚さは
、受光素子のＰ型拡散層３の底面からＮ型低比抵抗半導
体基板１の表面までが約１２ミクロンとなるように設定
される。この表面は酸化シリコンのような表面保護膜４
で被覆される。この表面保護膜４の所望の場所に穴を開
け、アノード端子５が設けられる。図示されていないが
、カソード端子はＮ型低比抵抗半導体基板１の裏面に設
けられる。FIG. 9 is a schematic cross-sectional view of an example of a pin photodiode. Such a device is created through the following steps. First, on an N-type low resistivity semiconductor substrate 1,
For example, an N-type high resistivity epitaxial layer 6 of about 100 ohm-cm is laminated. Next, a P-type diffusion layer 3 is formed as an anode on the surface of the N-type high resistivity epitaxial layer 6. When the photodetector is used with a reverse bias of 5 volts, the width of the depletion layer on the cathode side is approximately 12 microns, so the thickness of the N-type high resistivity epitaxial layer 6 is equal to the thickness of the P-type diffusion layer 3 of the photodetector. The distance from the bottom surface of the N-type low resistivity semiconductor substrate 1 to the surface of the N-type low resistivity semiconductor substrate 1 is approximately 12 microns. This surface is covered with a surface protective film 4 such as silicon oxide.
covered with. A hole is made at a desired location in this surface protection film 4, and an anode terminal 5 is provided. Although not shown, a cathode terminal is provided on the back surface of the N-type low resistivity semiconductor substrate 1.
【０００４】以上のようにＮ型高比抵抗エピタキシャル
層６を受光部とすることによって、高速応答を得る工夫
がされている。As described above, attempts have been made to obtain high-speed response by using the N-type high resistivity epitaxial layer 6 as a light receiving section.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、前記の
ような構造の受光素子では、カソードとなるＮ型層の高
比抵抗部分をエピタキシャル層で形成するため、さらに
高比抵抗化することが困難で、３００オームｃｍ程度が
限界であり、接合容量を十分低減することができない。このためＣＲ時定数を十分小さくできないので高速化を
妨げる。また、エピタキシャル成長等の高温熱処理によ
り、不純物濃度の高いＮ型低比抵抗半導体基板１から、
Ｎ型高比抵抗エピタキシャル層６にＮ型不純物が這上が
ってしまうため、空乏層化していない這上がり部分で発
生したキャリアが、拡散により空乏層に到達するため、
応答速度の高速化を妨げる。[Problems to be Solved by the Invention] However, in the light receiving element having the above structure, the high resistivity portion of the N-type layer that becomes the cathode is formed of an epitaxial layer, so it is difficult to further increase the resistivity. , 300 ohm-cm is the limit, and the junction capacitance cannot be sufficiently reduced. For this reason, the CR time constant cannot be made sufficiently small, which hinders speeding up. In addition, by high-temperature heat treatment such as epitaxial growth, from the N-type low resistivity semiconductor substrate 1 with a high impurity concentration,
Since N-type impurities creep up into the N-type high resistivity epitaxial layer 6, carriers generated in the creep-up portion that has not become a depletion layer reach the depletion layer by diffusion.
This prevents faster response speed.
【０００６】本発明の目的は、前述の欠点を除き、受光
素子の応答速度の高速化を図ることにある。An object of the present invention is to eliminate the above-mentioned drawbacks and increase the response speed of a light receiving element.
【０００７】[0007]
【課題を解決するための手段】本発明においては、たと
えばＮ型の低比抵抗半導体基板の表面に、基板接着法に
よりＮ型の高比抵抗半導体基板を貼合わせ、このＮ型の
高比抵抗半導体基板の厚さは、その表面に形成されるア
ノード底面からＮ型の低比抵抗半導体基板の表面に到る
までの厚さが、受光素子に加えられる逆バイアスによっ
て広がる空乏層の幅に等しくなるように設定した。[Means for Solving the Problems] In the present invention, for example, an N-type high specific resistance semiconductor substrate is bonded to the surface of an N-type low specific resistance semiconductor substrate by a substrate bonding method, and The thickness of the semiconductor substrate is such that the thickness from the bottom of the anode formed on its surface to the surface of the N-type low resistivity semiconductor substrate is equal to the width of the depletion layer that is expanded by the reverse bias applied to the light receiving element. I set it so that
【０００８】[0008]
【作用】本発明は、以上のような構造であるから、カソ
ードの高比抵抗部分に高比抵抗半導体基板を用いるため
、エピタキシャル成長では得られない、たとえば、１０
００オームｃｍ程度の高比抵抗層が得られ、接合容量を
十分低減でき、ＣＲ時定数を小さくすることができる。また、基板接着法により高比抵抗基板と低比抵抗半導体
基板とを貼合わせるため、低比抵抗半導体基板から高比
抵抗半導体基板への不純物の這上がりが抑えられ、不純
物濃度プロファイルを急峻に保つことができる。これに
より、受光素子に印加される逆バイアスによって広がる
空乏層以外の領域の不純物濃度プロファイルを急峻にで
きるため、空乏層外で発生したキャリアはライフタイム
が短く、光電流に寄与しなくなる。[Function] Since the present invention has the above-described structure, a high resistivity semiconductor substrate is used for the high resistivity portion of the cathode.
A high specific resistance layer of about 0.00 ohm cm can be obtained, the junction capacitance can be sufficiently reduced, and the CR time constant can be made small. In addition, since the high resistivity substrate and the low resistivity semiconductor substrate are bonded together using the substrate bonding method, the creeping up of impurities from the low resistivity semiconductor substrate to the high resistivity semiconductor substrate is suppressed, and the impurity concentration profile is maintained steeply. be able to. As a result, the impurity concentration profile in the region other than the depletion layer, which is expanded by the reverse bias applied to the light-receiving element, can be made steep, so carriers generated outside the depletion layer have a short lifetime and do not contribute to the photocurrent.
【０００９】このような構造にすることによって、応答
速度の高速化の妨げとなる拡散電流成分の寄与しない、
時定数の小さい優れた受光素子が得られる。[0009] By adopting such a structure, the contribution of the diffusion current component, which hinders the increase in response speed, is eliminated.
An excellent light receiving element with a small time constant can be obtained.
【００１０】0010
【実施例】図１は本発明の一実施例の構造を示す略断面
図である。図９の従来例と異なるところは、Ｎ型高比抵
抗エピタキシャル層６の代わりにＮ型高比抵抗半導体基
板２を用い、所望の厚さまで研摩していることである。図９との同一の部分については、同一の符号で表わされ
る。この装置は図２及び図３の略断面図に示されるよう
な工程で製造される。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic sectional view showing the structure of an embodiment of the present invention. The difference from the conventional example shown in FIG. 9 is that an N-type high-resistivity semiconductor substrate 2 is used instead of the N-type high-resistivity epitaxial layer 6 and polished to a desired thickness. The same parts as in FIG. 9 are represented by the same reference numerals. This device is manufactured through the steps shown in the schematic cross-sectional views of FIGS. 2 and 3.
【００１１】まず、図２に示されるように、第１の導電
型をＮ型とすると、Ｎ型低比抵抗半導体基板１の表面に
、１０００オームｃｍ程度のＮ型高比抵抗半導体基板２
が、ウェハ接着法により矢印の方向に貼合わされる。First, as shown in FIG. 2, if the first conductivity type is N type, an N type high resistivity semiconductor substrate 2 of about 1000 ohm cm is formed on the surface of an N type low resistivity semiconductor substrate 1.
are pasted together in the direction of the arrow by the wafer bonding method.
【００１２】次に、図３に示されるように、Ｎ型高比抵
抗半導体基板２は、所望の厚さまで研摩される。受光素
子を５ボルトの逆バイアスで使用するとした場合、カソ
ード側の空乏層の幅は約３５ミクロンとなるので、Ｎ型
高比抵抗半導体基板の厚さは、後で形成されるアノード
となるＰ型拡散層３の底面からＮ型低比抵抗半導体基板
１の表面までが約３５ミクロンとなるように設定される
。Next, as shown in FIG. 3, the N-type high resistivity semiconductor substrate 2 is polished to a desired thickness. When the photodetector is used with a reverse bias of 5 volts, the width of the depletion layer on the cathode side is approximately 35 microns, so the thickness of the N-type high resistivity semiconductor substrate is the same as that of P, which will be formed later. The distance from the bottom of the type diffusion layer 3 to the surface of the N-type low resistivity semiconductor substrate 1 is set to be about 35 microns.
【００１３】次に図１に示すように、Ｎ型高比抵抗半導
体基板２の表面にアノードとなる第２の導電型のＰ型拡
散層３が設けられる。これらの表面は表面保護膜４で被
覆され、その所望の場所に穴を開け、アノード端子５が
設けられる。図示されていないが、カソード端子はＮ型
低比抵抗半導体基板１の裏面に設けられる。Next, as shown in FIG. 1, a P-type diffusion layer 3 of a second conductivity type is provided on the surface of the N-type high resistivity semiconductor substrate 2 to serve as an anode. These surfaces are covered with a surface protective film 4, holes are made at desired locations, and anode terminals 5 are provided. Although not shown, a cathode terminal is provided on the back surface of the N-type low resistivity semiconductor substrate 1.
【００１４】前記の実施例においては、単一の受光素子
のみを形成する構造について述べたが、受光素子と信号
処理回路を同一チップ上に形成する構造についても適用
できる。In the above embodiments, a structure in which only a single light-receiving element is formed has been described, but the present invention can also be applied to a structure in which a light-receiving element and a signal processing circuit are formed on the same chip.
【００１５】図４は、受光素子と信号処理回路を同一チ
ップ上に形成する構造の一実施例を示す略断面図である
。図１と同一の部分については同一の符号で表わされる
。図の左方には受光素子部２０が形成され、右方には信
号処理回路部２１が形成されている。FIG. 4 is a schematic cross-sectional view showing an embodiment of a structure in which a light receiving element and a signal processing circuit are formed on the same chip. The same parts as in FIG. 1 are denoted by the same reference numerals. A light receiving element section 20 is formed on the left side of the figure, and a signal processing circuit section 21 is formed on the right side.
【００１６】この装置は、図５ないし図８の略断面図に
示されるような工程で製造される。まず、図５に示され
るように、約１０００オームｃｍ程度のＮ型高比抵抗半
導体基板２の信号処理回路予定領域にＰ型埋込拡散層７
を形成する。次に、このＮ型高比抵抗半導体基板２を、
Ｎ型低比抵抗半導体基板１の表面に、ウェハ接着法によ
り矢印の方向に貼合わせる。ここでＰ型埋込拡散層７は
、受光素子と信号処理回路を電気的に分離するためのも
のである。This device is manufactured through the steps shown in the schematic cross-sectional views of FIGS. 5 to 8. First, as shown in FIG. 5, a P-type buried diffusion layer 7 is formed in a signal processing circuit area of an N-type high resistivity semiconductor substrate 2 of approximately 1000 ohm cm.
form. Next, this N-type high resistivity semiconductor substrate 2 is
It is bonded to the surface of an N-type low resistivity semiconductor substrate 1 in the direction of the arrow by a wafer bonding method. Here, the P-type buried diffusion layer 7 is for electrically separating the light receiving element and the signal processing circuit.
【００１７】次に、図６に示すように、Ｎ型高比抵抗半
導体基板２を所望の厚さまで研摩する。受光素子を５ボ
ルトの逆バイアスで使用するとした場合、前記実施例と
同様、カソード側の空乏層の幅は約３５ミクロンとなる
ので、Ｎ型高比抵抗半導体基板２の厚さは、後の工程で
形成されるアノードとなるＰ型拡散層１１の底面からＮ
型低比抵抗半導体基板１の表面まで約３５ミクロンとな
るように設定される。Next, as shown in FIG. 6, the N-type high resistivity semiconductor substrate 2 is polished to a desired thickness. When the photodetector is used with a reverse bias of 5 volts, the width of the depletion layer on the cathode side is approximately 35 microns, as in the previous embodiment, so the thickness of the N-type high resistivity semiconductor substrate 2 is as follows. N
The distance to the surface of the low resistivity semiconductor substrate 1 is approximately 35 microns.
【００１８】次に、図７に示すように、信号処理回路予
定領域のみにＮ型埋込拡散層８を形成し、それらの表面
の全面に信号処理回路に適した不純物濃度のＮ型エピタ
キシャル層９が積層される。Next, as shown in FIG. 7, an N-type buried diffusion layer 8 is formed only in the region where the signal processing circuit is planned, and an N-type epitaxial layer with an impurity concentration suitable for the signal processing circuit is formed on the entire surface thereof. 9 are stacked.
【００１９】次に、図８に示されるように、各素子を分
離するため、Ｐ型埋込拡散層７の周縁部の上に、Ｐ型分
離拡散層１０が形成される。また同時に、受光素子部は
その表面にアノードとなるＰ型拡散層１１が形成される
。Next, as shown in FIG. 8, a P-type isolation diffusion layer 10 is formed on the peripheral edge of the P-type buried diffusion layer 7 in order to isolate each element. At the same time, a P-type diffusion layer 11 serving as an anode is formed on the surface of the light receiving element section.
【００２０】次に、図４に示されるように、信号処理回
路予定領域の表面にＰ型のベース拡散層１２、Ｎ型のコ
レクタ拡散層１４、ベース拡散層１２の一部にＮ型のエ
ミッタ拡散層１３が形成される。これらによってＮＰＮ
トランジスタが構成される。これらの表面は表面保護膜
４で被覆され、この表面保護膜４の所望の場所に穴を開
け、アノード端子５、ベース端子１５、コレクタ端子１
７、エミッタ端子１６等が設けられる。カソード端子は
、前述のように図示されていないが、Ｎ型低比抵抗半導
体基板１の裏面に設けられる。Next, as shown in FIG. 4, a P-type base diffusion layer 12, an N-type collector diffusion layer 14, and an N-type emitter are formed on a part of the base diffusion layer 12 on the surface of the signal processing circuit area. A diffusion layer 13 is formed. By these, NPN
A transistor is configured. These surfaces are covered with a surface protective film 4, and holes are made at desired locations in this surface protective film 4 to form an anode terminal 5, a base terminal 15, and a collector terminal 1.
7. An emitter terminal 16 and the like are provided. Although the cathode terminal is not illustrated as described above, it is provided on the back surface of the N-type low resistivity semiconductor substrate 1.
【００２１】本実施例においては、カソード端子を裏面
に設けているが、受光素子２０の適当な場所に、Ｎ型埋
込拡散層のような適当な拡散を順次行なうことによって
、そのカソード端子を表面に設けることもできる。また
、Ｐ型埋込拡散層７を、Ｎ型低比抵抗半導体基板１とＮ
型高比抵抗半導体基板２を貼合わせる前に形成している
が、Ｎ型高比抵抗半導体基板２の研摩後に行なっても構
わない。In this embodiment, the cathode terminal is provided on the back surface, but by sequentially applying appropriate diffusion such as an N-type buried diffusion layer to an appropriate location of the light receiving element 20, the cathode terminal can be It can also be provided on the surface. Furthermore, the P-type buried diffusion layer 7 is connected to the N-type low resistivity semiconductor substrate 1 and the N-type buried diffusion layer 7.
Although it is formed before bonding the N-type high-resistivity semiconductor substrate 2, it may be performed after polishing the N-type high-resistivity semiconductor substrate 2.
【００２２】前記のＰ型半導体をＮ型半導体に置換える
こともできる。[0022] The P-type semiconductor described above can also be replaced with an N-type semiconductor.
【００２３】[0023]
【発明の効果】本発明は、不純物濃度の低い高比抵抗半
導体基板をｐｉｎフォトダイオードのｉ層として用いる
ため、ｉ層の比抵抗をエピタキシャル層では不可能な３
００オームｃｍ以上の高比抵抗とすることができ、受光
素子のカソード側の空乏層の幅が大きくなり、接合容量
を低減できるため、ＣＲ時定数を小さくすることができ
る。Effects of the Invention The present invention uses a high resistivity semiconductor substrate with a low impurity concentration as the i-layer of a pin photodiode, so that the resistivity of the i-layer can be reduced to 3, which is impossible with an epitaxial layer.
A high specific resistance of 00 ohm-cm or more can be achieved, the width of the depletion layer on the cathode side of the light receiving element is increased, and the junction capacitance can be reduced, so that the CR time constant can be reduced.
【００２４】また、貼合わせ技術を用いることで、Ｎ型
低比抵抗半導体基板１からのＮ型不純物の這上がりがな
くなり、カソード側に広がる空乏層外の不純物濃度プロ
ファイルを急峻に保てるため、空乏層外で発生するキャ
リアのライフタイムが短くなり、空乏層に到達する拡散
成分を大幅に低減でき、受光素子の高速動作が可能とな
る。Furthermore, by using the bonding technique, creeping up of N-type impurities from the N-type low resistivity semiconductor substrate 1 is eliminated, and the impurity concentration profile outside the depletion layer spreading toward the cathode side can be maintained steeply. The lifetime of carriers generated outside the layer is shortened, the diffusion component reaching the depletion layer can be significantly reduced, and the light-receiving element can operate at high speed.
【００２５】また、受光素子と信号処理回路を同一チッ
プ上に形成する構造においても、Ｐ型埋込拡散層７形成
時の熱処理をウェハ貼合わせ前に行なえるため、Ｎ型低
比抵抗半導体基板１からのＮ型不純物の這上がりを抑え
ることができる。そのために受光素子の高速動作が可能
となる。Furthermore, even in a structure in which the light receiving element and the signal processing circuit are formed on the same chip, the heat treatment for forming the P-type buried diffusion layer 7 can be performed before bonding the wafers, so that the N-type low resistivity semiconductor substrate The rise of N-type impurities from 1 can be suppressed. This allows the light receiving element to operate at high speed.
【図１】本発明の一実施例の略断面図である。FIG. 1 is a schematic cross-sectional view of an embodiment of the invention.
【図２】本発明の工程の略断面図である。FIG. 2 is a schematic cross-sectional view of the process of the invention.
【図３】本発明の工程の略断面図である。FIG. 3 is a schematic cross-sectional view of the process of the invention.
【図４】本発明の他の実施例の略断面図である。FIG. 4 is a schematic cross-sectional view of another embodiment of the invention.
【図５】図４の工程を示す略断面図である。FIG. 5 is a schematic cross-sectional view showing the process of FIG. 4;
【図６】図４の工程を示す略断面図である。FIG. 6 is a schematic cross-sectional view showing the process of FIG. 4;
【図７】図４の工程を示す略断面図である。7 is a schematic cross-sectional view showing the process of FIG. 4. FIG.
【図８】図４の工程を示す略断面図である。8 is a schematic cross-sectional view showing the process of FIG. 4. FIG.
【図９】従来の一例の略断面図である。FIG. 9 is a schematic cross-sectional view of a conventional example.
１ Ｎ型低比抵抗半導体基板２ Ｎ型高比抵抗半導体基板３ Ｐ型拡散層４ 表面保護膜６ Ｎ型高比抵抗エピタキシャル層７ Ｐ型埋込拡散層８ Ｎ型埋込拡散層９ Ｎ型エピタキシャル層１０ Ｐ型分離拡散層１１ Ｐ型拡散層１２ ベース拡散層１３ エミッタ拡散層１４ コレクタ拡散層１５ ベース端子１６ エミッタ端子１７ コレクタ端子1 N-type low resistivity semiconductor substrate2 N-type high resistivity semiconductor substrate3 P-type diffusion layer4 Surface protective film6 N-type high resistivity epitaxial layer7 P-type buried diffusion layer8 N-type buried diffusion layer9 N-type epitaxial layer10 P-type separation diffusion layer11 P-type diffusion layer12 Base diffusion layer13 Emitter diffusion layer14 Collector diffusion layer15 Base terminal16 Emitter terminal17 Collector terminal
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3000158AJP2700356B2 (en) | 1991-01-07 | 1991-01-07 | Light receiving element |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3000158AJP2700356B2 (en) | 1991-01-07 | 1991-01-07 | Light receiving element |
| Publication Number | Publication Date |
|---|---|
| JPH04242980Atrue JPH04242980A (en) | 1992-08-31 |
| JP2700356B2 JP2700356B2 (en) | 1998-01-21 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3000158AExpired - Fee RelatedJP2700356B2 (en) | 1991-01-07 | 1991-01-07 | Light receiving element |
| Country | Link |
|---|---|
| JP (1) | JP2700356B2 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7649236B2 (en) | 2004-03-31 | 2010-01-19 | Hamamatsu Photonics K.K. | Semiconductor photodetector and photodetecting device having layers with specific crystal orientations |
| JP2010045313A (en)* | 2008-08-18 | 2010-02-25 | Univ Of Tokyo | Method of manufacturing detection element, and method of manufacturing far-infrared detector |
| WO2011129149A1 (en) | 2010-04-14 | 2011-10-20 | 浜松ホトニクス株式会社 | Semiconductor light detecting element |
| WO2012020498A1 (en)* | 2010-08-12 | 2012-02-16 | 富士電機株式会社 | Manufacturing method for semi-conductor device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5864072A (en)* | 1981-10-13 | 1983-04-16 | Nippon Telegr & Teleph Corp <Ntt> | Electron beam emission type semiconductor diode |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5864072A (en)* | 1981-10-13 | 1983-04-16 | Nippon Telegr & Teleph Corp <Ntt> | Electron beam emission type semiconductor diode |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7649236B2 (en) | 2004-03-31 | 2010-01-19 | Hamamatsu Photonics K.K. | Semiconductor photodetector and photodetecting device having layers with specific crystal orientations |
| JP2010045313A (en)* | 2008-08-18 | 2010-02-25 | Univ Of Tokyo | Method of manufacturing detection element, and method of manufacturing far-infrared detector |
| WO2011129149A1 (en) | 2010-04-14 | 2011-10-20 | 浜松ホトニクス株式会社 | Semiconductor light detecting element |
| US9293499B2 (en) | 2010-04-14 | 2016-03-22 | Hamamatsu Photonics K.K. | Semiconductor light detecting element having silicon substrate and conductor |
| WO2012020498A1 (en)* | 2010-08-12 | 2012-02-16 | 富士電機株式会社 | Manufacturing method for semi-conductor device |
| US8685801B2 (en) | 2010-08-12 | 2014-04-01 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor device |
| Publication number | Publication date |
|---|---|
| JP2700356B2 (en) | 1998-01-21 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |