【発明の詳細な説明】［産業上の利用分野］本発明は、半導体装置の保護膜の構造に関する。[Detailed description of the invention][Industrial application field]The present invention relates to the structure of a protective film for a semiconductor device.
［従来の技術］従来の半導体装置及びその表面保護膜の構造は第３図の
ような窒化膜による一層構造をしており、この構造はＡ
ｌ合金膜に与える応力が大きくエレクトロマイグレーシ
ョン及びストレスマイグレーション耐性が劣化した。[Prior art] A conventional semiconductor device and its surface protection film have a single layer structure made of a nitride film as shown in FIG.
The stress applied to the l-alloy film was large and the electromigration and stress migration resistance deteriorated.
この事を従来の工程を追って説明すると、まずＳｉ基板
３０１上に酸化膜（ＳｉＯ２）３０２を全面に形成しフ
ォトエッチによってコンタクト部を設ける。This will be explained by following the conventional steps. First, an oxide film (SiO2) 302 is formed on the entire surface of a Si substrate 301, and a contact portion is provided by photo-etching.
さらに、高融点金属化合物とＡｌ合金膜を含む多層配［
３０３〜３０５を形成しフォトエッチする。Furthermore, a multilayer structure containing a high melting point metal compound and an Al alloy film [
303 to 305 are formed and photoetched.
最後に表面保護膜を窒化膜３０６ （０，８μｍの一層
構造で形成する。Finally, a surface protective film is formed as a nitride film 306 (0.8 μm in single layer structure).
以上が従来の工程である。The above is the conventional process.
［発明が解決しようとする課題及び目的］しかし、前述
の従来技術では、表面保護膜が窒化膜による一層構造で
あるため、Ａｌ合金膜に与える応力が大きくエレクトロ
マイグレーション、ストレスマイグレーション耐性が劣
化するという課題点があった。[Problems and objects to be solved by the invention] However, in the above-mentioned conventional technology, since the surface protective film has a single layer structure made of a nitride film, the stress applied to the Al alloy film is large and the resistance to electromigration and stress migration is deteriorated. There were some issues.
そこで、本発明はこのような課題点を解決するもので、
その目的とするところは、表面保護膜を形成する際、従
来の一層構造から酸化膜と窒化膜の二層構造にすること
によって、Ａｌ合金に与える応力を緩和させより信頼性
の高い多層配線を提供するところにある。Therefore, the present invention is intended to solve these problems.
The purpose of this is to change the conventional single-layer structure to a two-layer structure of an oxide film and a nitride film when forming a surface protection film, thereby alleviating stress on the Al alloy and creating more reliable multilayer wiring. It's there to provide.
［課題を解決するための手段］本発明の半導体装置は、高融点金属化合物とＡ」５合金
膜を含む多層配線の表面を酸化膜と窒化膜で保護し、二
層構造とすることを特徴とする。[Means for Solving the Problems] The semiconductor device of the present invention is characterized in that the surface of a multilayer interconnection including a high melting point metal compound and an A'5 alloy film is protected with an oxide film and a nitride film to form a two-layer structure. shall be.
［作用］本発明の上記の構成によれば、保護膜を形成する際、表
面を酸化膜と窒化膜で保護し二層構造にする事によって
、Ａｌ合金膜に与える応力を緩和させより信頼性の高い
多層配線を備えた半導体装置を構成できる。[Function] According to the above structure of the present invention, when forming the protective film, by protecting the surface with an oxide film and a nitride film to form a two-layer structure, the stress applied to the Al alloy film is relaxed and reliability is improved. It is possible to construct a semiconductor device having multilayer wiring with high resistance.
［実施例］本発明の半導体装置は、第１図に示される構造をしてい
る。[Example] A semiconductor device of the present invention has a structure shown in FIG.
１０１はＳｉ基板、１０２は酸化膜の二酸化珪素、１０
３は窒化チタン、１０４はアルミ合金膜、１０５は窒化
チタン、１０６は保護膜の５ｉ０２．１０７は保護膜の
５ｉ３Ｎａである。101 is a Si substrate, 102 is an oxide film of silicon dioxide, 10
3 is titanium nitride, 104 is an aluminum alloy film, 105 is titanium nitride, 106 is a protective film 5i02.107 is a protective film 5i3Na.
以下、詳細は工程を追いながら説明していく。Details will be explained below as we follow the process.
（第２図（ａ）〜（ｅ））まず、Ｓｉ基板２０１の表面全体に紛縁膜としテ酸化膜
（Ｓｉ０２）２０２を４０００人形成する。(FIGS. 2(a) to 2(e)) First, 4,000 tetanus oxide films (Si02) 202 are formed on the entire surface of the Si substrate 201 as a coating film.
さらに、フォトエッチによってコンタクト開孔部を設け
る。（第２図（ａ））次いで、配線層を形成する工程として、まず、スパッタ
リング装置内に窒素ガスを導入し、アルゴンと窒素の混
合ガスにより、基板温度２００℃の条件下で、反応性ス
パッタを行い、膜厚１０００人の窒化チタン膜（ＴｉＮ
）２０３を形成する。Furthermore, contact openings are provided by photo-etching. (Figure 2 (a)) Next, in the process of forming a wiring layer, first, nitrogen gas is introduced into the sputtering equipment, and reactive sputtering is performed using a mixed gas of argon and nitrogen at a substrate temperature of 200°C. A titanium nitride film (TiN) with a thickness of 1000
) 203 is formed.
さらにその上層にアルミ合金（Ａ １−０． ５ ％
Ｃｕ）２０４をスパッタし、膜厚０．５μｍのアルミ合
金膜を得る。さらに、もう−度反応性スバッタにより、
膜厚４００人の窒化チタン２０５を形成し、ＴｉＮ／Ａ
ｌ−０，５％Ｃｕ ／ Ｔ ｉ Ｎの三層構造配線を得
る。（第２図（ｂ））こうして得られた三層配線をフォトエッチによて同時に
パターニングする。（第２図（Ｃ））次に、該多層配線
の上層に保護膜として、５ｉ０２膜２０６を形成する。Furthermore, the upper layer is aluminum alloy (A 1-0.5%
Cu) 204 is sputtered to obtain an aluminum alloy film with a thickness of 0.5 μm. Furthermore, due to the reactive spatter,
Form a film of titanium nitride 205 with a thickness of 400 mm and TiN/A
A three-layer wiring structure of l-0,5% Cu/TiN is obtained. (FIG. 2(b)) The three-layer wiring thus obtained is simultaneously patterned by photoetching. (FIG. 2(C)) Next, a 5i02 film 206 is formed as a protective film on the multilayer wiring.
（第３図（ｄ））この際、該酸化膜の形成方法としては
、ＴＥ０１（Ｓｉ（○Ｃ２Ｈ３）４）によって３０００
人のＳｉＯ２を形成する。さらに保護膜のＳｉ３Ｎ、膜
２０７を形成する。（第２図（ｅ））この際、該窒化膜の形成方法としては５ｘＨａガス６０
０ｓｅｃｍ、ＮＨ３ガス６４００ｓｅｃｍの混合ガスに
より、圧力２５００ｍｔｏｒｒ、温度３５０℃の条件下
で、Ｓ Ｌ ３ Ｎ ｍ膜厚００人を得る。(Fig. 3(d)) At this time, the oxide film was formed using TE01 (Si(○C2H3)4).
Forming human SiO2. Furthermore, a Si3N film 207 as a protective film is formed. (Fig. 2(e)) At this time, the method for forming the nitride film is 5xHa gas 60
Using a mixed gas of 0 sec. and NH3 gas for 6400 sec., a film thickness of S L 3 N m and 0.00 mm is obtained under conditions of a pressure of 2500 mtorr and a temperature of 350° C.
上述の工程を経て、できあがった本発明、半導体装置は
、従来の半導体装置に比べると、表面を酸化膜と窒化膜
で保護し、二層構造にする事によって、Ａｌ合金膜に与
える応力を緩和させエレクトロマイグレーション及びス
トレスマイグレーションに強い配線が得られる。The semiconductor device of the present invention, which is completed through the above steps, has a two-layer structure with the surface protected by an oxide film and a nitride film, which reduces the stress applied to the Al alloy film, compared to conventional semiconductor devices. Thus, wiring that is resistant to electromigration and stress migration can be obtained.
さらに、本発明半導体装置を用いてエレクトロマイグレ
ーション試験を行ったところ、保護膜を二層にすると、
従来の一層構造に比べてＴＴＦ （Ｔｉｍｅ Ｔｏ
Ｆａｉ、１ｕｒｅ）にして２倍以上の向上がみちれた
。Furthermore, when an electromigration test was conducted using the semiconductor device of the present invention, it was found that when the protective film is made of two layers,
TTF (Time To
Fai, 1ure), an improvement of more than twice was observed.
［発明の効果］以上に述べた本発明によれば、従来の構造に比べて、保
護膜を形成する際、表面を酸化膜と窒化膜で保護し二層
構造にする事によって、Ａｌ合金に与える応力を緩和さ
せより信頼性の優れた半導体装置を提供できる。[Effects of the Invention] According to the present invention described above, compared to the conventional structure, when forming a protective film, the surface is protected with an oxide film and a nitride film to form a two-layer structure. It is possible to provide a semiconductor device with higher reliability by alleviating the applied stress.
第１図は、本発明の半導体装置を示す、主要断面図。第２図（ａ）〜（ｅ）は、本発明の半導体装置の製造工
程の断面図。第３図は、従来の半導体装置を示す断面図。１０１．２０１，３０１・・・Ｓｉ基板１０２．２０２
，３０２・・・酸化膜（ＳｉＯ２）１０３．２０３，３
０３・・・窒化チタン（ＴｉＮ）１０４．２０４，３０
４・・・Ａｌ合金膜１０５．２０５，３０５・・・窒化
チタン（ＴｉＮ）１０６．２０６ −− ・保護
膜（Ｓｉ０２）１０７．２０７，３０６・・・保護膜（
Ｓｉ３Ｎ４）以 上出願人 セイコーエプソン株式会社代理人 弁理士 絵本喜三部 他１名第霞（ｅ第巳（１）＋（（Ｌ）第１男とす力図FIG. 1 is a main sectional view showing a semiconductor device of the present invention. FIGS. 2(a) to 2(e) are cross-sectional views of the manufacturing process of the semiconductor device of the present invention. FIG. 3 is a sectional view showing a conventional semiconductor device. 101.201,301...Si substrate 102.202
,302...Oxide film (SiO2) 103.203,3
03...Titanium nitride (TiN) 104.204,30
4...Al alloy film 105.205,305...Titanium nitride (TiN) 106.206 ---Protective film (Si02) 107.207,306...Protective film (
Si3N4) and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Emoto and 1 other person Daikasumi (e Daimi (1) + ((L) 1st son and Rikizu
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21841390AJPH04100232A (en) | 1990-08-20 | 1990-08-20 | semiconductor equipment |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21841390AJPH04100232A (en) | 1990-08-20 | 1990-08-20 | semiconductor equipment |
| Publication Number | Publication Date |
|---|---|
| JPH04100232Atrue JPH04100232A (en) | 1992-04-02 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21841390APendingJPH04100232A (en) | 1990-08-20 | 1990-08-20 | semiconductor equipment |
| Country | Link |
|---|---|
| JP (1) | JPH04100232A (en) |
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| US6448612B1 (en) | 1992-12-09 | 2002-09-10 | Semiconductor Energy Laboratory Co., Ltd. | Pixel thin film transistor and a driver circuit for driving the pixel thin film transistor |
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5427980A (en)* | 1992-12-02 | 1995-06-27 | Hyundai Electronics Industries Co., Ltd. | Method of making a contact of a semiconductor memory device |
| US6448612B1 (en) | 1992-12-09 | 2002-09-10 | Semiconductor Energy Laboratory Co., Ltd. | Pixel thin film transistor and a driver circuit for driving the pixel thin film transistor |
| US6608353B2 (en) | 1992-12-09 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having pixel electrode connected to a laminate structure |
| US7045399B2 (en) | 1992-12-09 | 2006-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
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