【発明の詳細な説明】〔産業上の利用分野〕本発明は微細金属パターンの形成方法に関する。[Detailed description of the invention][Industrial application field]The present invention relates to a method for forming fine metal patterns.
従来この種の微細金属パターン形成方法としてはめっき
用の下地金属をスパッタ等で基板全面に付着した後レジ
ストパターンを形成して、さらに下地金属と同種の金属
を電気めっき法でパターンめっきし、レジストパターン
を除去した後にイオンミリング、スパッタエッチあるい
は種々のエツチング液を用いたウェットエッチ法により
レジストパターンの下にあった不要部分の下地金属を除
去する手法がよく用いられている（例ば特開昭５０・９
５１４７）。Conventionally, this type of fine metal pattern formation method involves depositing a base metal for plating on the entire surface of the substrate by sputtering, etc., forming a resist pattern, and then pattern-plating the same type of metal as the base metal using electroplating. After removing the pattern, a method is often used in which unnecessary portions of the underlying metal under the resist pattern are removed by ion milling, sputter etching, or wet etching using various etching solutions (for example, in Japanese Patent Application Laid-Open No. 50.9
5147).
上述した従来の微細金属パターン形成方法では、パター
ン幅が細い場合に下地金属の除去が困難になるという欠
点がある。特に線間隔が２μｍ以下、パターンの膜厚が
３μｍ以上となるような高密度配線パターンの場合は、
従来良く用いられているイオンミリングでは、ミリング
された金属の再付着などにより、下地金属の除去がほと
んどできないという欠点があった。The above-described conventional method for forming a fine metal pattern has a drawback that it becomes difficult to remove the underlying metal when the pattern width is narrow. In particular, in the case of high-density wiring patterns where the line spacing is 2 μm or less and the pattern film thickness is 3 μm or more,
Ion milling, which has been commonly used in the past, has the disadvantage that the underlying metal can hardly be removed due to redeposition of the milled metal.
本発明の微細パターン形成方法は金属膜を基板全体に付
着する工程とフォトレジストパターンを金属膜上に形成
する工程と、電気めっきにより該金属膜より電気化学的
に貴である金属パターンを該フォトレジストパターン以
外の該金属膜をウェットエツチングする工程とを含むこ
とを特徴とする。The fine pattern forming method of the present invention includes a step of attaching a metal film to the entire substrate, a step of forming a photoresist pattern on the metal film, and a step of forming a metal pattern that is electrochemically more noble than the metal film by electroplating. The method is characterized in that it includes a step of wet etching the metal film other than the resist pattern.
Ｃ実施例〕次に、本発明について図面を参照して説明する。C Example]Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の工程の基板断面図の一部を
示す。FIG. 1 shows a part of a cross-sectional view of a substrate in a step of an embodiment of the present invention.
（ａ）はＳｉまたはＡ ！！ ２０３などの半導体もし
くは非導体の基板１の上にめっき下地膜３としてのＮｉ
を３０００人スパッタ法で付着した状態を示す。この上
にポジティブフォトレジストをマスクを通して露光・現
像して所望のコイルのネガ状態のレジストマスク４が（
ｂ）に示すように形成される。下地膜３をカソードする
ことによ１７Ｃｕが電気めっきされ（Ｃ）のようにＣｕ
コイルパターン５が形成される。（ｄ）に示すようにレ
ジストマスク４を剥離した後、３．５％塩化第２鉄水溶
液に浸す。(a) is Si or A! ! Ni as a plating base film 3 on a semiconductor or non-conductor substrate 1 such as 203
This figure shows the state in which it was deposited using the 3000-person sputtering method. On top of this, a positive photoresist is exposed and developed through a mask to form a negative resist mask 4 of the desired coil (
It is formed as shown in b). 17Cu is electroplated by using the base film 3 as a cathode, as shown in (C).
A coil pattern 5 is formed. After the resist mask 4 is peeled off as shown in (d), it is immersed in a 3.5% ferric chloride aqueous solution.
塩化第２鉄水溶液はＮｉもＣｕも溶かすがＮｉよりＣｕ
の方が電気化学的に貴であるためにＮｉの溶解が促進さ
れ（ｅ）に示すように不要部分の下地膜３が除去される
。Ferric chloride aqueous solution dissolves both Ni and Cu, but Cu is more soluble than Ni.
Since this is electrochemically more noble, the dissolution of Ni is promoted and unnecessary portions of the base film 3 are removed as shown in (e).
この手法はＮｉとＣｕだけでなく他の金属の組み合わせ
（ＡｕとＣｕなど）でも適用できる。This method can be applied not only to Ni and Cu but also to other metal combinations (Au and Cu, etc.).
以上説明したように本発明は、めっき膜にめっき下地よ
り責な材料を用いることにより、下地膜のエツチングが
速やかに進行し、微細金属パターンを一容易に形成する
ことができる効果がある。As explained above, the present invention has the advantage that by using a material more aggressive than the plating base for the plating film, etching of the base film proceeds quickly and a fine metal pattern can be easily formed.
第１図は本発明の一実施例の工程図を示す図である。１・・・・・・基板、３・・・・・・下地膜、４・・・
・・・レジストマスク、５・・・・・・Ｃｕコイルパタ
ーン。FIG. 1 is a diagram showing a process diagram of an embodiment of the present invention. 1... Substrate, 3... Base film, 4...
...Resist mask, 5...Cu coil pattern.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14058389AJPH036023A (en) | 1989-06-02 | 1989-06-02 | Formation of fine metal patter |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14058389AJPH036023A (en) | 1989-06-02 | 1989-06-02 | Formation of fine metal patter |
| Publication Number | Publication Date |
|---|---|
| JPH036023Atrue JPH036023A (en) | 1991-01-11 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14058389APendingJPH036023A (en) | 1989-06-02 | 1989-06-02 | Formation of fine metal patter |
| Country | Link |
|---|---|
| JP (1) | JPH036023A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6117784A (en)* | 1997-11-12 | 2000-09-12 | International Business Machines Corporation | Process for integrated circuit wiring |
| KR100530737B1 (en)* | 2000-01-27 | 2005-11-28 | 한국전자통신연구원 | Fabrication method of metalization by electroplating in multi-chip module substrate manufacturing process |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6117784A (en)* | 1997-11-12 | 2000-09-12 | International Business Machines Corporation | Process for integrated circuit wiring |
| KR100530737B1 (en)* | 2000-01-27 | 2005-11-28 | 한국전자통신연구원 | Fabrication method of metalization by electroplating in multi-chip module substrate manufacturing process |
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