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JPH02170430A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

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Publication number
JPH02170430A
JPH02170430AJP63324331AJP32433188AJPH02170430AJP H02170430 AJPH02170430 AJP H02170430AJP 63324331 AJP63324331 AJP 63324331AJP 32433188 AJP32433188 AJP 32433188AJP H02170430 AJPH02170430 AJP H02170430A
Authority
JP
Japan
Prior art keywords
film
plasma
wiring
passivation
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63324331A
Other languages
Japanese (ja)
Inventor
Toshiharu Akimoto
秋元 利春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co LtdfiledCriticalFuji Electric Co Ltd
Priority to JP63324331ApriorityCriticalpatent/JPH02170430A/en
Publication of JPH02170430ApublicationCriticalpatent/JPH02170430A/en
Pendinglegal-statusCriticalCurrent

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Abstract

PURPOSE:To obtain a passivation film, which has a low internal stress and has a blocking action and a gettering action in combination, by a method wherein, after a plasma-PSG film doped with 2 to 5wt.% of P is adhered on the lower layer of a device, the structure of the device is formed into a multilayer structure consisting of a plasmaSiO film, a plasma-SiON film and a plasma-SiN film. CONSTITUTION:A p-type PSG film 4 doped with 2 to 5wt.% of P is adhered on a lower layer of a device as a passivation film subsequent to the formation of a metallic wiring and thereafter, the structure of the device is formed into a multilayer structure consisting of a p-type SiO film 5, a p-type SiON film 6 and a p-type SiN film 7 to restrain a steep change in the composition of the films. Thereby, while a local difference in a thermal expansion coefficient and a local stress concentration due to the difference are reduced, the formation of the passivation film, which has a low internal stress as a whole, and has a blocking action due to the film 7 and a gettering action due to the film 4, becomes possible. Therefore, a corrosion of a wiring, such as an Al wiring and the like, and the intrusion of alkaline ions, such as Na ions and the like, are stopped. Moreover, the track resistance of the device is improved by an addition of the P.

Description

Translated fromJapanese

【発明の詳細な説明】〔産業上の利用分野〕本発明は、半導体基板上に金属配線を形成後、さらにそ
の上にブロッキング作用とゲッタリング作用をfi備し
たパッシベーション膜がプラズマ励起CVD法で被覆さ
れる半導体装置の製造方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for forming metal wiring on a semiconductor substrate, and then forming a passivation film having a blocking effect and a gettering effect thereon using a plasma-enhanced CVD method. The present invention relates to a method of manufacturing a coated semiconductor device.

〔従来の技術〕[Conventional technology]

従来、金属配線形成後のパッシベーション膜としてはプ
ラズマ窒化膜(P−5IN llり、プラズマ燐珪酸ガ
ラスH!A (P−PSGPlt)あるいはプラズマオ
キシナイトライド1IA(P−5iON膜)がよく知ら
れている。
Conventionally, plasma nitride films (P-5IN), plasma phosphosilicate glass H!A (P-PSGPlt), or plasma oxynitride 1IA (P-5iON films) are well known as passivation films after metal wiring is formed. There is.

パッシベーション膜のパッシベーション効果は、大別し
てブロッキング作用とゲッタリング作用の二つに分けら
れ、そのうちブロッキング作用とは機械的損傷からの半
導体装置の保護や、外界からの水分の浸入によるMの腐
食、電食の防止の他、アルカリイオン等の不純物イオン
や金属不純物原子の侵入を阻止したり、α線によるソフ
トエラー効果を緩和させ特性の安定化を図るという作用
であり、それに加えM配線上のヒロックやエレクトロマ
イグレーシランの発生を抑制し信鯨性を向上させる効果
を持つ、すなわちデバイスの表面を絶縁保#1llff
で被覆し、外界の雰囲気から遮断することでデバイスの
信鯨性を確保しようとするものである。一方ゲツタリン
グ作用とは、外界から内部に侵入しようとするイオン等
をその保護膜内部で捕捉し、固定、不([化してしまう
作用であり、特に特徴的な作用としてパッシベーション
膜の下層に残存しているアルカリイオンなども捕獲1不
活性化し、Si  5lot界面、すなわちMO5界面
を安定化させるという作用も持っている0以上がパッシ
ベーション膜に要求される基本的特性である。
The passivation effect of a passivation film can be broadly divided into blocking effect and gettering effect. Of these, blocking effect protects the semiconductor device from mechanical damage, and protects the semiconductor device from corrosion due to moisture intrusion from the outside world. In addition to preventing corrosion, it also prevents the entry of impurity ions such as alkali ions and metal impurity atoms, and stabilizes the characteristics by mitigating the soft error effect caused by alpha rays.In addition, it prevents hillocks on the M wiring. It has the effect of suppressing the generation of electromigration silane and improving reliability, that is, it has the effect of insulating the surface of the device.
The idea is to ensure the reliability of the device by covering it with a protective layer and shielding it from the outside atmosphere. On the other hand, the gettering effect is an effect in which ions, etc. that try to enter from the outside world are captured inside the protective film, fixed and immobilized, and a particularly characteristic effect is that they remain in the lower layer of the passivation film. The basic characteristics required for a passivation film are 0 or more, which also has the effect of trapping and inactivating alkali ions, etc., and stabilizing the Si5lot interface, that is, the MO5 interface.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

パッシベーション膜としてよく知られている膜のうちの
P−SiN膜は、機械的強度が強く、さらにアルカリイ
オン、 H,O,α線などのブロック性に優れているが
、+5〜6 X 10”dyns/−程度の非常に高い
圧縮性の内部応力をもつため、例えばMの配線幅が3〜
2−になると、その応力に起因してMにスリット状の空
洞が生ずることにより電流密度が高くなり、エレクトロ
マイグレーシコンにより断線を起こす確率が高くなると
いう問題があった。
P-SiN film, which is well known as a passivation film, has strong mechanical strength and excellent blocking properties against alkali ions, H, O, α rays, etc. Because it has a very high compressive internal stress on the order of dyns/-, for example, if the wiring width of M is 3~
When the voltage becomes 2-, a slit-like cavity is formed in M due to the stress, which increases the current density and increases the probability of wire breakage due to electromigration silicon.

これに加え、内部応力を減少させるような膜の生成条件
にすると、今度はトレードオフ的に膜中水素濃度が2〜
3重量%に高くなり、その水素がMO8界面に移動して
ホットエレクトロンをトラシブしMOSの闇値電圧の変
動を招くという問題も報告されている0次にp−psc
膜の場合は、燐が添加されているため、ゲッタリング効
果によりアルカリイオンを固定できると共に燐をドープ
しない通常のプラズマ酸化膜(P−5iOIIりに比し
熱膨張係数が増加し、Mとの熱膨張係数の差を小さくで
きるのでM上でクランクを生じにくくすることができる
。さらに、膜中の水素量は微小であるので、P−5iN
 Illで問題となったようなMO3界面の不安定性の
問題はない、しかし現状、通常使用されているP!0.
濃度は、内部応力を+2 X lo”dyns/−以下
に小さくするため通常2〜5重量%程度であり、燐があ
る程度入っているので耐水性が低下しMの腐食を引き起
こすという可能性もすてきれないという問題があった。
In addition to this, if the film formation conditions are set to reduce internal stress, then as a trade-off, the hydrogen concentration in the film will be 2 to 2.
3% by weight, it has been reported that the hydrogen moves to the MO8 interface and trasses hot electrons, causing fluctuations in the dark value voltage of the MOS.
In the case of the film, since phosphorus is added, alkali ions can be fixed due to the gettering effect, and the coefficient of thermal expansion is increased compared to the normal plasma oxide film (P-5iOII) that is not doped with phosphorus, and it is different from M. Since the difference in thermal expansion coefficient can be reduced, it is possible to prevent cranking on M.Furthermore, since the amount of hydrogen in the film is minute, P-5iN
There is no problem of instability at the MO3 interface as was the problem with Ill, but at present, the commonly used P! 0.
The concentration is usually about 2 to 5% by weight in order to reduce the internal stress to +2 x lo" dyns/- or less, and since it contains a certain amount of phosphorus, there is a possibility that the water resistance will decrease and cause corrosion of M. There was a problem that it could not be done.

もちろん、ブロッキング性。Of course, blocking.

膜の硬度という観点ではP−3iN Illの方が有利
である。1後に、膜の応力を緩和することを目的とした
ものにP−3iON膜がある。この性質は膜の生成条件
にも大きく依存するが、P−5iO膜とP−538膜の
両者の性質をあわせもつと考えられる0例えば比誘電率
は4.7でp−5to膜と同程度である。水分に対する
耐水性はP−3IN Illと同程度である。そして、
膜の内部応力は生成条件を適当に選択すると零応力或い
は−2X IQ”dyns/−程度の引っ張り性にする
ことが出来る。しかし、膜中に燐が含有されていないの
でパッシベーション効果のうちゲッタリング効果はない
という不完全さがあり、例えば上部のりフロー膜として
硼素ガラス1! (BSG膜)を使用した場合は、半導
体装置としてのゲッタリング効果が不充分なものとなる
問題があった。
P-3iN Ill is more advantageous in terms of film hardness. After 1, there is a P-3iON film whose purpose is to relieve stress in the film. Although this property largely depends on the film formation conditions, it is thought to have the properties of both P-5iO film and P-538 film. For example, the dielectric constant is 4.7, which is about the same as that of P-5to film. It is. Water resistance to moisture is comparable to P-3IN Ill. and,
The internal stress of the film can be reduced to zero stress or tensile strength of -2X IQ" dyns/- by appropriately selecting the formation conditions. However, since the film does not contain phosphorus, gettering is a part of the passivation effect. For example, when boron glass 1! (BSG film) was used as the upper adhesive flow film, there was a problem that the gettering effect as a semiconductor device would be insufficient.

本発明の課題は、上記の各パッシベーション膜の問題点
を解決して、膜の内部応力は充分低減され、しかもブロ
ッキング作用とゲッタリング作用とを兼ね備えたパフシ
ベーシ町ン膜をプラズマ励起CVD法で形成する半導体
装置の製造方法を提供することにある。
The object of the present invention is to solve the problems of each of the above passivation films, and to form a passivation film using a plasma-enhanced CVD method, in which the internal stress of the film is sufficiently reduced, and which also has both blocking and gettering functions. An object of the present invention is to provide a method for manufacturing a semiconductor device.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題の解決のために、本発明の方法は、金属配線を
形成した半導体基板の上を、燐珪酸ガラス膜、シリコン
酸化膜、シリコンオキシナイトライド膜、シリコン窒化
膜を下層よりそれぞれプラズマ励起CVD法を用いて順
次積層してなるパッシベーション膜により被覆するもの
とする。
In order to solve the above problems, the method of the present invention is to form a phosphosilicate glass film, a silicon oxide film, a silicon oxynitride film, and a silicon nitride film from below on a semiconductor substrate on which metal wiring is formed by plasma-excited CVD. It shall be covered with a passivation film formed by sequentially laminating layers using a method.

〔作用〕[Effect]

パッシベーション膜の構造を、下層から、配線金属との
熱膨張係数の差の小さいP−PSG #から始メ7P−
5iOH,P−5iON!、 P−5iN IIIヲI
IIニ1IJEi I。
The structure of the passivation film starts from P-PSG #7P-, which has a small difference in thermal expansion coefficient from the wiring metal, from the bottom layer.
5iOH, P-5iON! , P-5iN III
II Ni1IJEi I.

た4FJfi造とし、パッシベーション膜の深さ方向の
ドーパントの急峻な変動をおさえることで局所的な熱膨
張係数の差異を低減し、さらに各単層の応力を相殺させ
パッシベーション膜としての内部応力を低減した上で、
上N膜であるP−3iN膜によるブロッキング効果、耐
湿性向上の他に、下層のP−PSG Illによるゲッ
タリング効果もあわせもつようにし、さらに金属配線上
での耐クランク性を向上させ、最終的に半導体装置の信
頼性を向上させる。
The 4FJfi structure reduces local differences in thermal expansion coefficients by suppressing steep fluctuations in dopants in the depth direction of the passivation film, and also reduces internal stress as a passivation film by canceling out stress in each single layer. After that,
In addition to the blocking effect and moisture resistance improvement of the P-3iN film, which is the upper N film, the gettering effect of the lower layer P-PSG Ill is also provided, and the crank resistance on the metal wiring is further improved. to improve the reliability of semiconductor devices.

〔実施例〕〔Example〕

第1図(5)、 (blは本発明の一実施例の工程を示
し、シリコン基板lに眉間絶縁膜としてのシリコン酸化
膜2を介してアルミニウム1を極配線3を形成しく図8
)、次いで枚葉式平行平板型のプラズマCVD%装置の
反応槽にこの基板を収容する1反応槽には、NxO−5
Nx0−5i系ガスを、SiBr4 secm、8.0
101000seの流量で、またPl+3/S目1#の
流量比を0.02〜0.12とし、キャリアガスとして
の300secmの流量のArガスと共に導入する。生
成温度380〜420℃、高周波電源周波数200kH
z、高周波パワー40W、堆積時圧力約I Torrの
条件に設定してプラズマを発生させ、図(blに示すP
−PSGS複膜堆積する。堆積速度は約l000人/分
で、得られた膜の屈折率は1.47となる。燐濃度はM
上での耐クランク性の向上を目的に粘性係数を上げるた
めと、耐湿性、ゲッタリング作用を勘案し2〜5重量%
程度となるようにPH2流量等の生成条件を鯛整する。
FIG. 1(5), (bl shows the process of one embodiment of the present invention, in which a polar wiring 3 is formed using aluminum 1 on a silicon substrate 1 via a silicon oxide film 2 as an insulating film between the eyebrows.
), then one reaction tank in which this substrate is accommodated in a reaction tank of a single-wafer parallel plate type plasma CVD% apparatus is filled with NxO-5.
Nx0-5i gas, SiBr4 sec, 8.0
At a flow rate of 101,000 sec, and a flow rate ratio of Pl+3/Sth 1# of 0.02 to 0.12, it is introduced together with Ar gas as a carrier gas at a flow rate of 300 sec. Generation temperature 380-420℃, high frequency power supply frequency 200kHz
Plasma was generated under the conditions of z, high frequency power of 40 W, and deposition pressure of approximately I Torr.
- Deposit PSGS multilayer. The deposition rate is approximately 1000 people/min and the refractive index of the resulting film is 1.47. Phosphorus concentration is M
2 to 5% by weight in order to increase the viscosity coefficient for the purpose of improving crank resistance, and taking into consideration moisture resistance and gettering effect.
Adjust the generation conditions such as PH2 flow rate so that

2層目のP−SiO膜5の形成は、上記条件のうちPH
s流量−〇とすることによって形成する0次に、3層目
のP−5ION膜6の形成は、N、O−3iHt−NI
(3系のガスを、5iH=30scc1 NI050〜
200scem、キャリアArAr300seの流量で
導入し、堆積時圧力を1〜3 Torrに設定して行う
、堆積速度は500〜600人/分で、得られた膜の屈
折率は1.82となる。第2図にP−3iON膜の生成
条件と内部応力の関係の一例を示す、R= NtO/ 
(NxO+Nus)と定義した場合、NH,の流量を一
定にしてR−0,2および0.8近辺で内部応力零の状
態が実現しており、例えば生成条件を変えることで応力
の変化が容易となる。!!に後に5iHi−NL系のガ
スを、5IH440sccm、 NH。
The formation of the second layer P-SiO film 5 was performed under the above conditions of PH
The third layer P-5 ION film 6 is formed by setting the s flow rate to −〇.N,O-3iHt-NI
(3 series gas, 5iH=30scc1 NI050~
The deposition rate is 500 to 600 persons/min, and the refractive index of the obtained film is 1.82. Figure 2 shows an example of the relationship between the formation conditions of the P-3iON film and the internal stress, R = NtO/
When defined as (NxO+Nus), a state of zero internal stress is achieved near R-0, 2 and 0.8 with a constant flow rate of NH, and it is easy to change the stress by changing the generation conditions, for example. becomes. ! ! After that, 5iHi-NL gas was added to 5IH440sccm, NH.

200sccm、キャリアN! 300secmの流量
で反応槽内に導入し、高周波パワー60W、堆積時圧力
をITorrの条件に設定しP−5iN膜7を成膜する
。堆積速度は700人/分で、得られた膜の屈折率は2
.0となる。このようにして形成されたパッシベーショ
ン膜の全体の厚さは1〜1゜5ρ程度である。
200sccm, carrier N! The P-5iN film 7 is formed by introducing into the reaction tank at a flow rate of 300 sec, setting the high frequency power to 60 W, and the deposition pressure to ITorr. The deposition rate was 700 people/min, and the refractive index of the resulting film was 2.
.. It becomes 0. The total thickness of the passivation film thus formed is about 1 to 1.5 .rho.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、金属配線形成後のパッシベーション膜
として下層に燐を2〜5重量%ドープしたp−psc@
を被着した後、順にP−5iOIIl 、 P−5iO
N膜、P−5iN膜という多層構造にして膜の組成の急
峻な変化をおさえているので、局所的な熱膨張係数の違
いや、それに起因する応力の局所的な集中を低減しなが
ら全体として低内部応力で、かつ、P−5iN W4に
よるブロッキング作用とP−PSG膜によるゲッタリン
グ作用を烹ね備えたパッシベーション膜の形成が可能と
なる。そのため、例えば、Mなどの配線の腐食の防止、
 Naイオンなどのアルカリイオンの浸入阻止および膜
中への捕捉と不活性化、燐の添加による耐クランク性の
向上、膜中水素濃度の減少によるMO3界面の安定性の
向上などが可能となり、はぼ理想的なパンシベーション
効果を得ることができるので、信紅性の高い半導体装置
をつくることが可能となる。さらに、P−5iON膜の
生成条件や膜厚を変えることで、全体的なパッシベーシ
ョン膜としての応力特性を容易に変えることができるの
で、金属配線下の眉間絶縁膜との応力との整合がとれや
すくなり、半導体装置の複合的な応力の低減が可能とな
り、高い信頼性を持つ半導体装置の作成が可能となる。
According to the present invention, p-psc@ doped with 2 to 5% by weight of phosphorus in the lower layer as a passivation film after metal wiring is formed.
After depositing P-5iOIIl, P-5iO
The multilayer structure of N film and P-5iN film suppresses sudden changes in the composition of the film, reducing local differences in thermal expansion coefficients and local concentration of stress caused by them, while improving overall performance. It is possible to form a passivation film that has low internal stress and has both the blocking effect of P-5iN W4 and the gettering effect of P-PSG film. Therefore, for example, prevention of corrosion of wiring such as M,
It is possible to prevent alkaline ions such as Na ions from entering, trap them in the membrane, and inactivate them, improve crank resistance by adding phosphorus, and improve the stability of the MO3 interface by reducing the hydrogen concentration in the membrane. Since an almost ideal pansivation effect can be obtained, it becomes possible to produce semiconductor devices with high reliability. Furthermore, by changing the formation conditions and film thickness of the P-5iON film, the overall stress characteristics of the passivation film can be easily changed, so the stress can be matched with the glabella insulating film under the metal wiring. This makes it possible to reduce the complex stress of the semiconductor device, making it possible to create a highly reliable semiconductor device.

また、プラズマ励起CVD法を真空ロード・ロック式多
室チャンバー (前記実施例なら、ば4室チヤンバー)
を用いて成膜することで、制御性が良い成膜が可能とな
り、各チャンバーでの成膜時間が短いので汚染も少なく
、さらに多層構造にするので膜のピンホール密度を大幅
に凍らすことができるという効果がある。
In addition, the plasma excitation CVD method is performed in a vacuum load-lock multi-chamber chamber (in the above example, a four-chamber chamber).
By forming a film using this method, it is possible to form a film with good controllability, the film formation time in each chamber is short, so there is less contamination, and the multilayer structure allows the pinhole density of the film to be significantly reduced. It has the effect of being able to.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図fat、 (blは本発明の一実施例のパッシベ
ーション膜形成工程を示す断面図、第2図はP−5IO
N膜生成時のNeo/ (NzO+ NHa)の値と膜
の内部応力との関係線図である。l:シリコン基板、3二Afii極配腺、4 : P−
PSG膜、5 : P−5i0 Ill、6 : P−
3iONII9.7 : P−5IN Ill。(7P−5VN臭(x109dyns/ci)0.00.2  0.4  0.6→R= NZO/(NZO+NH3)0.8
Figure 1 is a cross-sectional view showing the passivation film forming process of one embodiment of the present invention, Figure 2 is a P-5IO
FIG. 2 is a diagram showing the relationship between the value of Neo/(NzO+NHa) and the internal stress of the film during N film formation. l: Silicon substrate, 32 Afii polar glands, 4: P-
PSG film, 5: P-5i0 Ill, 6: P-
3iONII9.7: P-5IN Ill. (7P-5VN odor (x109dyns/ci) 0.0 0.2 0.4 0.6 →R= NZO/(NZO+NH3) 0.8

Claims (1)

Translated fromJapanese
【特許請求の範囲】[Claims](1)金属配線を形成した半導体基板の上を、燐珪酸ガ
ラス膜、シリコン酸化膜、シリコンオキシナイトライド
膜、シリコン窒化膜を下層よりそれぞれプラズマ励起C
VD法を用いて順次積層してなるパッシベーション膜に
より被覆することを特徴とする半導体装置の製造方法。
(1) Plasma excitation C
1. A method of manufacturing a semiconductor device, comprising covering the device with a passivation film formed by sequentially laminating layers using a VD method.
JP63324331A1988-12-221988-12-22 Manufacturing method of semiconductor devicePendingJPH02170430A (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP63324331AJPH02170430A (en)1988-12-221988-12-22 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP63324331AJPH02170430A (en)1988-12-221988-12-22 Manufacturing method of semiconductor device

Publications (1)

Publication NumberPublication Date
JPH02170430Atrue JPH02170430A (en)1990-07-02

Family

ID=18164593

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP63324331APendingJPH02170430A (en)1988-12-221988-12-22 Manufacturing method of semiconductor device

Country Status (1)

CountryLink
JP (1)JPH02170430A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5780364A (en)*1994-12-121998-07-14Micron Technology, Inc.Method to cure mobile ion contamination in semiconductor processing
EP0798765A3 (en)*1996-03-281998-08-05Shin-Etsu Handotai Company LimitedMethod of manufacturing a semiconductor wafer comprising a dopant evaporation preventive film on one main surface and an epitaxial layer on the other main surface
KR100428876B1 (en)*1996-12-202004-07-27주식회사 하이닉스반도체 Manufacturing method of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5780364A (en)*1994-12-121998-07-14Micron Technology, Inc.Method to cure mobile ion contamination in semiconductor processing
US5943602A (en)*1994-12-121999-08-24Micron Technology, Inc.Method to cure mobile ion contamination in semiconductor processing
US6114222A (en)*1994-12-122000-09-05Micron Technology, Inc.Method to cure mobile ion contamination in semiconductor processing
EP0798765A3 (en)*1996-03-281998-08-05Shin-Etsu Handotai Company LimitedMethod of manufacturing a semiconductor wafer comprising a dopant evaporation preventive film on one main surface and an epitaxial layer on the other main surface
US5834363A (en)*1996-03-281998-11-10Shin-Etsu Handotai Co., Ltd.Method of manufacturing semiconductor wafer, semiconductor wafer manufactured by the same, semiconductor epitaxial wafer, and method of manufacturing the semiconductor epitaxial wafer
KR100428876B1 (en)*1996-12-202004-07-27주식회사 하이닉스반도체 Manufacturing method of semiconductor device

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