【発明の詳細な説明】〔産業上の利用分野〕本発明は半導体装置分野に利用される。[Detailed description of the invention][Industrial application field]The present invention is utilized in the field of semiconductor devices.
本発明は半導体集積回路に関し、特に特定機能を有する
複数の半導体集積回路チップを、他の１つの半導体マス
タ基板上に集積して搭載するいわゆるウェーハインテグ
レーシ、 ン（Ｗａｆｅｒ Ｉｎｔｅｇｒａ−ｔｉｏｎ
） と呼ばれるウェーハ集積型集積回路に関する。The present invention relates to semiconductor integrated circuits, and in particular to so-called wafer integration, in which a plurality of semiconductor integrated circuit chips having specific functions are integrated and mounted on another semiconductor master substrate.
) concerning wafer-integrated integrated circuits.
本発明は、複数個の半導体チップが一つの半導体マスタ
基板に搭載されたウェーハ集積型集積回路において、前記半導体チップを、前記半導体マスタ基板の一主面に
設けられた凹状部に、導電性接着剤で固着された構造と
することにより、半導体チップの放熱性を向上し、基板電位の上昇を押さ
え、かつブレーナ技術を用いて簡単に製造できるように
したものである。The present invention provides a wafer-integrated integrated circuit in which a plurality of semiconductor chips are mounted on one semiconductor master substrate, in which the semiconductor chips are attached to a concave portion provided on one main surface of the semiconductor master substrate using conductive adhesive. The structure is fixed with a chemical agent, which improves the heat dissipation of the semiconductor chip, suppresses the increase in substrate potential, and makes it easy to manufacture using brainer technology.
従来、この種のウェーハ集積型集積回路として、第３図
に示すものがある（例えば、米国、電気電子学会、固体
回路（ＩＥＥＥ Ｊｏｕｒｎａｌ ｏｆ ５ｏｌｉｄ−
３ｔａｔｅＣｉｒｃｕｉｔｓ）ｖｏｌ、５Ｃ−２１ｎｏ
、５１）り８４５〜８５１０ｃｔ、１９８６）。Conventionally, there is a wafer-integrated integrated circuit of this type, as shown in FIG.
3tate Circuits) vol, 5C-21no
, 51) Ri 845-8510ct, 1986).
これは、まず半導体マスタ基板１上の所定領域をエツチ
ングによって貫通孔１２を形成し、その後半導体チップ
２を前記貫通孔に搭載する。このとき接着剤１３によっ
て半導体チップ２を半導体マスタ基板１に固着する。次
に、酸化膜７による通常のプレーナ技術によって、半導
体チップ２間の接続としてチップ接続用パッド５と配線
層６を形成する。そして酸化膜９を保護膜として被覆す
る。First, a through hole 12 is formed by etching a predetermined area on the semiconductor master substrate 1, and then the semiconductor chip 2 is mounted in the through hole. At this time, the semiconductor chip 2 is fixed to the semiconductor master substrate 1 using the adhesive 13. Next, a chip connection pad 5 and a wiring layer 6 are formed as connections between the semiconductor chips 2 by using a normal planar technique using an oxide film 7. Then, an oxide film 9 is applied as a protective film.
前述した従来のウェーハ集積型集積回路には、■ 半導
体チップ１２が接着剤１３を経由して半導体マスタ基板
１１と固着されているため、半導体チップ１２の熱放散
性が悪い、■ 半導体チップ１２の基板電位と半導体マスタ基板１
の基板電位とを等しくする場合、配線層６を経由するた
め基板電位が上昇しやすい、■ 半導体チップ２と半導
体マスタ基板１とを整合性をとって固着できにくく、そ
のためそれぞれの接続界面で半導体チップ２間に凹凸が
生じるため、後々の配線層形成工程でプレーナ技術が適
用し難い、などの欠点があった。The conventional wafer-integrated integrated circuit described above has the following problems: (1) the semiconductor chip 12 is fixed to the semiconductor master substrate 11 via the adhesive 13, so the heat dissipation of the semiconductor chip 12 is poor; Substrate potential and semiconductor master substrate 1
When making the substrate potential equal to the substrate potential of There were drawbacks such as the difficulty of applying planar technology in the later wiring layer formation process because of the unevenness between the two chips.
本発明の目的は、前記の欠点を除去することにより、半
導体チップの放熱性がよく、基板電位の上昇を押さえ、
かつプレーナ技術を用いて簡単に製造できるウェーハ集
積型集積回路を提供することにある。The purpose of the present invention is to eliminate the above-mentioned drawbacks, thereby improving the heat dissipation of the semiconductor chip, suppressing the rise in substrate potential, and
Another object of the present invention is to provide a wafer-integrated integrated circuit that can be easily manufactured using planar technology.
本発明は、一導電型の半導体基板に回路または素子が形
成された複数個の半導体チップと、この半導体チップが
それぞれの所定位置に搭載された一導電型の半導体マス
タ基板とを含むウェーハ集積型集積回路において、前記
半導体チップは、前記半導体マスタ基板の一主面の所定
の位置に設けられた凹状部に導電性接着剤により固着さ
れたことを特徴とする。The present invention relates to a wafer integrated type that includes a plurality of semiconductor chips in which circuits or elements are formed on semiconductor substrates of one conductivity type, and a semiconductor master substrate of one conductivity type on which the semiconductor chips are mounted at respective predetermined positions. In the integrated circuit, the semiconductor chip is fixed to a concave portion provided at a predetermined position on one principal surface of the semiconductor master substrate using a conductive adhesive.
半導体チップは、半導体マスタ基板の一主面の所定領域
に、例えば異方性エツチングによりあらかじめ設けられ
た凹状部に、例えばＡｇペーストなどの導電性接着剤で
固着される。The semiconductor chip is fixed to a predetermined region of one main surface of the semiconductor master substrate in a recessed portion previously provided by, for example, anisotropic etching, using a conductive adhesive such as, for example, Ag paste.
従って、半導体チップと半導体マスタ基板とは熱的およ
び電気的に一体となり、半導体チップの放熱性の向上を
図り、基板電位の上昇を押さえることが可能となる。さ
らに、凹状部は均一な形状に形成でき、プレーナ技術を
用いて全体を簡単に製造することが可能となる。Therefore, the semiconductor chip and the semiconductor master substrate are thermally and electrically integrated, and it is possible to improve the heat dissipation of the semiconductor chip and suppress the increase in substrate potential. Furthermore, the concave portion can be formed into a uniform shape, and the whole can be easily manufactured using planar technology.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の第一実施例を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention.
本第−実施例は、一導電型の半導体基板に回路または素
子が形成された複数個の半導体チップ２と、この半導体
チップ２をそれぞれの所定位置に搭載した一導電型の半
導体マスタ基板１とを含むウェーハ集積型集積回路にお
いて、半導体チップ２は、半導体マスタ基板１の一主面の所定
の位置に設けられた凹状部１１に導電性接着剤としての
Ａｇペースト３により固着された構造を有する。The present embodiment includes a plurality of semiconductor chips 2 in which circuits or elements are formed on semiconductor substrates of one conductivity type, and a semiconductor master substrate 1 of one conductivity type on which the semiconductor chips 2 are mounted at respective predetermined positions. In a wafer-integrated integrated circuit including: The semiconductor chip 2 has a structure in which the semiconductor chip 2 is fixed to a concave portion 11 provided at a predetermined position on one principal surface of the semiconductor master substrate 1 with an Ag paste 3 as a conductive adhesive. .
次に、本第−実施例の製造方法について説明する。Next, the manufacturing method of this embodiment will be explained.
厚さ数ｍｍの半導体マスタ基板１の特定領域を、異方性
エツチングで除去して凹状部１１を形成する。A specific region of a semiconductor master substrate 1 having a thickness of several mm is removed by anisotropic etching to form a concave portion 11 .
この凹状部１１の深さは搭載半導体チップ２の厚さ、例
えば５００μｍ程度で、凹状部の底部の大きさは半導体
チップ面積に等しくなるよう、レジストをマスタとして
ＫＯＨ等による異方性エツチングを行う。適当なエツチ
ングを行うことにより、半導体チップ２の搭載時の位置
決めが正確にできる。半導体マスタ基板１の導電型は、
搭載する半導体チップの導電型に一致させることが必要
であり、また低抵抗率であることが望ましい。The depth of this recessed portion 11 is the thickness of the mounted semiconductor chip 2, for example, about 500 μm, and anisotropic etching is performed using KOH or the like using a resist as a master so that the bottom size of the recessed portion is equal to the area of the semiconductor chip. . By performing appropriate etching, the semiconductor chip 2 can be accurately positioned during mounting. The conductivity type of the semiconductor master substrate 1 is
It is necessary to match the conductivity type of the semiconductor chip to be mounted, and it is desirable that the resistivity be low.
搭載する半導体チップ２は、すでに通常のプレーナ技術
等によって回路が形成されている。この半導体チップ２
を、導電性接着剤として、例えばＡｇペースト３を用い
て半導体マスタ基板１に固着させる。次に、例えばポリ
イミド樹脂４等の絶縁性充填剤で、異方性エツチングに
よって形成された凹状部と半導体チップ２間の空隙を埋
める。そして、チップ接続用パッド５を例えばＡＩから
なる配線層６で接続し、それぞれの半導体チップ２を相
互に接続する。A circuit has already been formed on the semiconductor chip 2 to be mounted using a normal planar technology or the like. This semiconductor chip 2
is fixed to the semiconductor master substrate 1 using, for example, Ag paste 3 as a conductive adhesive. Next, the gap between the semiconductor chip 2 and the concave portion formed by the anisotropic etching is filled with an insulating filler such as polyimide resin 4, for example. Then, the chip connection pads 5 are connected with a wiring layer 6 made of, for example, AI, and the respective semiconductor chips 2 are connected to each other.
次に、配線層６上の所定の位置に、ケース接続用パッド
８となる部分を残して、全面に保護膜として酸化膜９を
形成する。Next, at a predetermined position on the wiring layer 6, an oxide film 9 is formed as a protective film over the entire surface, leaving a portion that will become the case connection pad 8.
以上のように、通常のプレーナ技術等で製作された小規
模な機能を有する半導体チップ２を、あらかじめ他の半
導体基板マスタ基板１上に、矩形で凹状に作られた凹状
部１１に搭載し、その後再びプレーナ技術等によって配
線を施して半導体チップ２それぞれを相互に結線すれば
、機能の複合化した新しいウェーハ集積型集積回路を実
現することができる。As described above, the semiconductor chip 2 having a small-scale function manufactured by ordinary planar technology etc. is mounted in advance on another semiconductor substrate master substrate 1 in the concave portion 11 made in a rectangular concave shape, Thereafter, by interconnecting the semiconductor chips 2 by wiring again using planar technology or the like, it is possible to realize a new wafer-integrated integrated circuit with multiple functions.
なお、第１図は、行あるいは列の単方向のみの構造を示
す縦断面図であるが、行列状に半導体チップ２を同様に
搭載できる。Although FIG. 1 is a vertical cross-sectional view showing the structure in only one direction of rows or columns, the semiconductor chips 2 can be similarly mounted in a matrix.
第２図は本発明の第二実施例を示す縦断面図である。本
第二実施例は、半導体チップ２相互の結線を、半導体マ
スタ基板１上の表面に形成された配線層６を介してボン
ディング線１０で接続した構造としたものである。本第
二実施例では、半導体チップ相互の接続をボンディング
線１０で行うため、配線層６で接続する第一実施例に比
し、簡単に製造できる利点がある。FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention. The second embodiment has a structure in which semiconductor chips 2 are connected to each other by bonding wires 10 via a wiring layer 6 formed on the surface of a semiconductor master substrate 1. In the second embodiment, since the semiconductor chips are connected to each other by the bonding wires 10, there is an advantage that the semiconductor chips can be easily manufactured compared to the first embodiment in which the semiconductor chips are connected by the wiring layer 6.
本発明の特徴は、第１図および第２図において、半導体
チップ２が、半導体マスタ基板１の凹状部１１にＡｇペ
ースト（導電性接着剤）３で固着された構造を有するこ
とにある。A feature of the present invention is that, as shown in FIGS. 1 and 2, the semiconductor chip 2 has a structure in which the semiconductor chip 2 is fixed to the concave portion 11 of the semiconductor master substrate 1 with Ag paste (conductive adhesive) 3.
以上説明したように、本発明は、半導体マスタ基板上の
貫通までは至らない凹状部を異方性エツチングで形成す
ることにより、半導体チップを精度よく搭載でき、その
結果半導体チップ間接続のためのプレーナ技術が適用し
やすい効果がある。As explained above, the present invention enables semiconductor chips to be mounted with high precision by forming concave portions that do not penetrate through the semiconductor master substrate by anisotropic etching, thereby making it possible to mount semiconductor chips with high accuracy. Planar technology has the effect of being easy to apply.
さらに、半導体チップと半導体マスタ基板は、凹状部底
面の導電性ペーストで接続されるため、半導体チップの
熱放散性が向上し、半導体チップと半導体マスタ基板を
共通電位（共通グランド）でとりやすく基板電位を上昇
を押さえる効果がある。Furthermore, since the semiconductor chip and the semiconductor master board are connected with the conductive paste on the bottom of the recessed part, the heat dissipation of the semiconductor chip is improved, and it is easy to connect the semiconductor chip and the semiconductor master board to a common potential (common ground). It has the effect of suppressing the increase in potential.
第１図は本発明の第一実施例を示す縦断面図。第２図は本発明の第二実施例を示す縦断面図。第３図は従来例を示す縦断面図。１・・・半導体マスタ基板、２・・・半導体チップ、３
・・・Ａｇペースト、４・・・ポリイミド樹脂、５・・
・チップ接続用パッド、６・・・配線層、７．９・・・
酸化膜、８・・・ケース接続用パッド、１０・・・ボン
ディング線、１１・・・凹状部、１２・・・貫通孔、１
３・・・接着剤。特許出願人 日本電気株式会社、−代理人 弁理士 井 出 直 孝FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention. FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention. FIG. 3 is a longitudinal sectional view showing a conventional example. 1... Semiconductor master board, 2... Semiconductor chip, 3
...Ag paste, 4...Polyimide resin, 5...
・Chip connection pad, 6... wiring layer, 7.9...
Oxide film, 8... Case connection pad, 10... Bonding wire, 11... Concave portion, 12... Through hole, 1
3...Adhesive. Patent applicant: NEC Corporation, − Agent: Naotaka Ide, patent attorney
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63086381AJPH01258458A (en) | 1988-04-08 | 1988-04-08 | Wafer integration type integrated circuit |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63086381AJPH01258458A (en) | 1988-04-08 | 1988-04-08 | Wafer integration type integrated circuit |
| Publication Number | Publication Date |
|---|---|
| JPH01258458Atrue JPH01258458A (en) | 1989-10-16 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63086381APendingJPH01258458A (en) | 1988-04-08 | 1988-04-08 | Wafer integration type integrated circuit |
| Country | Link |
|---|---|
| JP (1) | JPH01258458A (en) |
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