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JPH01191424A - Resist hardening method - Google Patents

Resist hardening method

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Publication number
JPH01191424A
JPH01191424AJP1462488AJP1462488AJPH01191424AJP H01191424 AJPH01191424 AJP H01191424AJP 1462488 AJP1462488 AJP 1462488AJP 1462488 AJP1462488 AJP 1462488AJP H01191424 AJPH01191424 AJP H01191424A
Authority
JP
Japan
Prior art keywords
resist
ion
semiconductor wafer
curing
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1462488A
Other languages
Japanese (ja)
Inventor
Katsuo Koike
小池 勝夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba CorpfiledCriticalToshiba Corp
Priority to JP1462488ApriorityCriticalpatent/JPH01191424A/en
Publication of JPH01191424ApublicationCriticalpatent/JPH01191424A/en
Pendinglegal-statusCriticalCurrent

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Abstract

PURPOSE:To effectively cure a resist to a predetermined depth in a short time without damages of the resist, to suppress gas discharge in succeeding processes and to prevent an element and a manufacturing apparatus from being contaminated by employing an ion radiation for curing the resist. CONSTITUTION:After a resist is formed on a semiconductor wafer, it is placed on a stage 14 in a processor 10 evacuated in vacuum by an evacuation system 15, and a whole semiconductor wafer 13 is radiated with Ar ion beam radiated from an ion source 11. Thus, gas is discharged from the resist by an ion collision, the resist can be cured in a short time without collapse of its pattern, and gas discharge in a later ion implanting step is eliminated by the curing, thereby preventing an element and a manufacturing apparatus form being contaminated.

Description

Translated fromJapanese

【発明の詳細な説明】[発明の目的](産業上の利用分野)本発明は、半導体装置の製造プロセスにおける、パター
ン形成されたレジストの硬化処理方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for curing a patterned resist in a semiconductor device manufacturing process.

(従来の技術)半導体装置の製造に欠かせないプロセスとして、リソグ
ラフィ工程がある。この場合、半導体ウェーハ上に形成
したレジスト・パターンの形状を保持するため通常、1
30℃程度に温度を上昇させてレジストを硬化させるベ
ーキングが行われる。最近の半導体集積回路の高密度化
、高集積化に伴い、レジスト材料も改良されているが、
一般にレジストは耐熱性が悪く、ベーキングによってパ
ターンが崩れる、という問題がある。これは、微細加工
を困難にする。このためベーキングに代って紫外光の照
射によるレジスト硬化処理法も採用されている。しかし
ながら、紫外光照射による硬化はレジスト表面に止まる
。このためその後このレジスト・パターンをマスクとし
て用いたイオン注入等を行なうと、イオンによってレジ
スト内部まで衝撃される結果、レジストからの異常なガ
ス放出があり、これが素子や製造装置の汚染をもたらし
、素子の信頓性を劣化させる。また紫外光照射は、効果
的に行なうためには現状ではウェーハ1枚につき2分近
くかかり、生産性が悪い。
(Prior Art) A lithography process is an essential process for manufacturing semiconductor devices. In this case, in order to maintain the shape of the resist pattern formed on the semiconductor wafer, usually one
Baking is performed to harden the resist by raising the temperature to about 30°C. With the recent increase in density and integration of semiconductor integrated circuits, resist materials have also been improved.
Generally, resists have poor heat resistance, and the problem is that the pattern collapses when baked. This makes microfabrication difficult. For this reason, a resist hardening method using ultraviolet light irradiation is also used instead of baking. However, curing due to ultraviolet light irradiation is limited to the resist surface. For this reason, when ion implantation is subsequently performed using this resist pattern as a mask, the inside of the resist is bombarded by ions, resulting in abnormal gas release from the resist, which contaminates devices and manufacturing equipment. deteriorate the credibility of Furthermore, in order to effectively perform ultraviolet light irradiation, it currently takes nearly two minutes per wafer, resulting in poor productivity.

(発明が解決しようとする課題)以上のように従来のレジスト硬化処理法では、ベーキン
グではパターンのくずれがあり、紫外光照射ではその後
の工程でガス放出による汚染が生じる、等の問題があっ
た。
(Problems to be Solved by the Invention) As described above, conventional resist hardening processing methods have problems such as pattern distortion during baking and contamination due to gas release during subsequent steps when irradiated with ultraviolet light. .

本発明は、この様な問題を解決した、レジスト硬化処理
方法を提供することを目的とする。
An object of the present invention is to provide a resist hardening treatment method that solves these problems.

[発明の構成](課題を解決するための手段)本発明は、半導体ウェーハ上にレジストをパターン形成
した後、このウェーハに真空中でイオン照射を行なうこ
とを特徴とする。
[Structure of the Invention] (Means for Solving the Problems) The present invention is characterized in that after patterning a resist on a semiconductor wafer, the wafer is irradiated with ions in a vacuum.

(作用)本発明によれば、イオン衝撃によってレジストからガス
が放出され、レジストは表面から一定の深さまで硬化し
て安定化する。本発明者らの実験によれば、パターンの
崩れを生じることなく、ごく短時間の処理でレジストを
硬化させることができる。そしてこの様な硬化処理を施
すことにより、その後のイオン注入工程でのガス放出が
なくなり、素子や製造装置の汚染を防止することができ
る。
(Function) According to the present invention, gas is released from the resist by ion bombardment, and the resist is hardened and stabilized from the surface to a certain depth. According to experiments conducted by the present inventors, the resist can be hardened in a very short time without causing pattern collapse. By performing such a hardening treatment, gas release during the subsequent ion implantation step is eliminated, and contamination of the device and manufacturing equipment can be prevented.

(実施例)以下、本発明の詳細な説明する。(Example)The present invention will be explained in detail below.

第1図は、本発明の一実施例に用いたレジスト硬化処理
装置である。10は処理装置であり、内部は排気系15
により真空排気されるようになっている。11はイオン
源であり、このイオン源11から引出されたArイオン
ビームは、静電走査系12を経て、ステージ14上に載
置された半導体ウェーハ13の全面に照射される。半導
体つ工−ハ13表面には所望のレジスト・パターンが形
成されている。
FIG. 1 shows a resist hardening processing apparatus used in one embodiment of the present invention. 10 is a processing device, and inside is an exhaust system 15
It is designed to be evacuated. Reference numeral 11 denotes an ion source, and an Ar ion beam extracted from the ion source 11 passes through an electrostatic scanning system 12 and is irradiated onto the entire surface of a semiconductor wafer 13 placed on a stage 14. A desired resist pattern is formed on the surface of the semiconductor chip 13.

このように構成された装置を用い、30keVに加速さ
れた5mAのArイオンビームを走査して、1μmのレ
ジストを塗布、バターニングした半導体ウェーハに照射
した。なおレジストはT S MRB8QO(東京応ぽ
化デ製))を用いてこれを塗布後90℃、270seC
のプリベークを施し、紫外線露光でパターン露光した。
Using the apparatus configured as described above, a 5 mA Ar ion beam accelerated to 30 keV was scanned and irradiated onto a semiconductor wafer coated with a 1 μm resist and patterned. The resist was coated using T S MRB8QO (manufactured by Tokyo Opoka De Co., Ltd.) and heated at 90°C and 270sec.
The film was prebaked and pattern exposed using ultraviolet light.

現像は、現像液N5D−73(東京応化製)を使用した
。僅か数十秒の処理時間で効果的なレジストの硬化処理
が行われた。第2図は、このイオン照射中の装置の真空
度の変化を示す。イオン照射開始直後にガス放出による
真空度の低下が生じるが、開始後40秒でレジストから
のガス放出はなくなり、レジスト硬化処理が終了する。
For development, developer N5D-73 (manufactured by Tokyo Ohka) was used. Effective resist hardening treatment was performed in just a few tens of seconds. FIG. 2 shows changes in the degree of vacuum of the apparatus during this ion irradiation. Immediately after the start of ion irradiation, the degree of vacuum decreases due to gas release, but gas release from the resist stops 40 seconds after the start, and the resist hardening process ends.

この実施例によりレジスト硬化したウエーノ1を電子顕
微鏡で観測した結果、表面から約1000人の深さまで
硬化しており、形状のダレやノ1ガレも認められなかっ
た。またこのようにレジスト硬化処理を施したウェーハ
をイオン注入装置に装着し、ヒ素イオンを50keVに
加速して、5×1015/cm2注入したが、イオン打
込み室の真空度の低下はな(、またレジスト形状に異常
もなかった。
As a result of observing the resist hardened Ueno 1 according to this example using an electron microscope, it was found that the resist was hardened to a depth of about 1000 mm from the surface, and no sagging or cracking of the shape was observed. Furthermore, the wafer subjected to the resist hardening process was loaded into an ion implanter, and arsenic ions were accelerated to 50 keV and implanted at 5 x 1015/cm2, but the degree of vacuum in the ion implantation chamber did not decrease (and There was no abnormality in the resist shape.

以上のようにこの実施例によれば、レジスト・パターン
の形崩れを生じることなく、ごく短時間の処理でレジス
トの安定化が図られる。またこのレジスト処理工程でレ
ジストからガスを放出させるので、その後のイオン注入
工程等でのガス放出をなくして、素子や装置の汚染を防
止することができる。
As described above, according to this embodiment, the resist pattern can be stabilized in a very short period of time without causing deformation of the resist pattern. Further, since gas is released from the resist in this resist processing step, gas is not released in the subsequent ion implantation step, etc., and contamination of elements and devices can be prevented.

本発明は上記実施例に限られるものではない。The present invention is not limited to the above embodiments.

例えば、照射するイオンはArイオンに限らず、他の各
種不活性ガスを初め、素子作製に影響のないイオンを用
いることができる。またイオンビームを偏向して走査す
る代わりに、ウニ /Xを駆動してもよいし、両者を併
用することもできる。
For example, the ions to be irradiated are not limited to Ar ions, and other various inert gases as well as ions that do not affect device fabrication can be used. Furthermore, instead of deflecting and scanning the ion beam, the urchin/X may be driven, or both may be used in combination.

その池水発明は、その趣旨を逸脱しない範囲で種々変形
して実施することができる。
The pond water invention can be implemented with various modifications without departing from the spirit thereof.

[発明の効果]以上述べたように本発明によれば、レジスト硬化処理に
イオン照射を用いることにより、レジストの形崩れを伴
うことなく、短時間で効果的に所定深さまで硬化させる
ことができ、またその後の処理工程でのレジストからの
ガス放出も抑制して素子や製造装置の汚染を防止するこ
とができる。
[Effects of the Invention] As described above, according to the present invention, by using ion irradiation for resist hardening treatment, it is possible to effectively harden the resist to a predetermined depth in a short time without causing the resist to lose its shape. Furthermore, gas release from the resist during subsequent processing steps can be suppressed to prevent contamination of elements and manufacturing equipment.

従ってまた本発明によれば、半導体装置の一層の微細加
工が可能になり、集積回路の高集積化を図ることができ
る。
Therefore, according to the present invention, even finer processing of semiconductor devices is possible, and higher integration of integrated circuits can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に用いたレジスト硬化処理装
置の概略構成を示す図、第2図は実施例におけるレジス
トからのガス放出の様子を示す図である。10・・・処理装置、11・・・イオン源、12・・・
静電走査系、13・・・半導体ウェーハ、14・・・ス
テージ、15・・・排気系。出願人代理人 弁理士 鈴江武彦第1図第2図
FIG. 1 is a diagram showing a schematic configuration of a resist hardening processing apparatus used in an example of the present invention, and FIG. 2 is a diagram showing a state of gas release from a resist in the example. 10... Processing device, 11... Ion source, 12...
Electrostatic scanning system, 13... semiconductor wafer, 14... stage, 15... exhaust system. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

Translated fromJapanese
【特許請求の範囲】[Claims] 半導体ウェーハにレジスト・パターンを形成した後、
そのウェーハ表面に真空中でイオン照射を行なうことを
特徴とするレジスト硬化処理方法。
After forming the resist pattern on the semiconductor wafer,
A resist hardening processing method characterized by irradiating the wafer surface with ions in a vacuum.
JP1462488A1988-01-271988-01-27 Resist hardening methodPendingJPH01191424A (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP1462488AJPH01191424A (en)1988-01-271988-01-27 Resist hardening method

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP1462488AJPH01191424A (en)1988-01-271988-01-27 Resist hardening method

Publications (1)

Publication NumberPublication Date
JPH01191424Atrue JPH01191424A (en)1989-08-01

Family

ID=11866358

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP1462488APendingJPH01191424A (en)1988-01-271988-01-27 Resist hardening method

Country Status (1)

CountryLink
JP (1)JPH01191424A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS59152621A (en)*1983-02-211984-08-31Nec Corp ion implanter
JPS63133629A (en)*1986-11-261988-06-06Nec CorpManufacture of integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS59152621A (en)*1983-02-211984-08-31Nec Corp ion implanter
JPS63133629A (en)*1986-11-261988-06-06Nec CorpManufacture of integrated circuit device

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