JPH01149464A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To allow an additional capacity to decrease without a change in the area of an element by a method wherein the element includes a first buried layer containing an impurity opposite in conductivity type to a semiconductor substrate of one conductivity type it finds itself on and a semiconductor layer of the opposite conductivity type formed on the first buried layer. CONSTITUTION:Between an N<+>-type buried collector layer C1, designed to reduce collector series resistance and positioned under an N<-> semiconductor layer C2, and a P-type semiconductor substrate S, there exists an N<->-type buried layer C3. This design reduces collector.substrate additional capacity. Impurity concentration in the N<->-type buried layer C3 is an order of magnitude higher than that in the semiconductor substrate S. The concentration is so designed that it gently decreases toward the semiconductor substrate S. Such a gradual decrease in distribution of a low-concentration impurity may be achieved when a small quantity of impurity ions is implanted into the substrate S, before the epitaxial growth of the N<->-type semiconductor layer C2, at a high energy of several 100keV and is allowed to be diffused in a later thermal process. With the energy for the ion implantation being quite high, crystals are hardly damaged in the vicinity of the substrate surface.

Description

Translated fromJapanese

【発明の詳細な説明】〔産業上の利用分野〕本発明は半導体装置に関し、特にバイポーラ型トランジ
スタの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a bipolar transistor.

〔従来の技術〕[Conventional technology]

従来半導体装置を構成する基本バイポーラトランジスタ
は、第５図に示すように、Ｐ型半導体基板Ｓ上に形成さ
れた不純物濃度の高いＮ＋型埋込みコレクタＮＣ１と、
その上の比較的不純物濃度の低いＮ−型半導体層Ｃ２の
表面に形成されたＰ形ベース領域Ｂと、このベース領域
中に形成されたエミッタ領域Ｅにより構成されていた。As shown in FIG. 5, a basic bipolar transistor constituting a conventional semiconductor device includes an N+ type buried collector NC1 with a high impurity concentration formed on a P type semiconductor substrate S, and
It consisted of a P-type base region B formed on the surface of an N-type semiconductor layer C2 having a relatively low impurity concentration thereon, and an emitter region E formed in this base region.

このトランジスタ素子において、Ｎ＋型埋込みコレクタ
層Ｃ！はコレクタ直列抵抗を下げるために設けられてい
るものである。この埋込コレクタ層Ｃ１は、低抵抗化の
ために高不純物濃度（２１０２°ｃｍ−３）である必要
がある。In this transistor element, the N+ type buried collector layer C! is provided to reduce the collector series resistance. This buried collector layer C1 needs to have a high impurity concentration (2102[deg.]cm-3) in order to reduce the resistance.

また、通常基板電位は半導体装置の最低電位に設定され
ており、動作時には、コレクタ・基板間に数ボルトの電
圧が印加されている。この逆バイアスのほとんどは、コ
レクタ・基板間のＰＮ接合面にかかり、接合面の空乏層
を広げ基板への漏れ電流を押える働きをする。しかし、
この空乏層は同時に、付加容量として働くので空乏層幅
は大きい方が望ましい。Further, the substrate potential is usually set to the lowest potential of the semiconductor device, and during operation, a voltage of several volts is applied between the collector and the substrate. Most of this reverse bias is applied to the PN junction between the collector and the substrate, and serves to spread the depletion layer at the junction and suppress leakage current to the substrate. but,
Since this depletion layer also functions as an additional capacitance, it is desirable that the width of the depletion layer be large.

第３図に従来のバイポーラトランジスタのＰ型半導体基
板の深さ方向に対する不純物濃度分布と空乏層の広がり
を示す。FIG. 3 shows the impurity concentration distribution and the spread of the depletion layer in the depth direction of the P-type semiconductor substrate of a conventional bipolar transistor.

第３図において空乏層の幅Ｘは、ＰＮ接合点Ｘ、を中心
にＮ型及びＰ型側に電荷量の積がつり合う点ＸＡ、ＸＤ
まで広がり、この和になっていることは周知のとおりで
ある。埋込コレクタ層の不純物濃度が高いためＸＡは小
さく、不純物濃度の比較的低い基板側のＸＤにより空乏
層の幅Ｘは決まってしまう。In Figure 3, the width X of the depletion layer is the point XA, XD where the product of charges is balanced on the N-type and P-type sides around the PN junction X.
As is well known, it has expanded to this sum. Since the impurity concentration of the buried collector layer is high, XA is small, and the width X of the depletion layer is determined by XD on the substrate side where the impurity concentration is relatively low.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記した従来のバイポーラトランジスタにおいては、Ｎ
＋型埋込みコレクタ層Ｃ１は、トランジスタ素子自体と
等しい大面積を有しており、埋込みコレクタ層と半導体
基板間のＰＮ接合による付加容量は、他のＰＮ接合のそ
れに比べ数倍になっている。この容量増加は、高周波特
性を劣化させトランジスタのスイッチング速度を遅らせ
る大きな原因となる。すなわち、エミッタからコレクタ
への少数キャリアの伝搬遅延速度を増加させてしまうの
である。In the conventional bipolar transistor mentioned above, N
The +-type buried collector layer C1 has an area as large as the transistor element itself, and the additional capacitance due to the PN junction between the buried collector layer and the semiconductor substrate is several times larger than that of other PN junctions. This increase in capacitance is a major cause of deteriorating high frequency characteristics and slowing down the switching speed of the transistor. In other words, the propagation delay speed of minority carriers from the emitter to the collector increases.

上記のことよりトランジスタ動作の高速化を考えたとき
、素子自体の面積縮少化が考えられるが、これは、トラ
ンジスタ製造上のマスクバタンマージンの縮少化が必要
なため、また、扱える電力レベルの確保のため容易では
ない。Based on the above, when considering speeding up transistor operation, it is possible to reduce the area of the element itself, but this is because it is necessary to reduce the mask button margin in transistor manufacturing, and also because it requires a reduction in the power level that can be handled. It is not easy to ensure that

本発明の目的は、素子自体の面積を変えることなく埋込
コレクタ層と半導体基板間の付加容量を低減させたバイ
ポーラトランジスタを有する半導体装置を提供すること
にある。An object of the present invention is to provide a semiconductor device having a bipolar transistor in which additional capacitance between a buried collector layer and a semiconductor substrate is reduced without changing the area of the element itself.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、−導電型半導体基板上に形成さ
れた逆導電型低濃度不純物を含む第１の埋込層と、該第
１の埋込層上に形成された逆導電型高濃度不純物を含む
第２の埋込層と、該第２の埋込層上に形成された逆導電
型半導体層とを含んで構成される。The semiconductor device of the present invention includes: a first buried layer containing a low concentration impurity of opposite conductivity type formed on a semiconductor substrate of conductivity type; and a high concentration impurity of opposite conductivity type formed on the first buried layer; The semiconductor device includes a second buried layer containing impurities and an opposite conductivity type semiconductor layer formed on the second buried layer.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第１図
は本発明の第１の実施例の断面図である。Next, the present invention will be explained with reference to the drawings. FIG. 1 is a sectional view of a first embodiment of the invention.

第１図において、比較的低濃度のＰ型半導体基板Ｓ上に
はコレクタ領域となるＮ−型埋込層Ｃ３とＮ＋型埋込み
コレクタ層Ｃ１とエピタキシャル層からなるＮ型半導体
層Ｃ２が形成されており、この半導体層表面にＰ型ベー
ス領域Ｂと、さらにその中にＮ＋型エミッタ領域Ｅが形
成されている。そしてこれらの埋込みコレクタ、ベース
、エミッタの各領域にそれぞれ金属電極り、、Ｄ２゜Ｄ
３が設けである。尚、Ｉｌは半導体表面と金属配線との
絶縁層、■２は素子間絶縁体である。In FIG. 1, an N-type buried layer C3 serving as a collector region, an N+-type buried collector layer C1, and an N-type semiconductor layer C2 consisting of an epitaxial layer are formed on a relatively lightly doped P-type semiconductor substrate S. A P type base region B is formed on the surface of this semiconductor layer, and an N+ type emitter region E is further formed therein. Then, metal electrodes are placed on each of these buried collector, base, and emitter regions, respectively.D2゜D
3 is a provision. Note that Il is an insulating layer between the semiconductor surface and metal wiring, and 2 is an inter-element insulator.

このように構成された第１の実施例においては、実質的
なコレクタ部分であるＮ−型半導体層Ｃ２の下層に位置
するコレクタ直列抵抗低減用のＮ＋型埋込みコレクタＫ
Ｊ　Ｃｔと、Ｐ型半導体基板Ｓとの間に、Ｎ−型埋込み
層Ｃ３が設けであるため、コレクタ・基板間の付加容量
は減少する。この領域の深さ方向に対する不純物濃度分
布の様子を第４図に示す。In the first embodiment configured in this manner, an N+ type buried collector K for reducing collector series resistance is located below the N- type semiconductor layer C2 which is a substantial collector portion.
Since the N-type buried layer C3 is provided between J Ct and the P-type semiconductor substrate S, the additional capacitance between the collector and the substrate is reduced. FIG. 4 shows the impurity concentration distribution in the depth direction of this region.

第４図において、Ｎ＝型埋込み層Ｃ３は、基板不純物濃
度より一桁程度高い不純物濃度で基板側に向って緩やか
に減少するように作られている。In FIG. 4, the N= type buried layer C3 is formed to have an impurity concentration that is about one order of magnitude higher than the substrate impurity concentration and gradually decreases toward the substrate side.

このような低濃度での緩やかな不純物分布ＩＩは、Ｎ−
型半導体層Ｃ２をエピタキシャル成長により形成する前
に、基板中にイオン注入法により高エネルギー（〜数１
００ｋｅＶ）、低注入量で不純物をドープし、その後の
熱処理工程での拡散により形成することができる。イオ
ン注入のエネルギーは、極めて大きいため基板表面付近
での結晶ダメージはほとんどない。このことは、エピタ
キシャル成長工程において重要である。The gradual impurity distribution II at such a low concentration is due to N-
Before forming the type semiconductor layer C2 by epitaxial growth, a high energy (~several 1
00 keV), the impurity can be doped at a low dose and then diffused in a subsequent heat treatment process. Since the energy of ion implantation is extremely high, there is almost no crystal damage near the substrate surface. This is important in the epitaxial growth process.

このように構成された第１の実施例のコレクタ・基板間
に逆バイアスが印加される動作時においては、コレクタ
・基板間におけるＰＮ接合での空乏層の広がりは、接合
点Ｘ、より基板方向へのＸＤは従来型とほとんど変らな
いが、埋込みコレクタ方向へのＸＡは、Ｎ−型埋込層Ｃ
８が緩やかな濃度匂配で存在するため大きく広がり、空
乏層の幅Ｘは増加し、コレクタ・基板間の付加容量は減
少する。。During operation in which a reverse bias is applied between the collector and the substrate of the first embodiment configured as described above, the depletion layer at the PN junction between the collector and the substrate spreads from the junction point X toward the substrate. The XD toward the buried collector is almost the same as the conventional type, but the XA toward the buried collector is due to the N-type buried layer C.
8 exists with a gentle concentration gradient, it widens greatly, the width X of the depletion layer increases, and the additional capacitance between the collector and the substrate decreases. .

第２図は本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.

本第２の実施例ではＮ−型埋込み層Ｃ８が素子間分離用
の絶縁体重２の近傍に形成されていない所以外は第１の
実施例と同じである。The second embodiment is the same as the first embodiment except that the N-type buried layer C8 is not formed near the insulating weight 2 for isolation between elements.

Ｎ−型埋込層Ｃ３をこの絶縁体重２に接触する大きさ、
つまりＮ−型埋込コレクタ層Ｃ１直下全面に形成した場
合、素子自体の深さが増すため素子間絶縁体Ｉ２の深さ
もそれに準じて深くしなければならない。この第２の実
施例では、素子間絶縁体Ｉ２近傍でコレクタ領域はｃ、
、、Ｃ２だ°けとなり、従来型と変らなくなるため、こ
の絶縁体■２の深さは従来型と同程度でよく、かつ、コ
レクタ・基板間の付加容量を充分小さくできる利点があ
る。The size of the N-type buried layer C3 to be in contact with this insulating weight 2,
In other words, when it is formed over the entire surface directly under the N-type buried collector layer C1, the depth of the element itself increases, and therefore the depth of the inter-element insulator I2 must be increased accordingly. In this second embodiment, the collector region near the inter-element insulator I2 is c,
, C2, which is the same as that of the conventional type, the depth of the insulator 2 may be the same as that of the conventional type, and there is an advantage that the additional capacitance between the collector and the substrate can be sufficiently small.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、−導電型半導体基板と逆
導電型高濃度不純物を含む埋込層との間に逆導電型低濃
度不純物を含む埋込み層を形成することにより、コレク
タ・基板間のＰＮ接合により生じる空乏層のコレクタ側
への広がりを増加させ、コレクタ・基板間付加容量の低
減を実現できる。このことは、トランジスタ動作のスイ
ッチング速度の高速化に効果がある。特に素子の高集積
化を図り多数のトランジスタを動作させる場合の効果は
大きくなる。As explained above, the present invention provides a structure between the collector and the substrate by forming a buried layer containing low concentration impurities of opposite conductivity type between a semiconductor substrate of conductivity type and a buried layer containing high concentration impurities of opposite conductivity type. By increasing the spread of the depletion layer generated by the PN junction toward the collector side, it is possible to reduce the additional capacitance between the collector and the substrate. This has the effect of increasing the switching speed of transistor operation. In particular, the effect becomes greater when the elements are highly integrated and a large number of transistors are operated.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図は、本発明の第１及び第２の実施例の
断面図、第３図及び第４図は従来の半導体装置及び本発
明の実施例における埋込みコレクタ層付近での深さ方向
に対する不純物濃度の分布及び空乏層の広がりを表わし
た図、第５図は従来の半導体装置の断面図である。工１・・・絶縁層、Ｉ２・・・素子間絶縁体、Ｓ・・・
Ｐ型半導体基板、Ｃ１・・・Ｎ＋型埋込みコレクタ層、
Ｃ２・・・Ｎ−型半導体層、Ｃ３・・・Ｎ−型埋込み層
、Ｂ・・・Ｐ型ベース領域、Ｅ・・・Ｎ＋型エミッタ領
域、Ｄ、、Ｄ２．Ｄ、・・・金属電極、Ｘ、・・・コレ
クタ・基板間のＰＮ接合の深さ、Ｘ・・・コレクタ基板
間の空乏層幅、Ｎｓ・・・基板不純物濃度１、ＸＡ・・
・Ｘ」よりＮ型半導体中への空乏層の広がり、ｘＤ・・
・ＸＪよりＰ型半導体中への空乏層の広がり、ＩＩ・・
・Ｎ−型埋込み層中の不純物の分布。1 and 2 are cross-sectional views of the first and second embodiments of the present invention, and FIGS. 3 and 4 are cross-sectional views of the conventional semiconductor device and the depth near the buried collector layer in the embodiment of the present invention. FIG. 5, which is a diagram showing the impurity concentration distribution and the spread of the depletion layer in the horizontal direction, is a cross-sectional view of a conventional semiconductor device. Process 1... Insulating layer, I2... Inter-element insulator, S...
P-type semiconductor substrate, C1...N+ type buried collector layer,
C2...N- type semiconductor layer, C3...N- type buried layer, B...P type base region, E...N+ type emitter region, D,, D2. D,... Metal electrode, X,... Depth of PN junction between collector and substrate, X... Depletion layer width between collector and substrate, Ns... Substrate impurity concentration 1, XA...
・Spreading of the depletion layer into the N-type semiconductor from ``X'', xD...
・Spreading of the depletion layer from XJ into the P-type semiconductor, II...
- Distribution of impurities in the N-type buried layer.

Claims (1)

Translated fromJapanese

【特許請求の範囲】[Claims]　一導電型半導体基板上に形成された逆導電型低濃度不
純物を含む第１の埋込層と、該第１の埋込層上に形成さ
れた逆導電型高濃度不純物を含む第２の埋込層と、該第
２の埋込層上に形成された逆導電型半導体層とを含むこ
とを特徴とする半導体装置。A first buried layer containing a low concentration impurity of an opposite conductivity type formed on a semiconductor substrate of one conductivity type, and a second buried layer containing a high concentration impurity of an opposite conductivity type formed on the first buried layer. A semiconductor device comprising: a buried layer; and an opposite conductivity type semiconductor layer formed on the second buried layer.