【発明の詳細な説明】〔産業上の利用分野〕本発明は半導体基板上での微細パタン形成方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming fine patterns on a semiconductor substrate.
従来の微細パタン形成方法は光露光法により行われてい
る。光露光技術の中でも、単波長光を用いるステッパー
を使う方法が広く実用に供されている。波長としてはｇ
線である４３８ｎｍか、ｉ線の３６５ｎｍが用いられて
いるが、その解像力は０．６〜０．７μｍ程度である。A conventional method for forming fine patterns is a light exposure method. Among optical exposure techniques, a method using a stepper that uses single-wavelength light is widely used in practice. The wavelength is g
Either the 438 nm line or the 365 nm i line is used, and their resolution is about 0.6 to 0.7 μm.
さらに微細なパタンを形成する方法としてエキシマレー
ザ−光を用いる方法や、Ｘ線露光法や電子ビーム露光法
があるが、現在まだ研究段階にある。Methods for forming even finer patterns include a method using excimer laser light, an X-ray exposure method, and an electron beam exposure method, but these methods are still in the research stage.
上述した従来のステッパー技術では０．５μｍからそれ
以下の微細パタンを形成するのは不可能である。しかし
ながらこのような微細なパタンか再現性良く実用レベル
で形成できれば超ＬＳＩデバイスの高密度化のために、
この効果は極めて大きい。With the conventional stepper technology described above, it is impossible to form fine patterns from 0.5 μm to less than 0.5 μm. However, if such fine patterns can be formed at a practical level with good reproducibility, it will be possible to increase the density of VLSI devices.
This effect is extremely large.
本発明の微細パタン形成法は、半導体基板上に所定パタ
ンの酸化シリコン膜を形成する工程と、この酸化シリコ
ン膜に等方性エツチングを施してパタンを微細化する工
程と、前記微細化された酸化シリコン膜、パタンの形成
された基板上にレジストを塗布する工程と、前記レジス
トを酸化シリコン膜の上面が露出するまでエッチバック
する工程と、酸化シリコン膜をエツチング除去すること
により微細な開口を有するレジストパタンを得る工程と
を有している。The fine pattern forming method of the present invention includes a step of forming a silicon oxide film with a predetermined pattern on a semiconductor substrate, a step of isotropically etching the silicon oxide film to make the pattern finer, and a step of forming a fine pattern on the silicon oxide film. A step of applying a resist onto a substrate on which a silicon oxide film and a pattern are formed, a step of etching back the resist until the upper surface of the silicon oxide film is exposed, and a step of etching away the silicon oxide film to form a fine opening. and obtaining a resist pattern having the following characteristics.
次に、本発明について図面を参照して説明する。Next, the present invention will be explained with reference to the drawings.
第１図〜第５図は本発明の一実施例の工程順縦断面図で
ある。第１図はシリコン基板１上に熱酸化によって被着
された酸化シリコン膜２を選択的にエツチングしてパタ
ン形成した状態を示す図である。酸化シリコン膜の選択
エツチングはフォトレジスト３をマスクとしてリアクテ
ィブイオンエツチングによる異方性エツチングでおこな
われ、レジストと同じ幅をもつ酸化シリコン膜２が形成
される。フォトレジスト３のパタニングはｇ線ステッパ
によりおこなわれ、その限界解像度である０、７μｍの
幅でレジストパタン３が残して形成される。つぎに、第
１図のシリコン基板な希弗酸中に浸すことにより酸化シ
リコン膜２の幅を減少せしめる。希弗酸の濃度と液温を
十分にコントロールすることにより減少幅の再現性を実
用的にまで高めるのは容易である。減少幅を０．２μｍ
として酸化膜パタンの幅を０．７μｍから０．５μｍに
まで微細化した状態を示したのが第２図である。第２図
のフォトレジスト３を除去した後に新たにレジスト４を
第３図に示すように酸化シリコン膜２を埋設するように
塗布する。その後、酸素プラズマによりリアクティブイ
オンエツチングを行いレジスト４の膜厚を減小せしめて
いき酸化シリコン膜２の上面が露出された第４図の段階
でエツチングを終了する。しかる後に弗酸に浸すことに
より酸化シリコン膜をエツチング除去してレジストパタ
ン５を得る。このレジストパタン５の開口部分の中層は
０．５μｍである。1 to 5 are vertical sectional views in the order of steps of an embodiment of the present invention. FIG. 1 shows a state in which a silicon oxide film 2 deposited on a silicon substrate 1 by thermal oxidation is selectively etched to form a pattern. Selective etching of the silicon oxide film is performed by anisotropic etching by reactive ion etching using the photoresist 3 as a mask, and a silicon oxide film 2 having the same width as the resist is formed. Patterning of the photoresist 3 is performed using a g-line stepper, and a resist pattern 3 is left with a width of 0.7 μm, which is the limit resolution of the photoresist 3. Next, the width of the silicon oxide film 2 is reduced by immersing the silicon substrate shown in FIG. 1 in dilute hydrofluoric acid. By sufficiently controlling the concentration of dilute hydrofluoric acid and the liquid temperature, it is easy to increase the reproducibility of the reduction width to a practical level. Decrease width by 0.2μm
FIG. 2 shows a state in which the width of the oxide film pattern has been reduced from 0.7 μm to 0.5 μm. After removing the photoresist 3 shown in FIG. 2, a new resist 4 is applied so as to bury the silicon oxide film 2 as shown in FIG. Thereafter, reactive ion etching is performed using oxygen plasma to reduce the film thickness of the resist 4, and the etching is terminated at the stage shown in FIG. 4 when the upper surface of the silicon oxide film 2 is exposed. Thereafter, the silicon oxide film is etched away by immersion in hydrofluoric acid to obtain a resist pattern 5. The middle layer of the opening portion of this resist pattern 5 has a thickness of 0.5 μm.
例えばシリコン基板に微細な溝を形成したい場合、この
ようにして得られたレジストパターンをマスクにリアク
ティブイオンエツチングでシリコン基板を異方性エツチ
ングすることにより幅０．５μｍの溝を形成することが
できる。For example, when it is desired to form a fine groove in a silicon substrate, it is possible to form a groove with a width of 0.5 μm by anisotropically etching the silicon substrate by reactive ion etching using the resist pattern thus obtained as a mask. can.
本実施例ではシリコン基板を酸化することによって形成
された酸化シリコン膜上にフォトレジストを塗布して、
等方性エツチングによる微細化の処理工程をこの酸化シ
リコン膜に加えたが、酸化シリコン膜として気相成長法
で被着したものでも同様の効果が得られることは言うま
でもない。In this example, a photoresist is applied on a silicon oxide film formed by oxidizing a silicon substrate.
Although the silicon oxide film was subjected to a refinement process using isotropic etching, it goes without saying that the same effect can be obtained by depositing a silicon oxide film by vapor phase growth.
以上説明したように本発明ではまず、露光装置の限界解
像度でパタンを形成し、さらに等方性エツチングにより
このパタンを微細化せしめることにより、装置の限界解
像度よりも微細なパタン形成をすることが可能となる。As explained above, in the present invention, a pattern is first formed at the limit resolution of the exposure device, and then this pattern is made finer by isotropic etching, thereby making it possible to form a pattern finer than the limit resolution of the device. It becomes possible.
第１図〜第５図は本発明の一実施例の工程順縦断面図で
ある。■・・・・・・シリコン基板、２・・団・酸化シリコン
膜、３・・・・・・フォトレジスト、４・旧・・レジス
ト、５・・団・レジストパタン。代理人 弁理士 内 原 １日拒ｌ 図弔２図第３図乃５図1 to 5 are vertical sectional views in the order of steps of an embodiment of the present invention. ■... Silicon substrate, 2... group silicon oxide film, 3... photoresist, 4... old resist, 5... group resist pattern. Agent Patent Attorney Uchihara 1 Day Refusal Diagrams 2, 3 and 5
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27222487AJPH01114041A (en) | 1987-10-27 | 1987-10-27 | Forming method for fine pattern |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27222487AJPH01114041A (en) | 1987-10-27 | 1987-10-27 | Forming method for fine pattern |
| Publication Number | Publication Date |
|---|---|
| JPH01114041Atrue JPH01114041A (en) | 1989-05-02 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27222487APendingJPH01114041A (en) | 1987-10-27 | 1987-10-27 | Forming method for fine pattern |
| Country | Link |
|---|---|
| JP (1) | JPH01114041A (en) |
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| US6917076B2 (en) | 1996-05-28 | 2005-07-12 | United Microelectronics Corporation | Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device |
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| JP2008306161A (en)* | 2007-06-05 | 2008-12-18 | Hynix Semiconductor Inc | Method for forming fine pattern of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6917076B2 (en) | 1996-05-28 | 2005-07-12 | United Microelectronics Corporation | Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device |
| KR100603700B1 (en)* | 2002-12-03 | 2006-07-20 | 인터내셔널 비지네스 머신즈 코포레이션 | Method to Enhance Resolution of a Chemically Amplified Photoresist |
| KR100660647B1 (en)* | 2004-09-18 | 2006-12-21 | (주)대진코스탈 | Double Sedan Document Shredder |
| JP2008306161A (en)* | 2007-06-05 | 2008-12-18 | Hynix Semiconductor Inc | Method for forming fine pattern of semiconductor device |
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