【０００１】[0001]
【産業上の利用分野】本発明はアクティブマトリックス
液晶ディスプレイやイメージセンサー、三次元ＬＳＩデ
バイスなど、絶縁性物質上に作成される薄膜半導体装置
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film semiconductor device formed on an insulating material, such as an active matrix liquid crystal display, an image sensor, and a three-dimensional LSI device.
【０００２】[0002]
【従来の技術】近年液晶ディスプレイの大画面化、高解
像度化に伴いその駆動方式は単純マトリックス方式から
アクティブマトリックス方式へと移行し、大容量の情報
を表示出来る様になりつつ有る。アクティブマトリック
ス方式は数十万を超える画素を有する液晶ディスプレイ
が可能で有り、各画素毎にスイッチング・トランジスタ
を形成する物で有る。2. Description of the Related Art In recent years, as the screen size and resolution of liquid crystal displays have increased, the driving system has shifted from a simple matrix system to an active matrix system, and it has become possible to display a large amount of information. The active matrix method can provide a liquid crystal display having more than hundreds of thousands of pixels, and forms a switching transistor for each pixel.
【０００３】これらのスイッチング素子は通常絶縁性物
質上に作成される薄膜トランジスタ（以下ＴＦＴと略
記）が用いられる。ＴＦＴの能動層としては、アモルフ
ァス・シリコンや多結晶シリコンが用いられるが、駆動
回路迄一体化してＴＦＴで作成しようとする場合や画素
の高密度高精細化を進める場合には動作速度の速い多結
晶シリコンが有利である。こうした多結晶シリコンを用
いたＴＦＴを画素のスイッチング素子として用いた時、
画素に対して信号を入力する所謂トランジスタのＯＮ状
態に於いてはアモルファス・シリコンＴＦＴに比べて一
桁以上高いオン電流が得られる。As these switching elements, thin film transistors (hereinafter abbreviated as TFTs) formed on an insulating material are usually used. As the active layer of the TFT, amorphous silicon or polycrystalline silicon is used. However, when the driving circuit is integrated with the TFT or when the pixel density is increased and the definition is advanced, the operation speed is high. Crystalline silicon is advantageous. When a TFT using such polycrystalline silicon is used as a pixel switching element,
In a so-called transistor ON state for inputting a signal to a pixel, an ON current higher by one digit or more than that of an amorphous silicon TFT can be obtained.
【０００４】これに対して入力された信号を保持してい
るトランジスタのＯＦＦ状態では、多結晶シリコンを用
いたＴＦＴはアモルファス・シリコンＴＦＴに比べて多
量の漏洩電流ＩOFFが生じ、画質の低下を引き起こす原
因となっている。On the other hand, when a transistor holding an input signal is in an OFF state, a TFT using polycrystalline silicon generates a larger amount of leakage current IOFF as compared with an amorphous silicon TFT. It hasbecome a cause.
【０００５】従来この漏洩電流ＩOFF を減少させる為に
多結晶シリコンＴＦＴに於いてソース・ドレイン領域に
添加するドナー又はアクセプターとなる不純物の濃度を
変えるライト・ドープ・ドレイン法（ＬＤＤ法）が採用
されている（Ｋ．ＮＡＫＡＺＡＷＡ ｅｔ ａｌ Ｓ１
Ｄ９０ｄｉｇｅｓｔ ３１１’９０）。即ちソース領域
及びドレイン領域内に於いて取り出し電極側の領域で不
純物濃度を高くし、チャンネル側の領域で低くする構造
としたＴＦＴを作成して漏洩電流ＩOFF を減らしてい
る。Conventionally, in order to reduce the leakage current IOFF , a light-doped drain method (LDD method) for changing the concentration of an impurity serving as a donor or an acceptor added to a source / drain region in a polycrystalline silicon TFT has been adopted. (K. NAKAZAWA et al S1
D90 digest 311'90). That is, in the source region and the drain region, a TFT having a structure in which the impurity concentration is increased in the region on the extraction electrode side and reduced in the region on the channel side ismanufactured to reduce the leakage current IOFF .
【０００６】このＬＤＤ構造を有するＴＦＴの従来技術
に依る製造方法を図２を用いて説明する。まず絶縁基板
２０１上に不純物が高濃度に添加されたソース・ドレイ
ン領域２０２を形成する。これは例えば燐添加された多
結晶シリコン膜を減圧気相化学堆積法（ＬＰＣＶＤ法）
などで形成する。（図２ａ）次に真性シリコン膜２０３
を形成し、更にゲート絶縁膜２０４を堆積後ゲート電極
２０５を形成する。（図２ｂ）その後ゲート電極２０５
をマスクとして不純物２０６を１×１０15ｌ／ｃｍ2 程
度以下打ち込みＬＤＤ領域２０８及びチャンネル部２０
７を形成する。（図２ｃ）その後必要に応じて層間絶縁
膜２０９を堆積し、不純物が高濃度に添加されたソース
・ドレイン領域にコンタクト・ホールを開口し、ソース
・ドレイン取り出し電極２１０を形成してＴＦＴが完成
する。A method of manufacturing a TFT having the LDD structure according to the prior art will be described with reference to FIG. First, a source / drain region 202 to which an impurity is added at a high concentration is formed on an insulating substrate 201. For example, a polycrystalline silicon film doped with phosphorus is formed by a low pressure chemical vapor deposition (LPCVD) method.
It forms with. (FIG. 2a) Next, the intrinsic silicon film 203
Is formed, and after a gate insulating film 204 is deposited, a gate electrode 205 is formed. (FIG. 2b) then gate electrode 205
The impurity 206 is implanted into the LDD region 208 and the channel portion 20 at a dose of about 1 × 1015 l / cm2 or less using
7 is formed. (FIG. 2c) Then, if necessary, an interlayer insulating film 209 is deposited, contact holes are opened in the source / drain regions to which impurities are added at a high concentration, and source / drain extraction electrodes 210 are formed to complete the TFT. I do.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら前述した
従来技術に依るＬＤＤ作成には幾つかの問題が有る。ま
ず第一に不純物が高濃度に添加されたソース・ドレイン
領域２０２を最初に形成する為、その存在に依りＴＦＴ
の微細化が困難となる。この結果画素部に於けるＴＦＴ
のしめる面積が大きくなり、開口率が低くなって暗い画
面の液晶ディスプレイとなったり、微細化出来ぬ事から
画素数を増大出来ず、高精細な画面を提供し得ないとの
問題点が出現する。加えて工程が長い為、歩留りの低下
や製品価格を低下出来ないとの問題が有る。更に、アラ
イメントの位置合わせの都合上ＬＤＤ領域２０８の距離
が４〜５μｍと大きくなり、この為ＬＤＤ領域への添加
量が少な過ぎるとＴＦＴに寄生抵抗が生じ、オン電流値
が低下したり、多過ぎるとＬＤＤとならず、オフ漏洩電
流が増大して仕舞うとの問題点が有る。However, there are some problems in the LDD fabrication according to the above-mentioned prior art. First, since the source / drain region 202 to which impurities are added at a high concentration is formed first, the presence of the
It becomes difficult to miniaturize. As a result, the TFT in the pixel section
There is a problem that the area to be covered is large, the aperture ratio is low and the LCD becomes a dark screen, and the number of pixels cannot be increased due to the inability to miniaturize, and a high-definition screen cannot be provided. I do. In addition, since the process is long, there is a problem that the yield cannot be reduced and the product price cannot be reduced. Further, the distance between the LDD regions 208 is increased to 4 to 5 μm for the sake of alignment. For this reason, if the addition amount to the LDD regions is too small, a parasitic resistance occurs in the TFT, and the on-current value is reduced. If it is too long, the LDD does not occur, and there is a problem that the off-leakage current increases and the operation ends.
【０００８】そこで本発明はこの様な諸問題点の解決を
目指し、その目的とする所は工程を簡略化した上でＴＦ
Ｔの微細化を進められ得るＬＤＤ構造のＴＦＴの製造方
法を提供する事に有る。Accordingly, the present invention aims to solve these problems, and the purpose thereof is to simplify the process and to improve the TF.
An object of the present invention is to provide a method of manufacturing a TFT having an LDD structure that can promote the miniaturization of T.
【０００９】[0009]
【課題を解決するための手段】本発明は、少なくとも表
面が絶縁性物質である基板上に、半導体層を形成する工
程と、該半導体層上にゲート絶縁膜を形成した後、該ゲ
ート絶縁膜上にゲート電極を形成する工程と、前記ゲー
ト電極端部を覆うようにレジストマスクを形成して、前
記半導体層上のゲート絶縁膜を必要量だけ除去して、前
記レジストマスクに覆われていた領域は厚いゲート絶縁
膜領域、前記レジストマスクに覆われていなかった領域
は薄いゲート絶縁膜領域とするゲート絶縁膜除去工程
と、前記厚いゲート絶縁膜領域及び薄いゲート絶縁膜領
域を介し、且つ、前記ゲート電極をマスクとして不純物
イオンを前記半導体層に導入することにより、前記厚い
ゲート絶縁膜領域に対応する前記半導体層を低濃度半導
体層とし、前記薄いゲート絶縁膜領域に対応する前記半
導体層を不純物を高濃度半導体層とし、前記低濃度半導
体層と前記高濃度半導体層よりなるソース領域及びドレ
イン領域を形成する工程とを含み、前記ゲート絶縁膜除
去工程のゲート絶縁膜除去必要量はＬＳＳ理論に基づい
て高濃度半導体層への添加量と低濃度半導体層への添加
量、及び打ち込みエネルギー、及び不純物イオン種に応
じて定められることを特徴とする。According to the present invention, there is provided a semiconductor device comprising a step of forming a semiconductor layer on a substrate having at least a surface made of an insulating material; a step of forming a gate insulating film on the semiconductor layer; Forming a gate electrode thereon, forming a resist mask so as to cover an end of the gate electrode, removing a necessary amount of a gate insulating film on the semiconductor layer, and covering the semiconductor layer with the resist mask. A region is a thick gate insulating film region, a region not covered with the resist mask is a thin gate insulating film region, a gate insulating film removing step, and the thick gate insulating film region and the thin gate insulating film region, and By introducing impurity ions into the semiconductor layer using the gate electrode as a mask, the semiconductor layer corresponding to the thick gate insulating film region is made a low-concentration semiconductor layer, Forming a source region and a drain region comprising the low-concentration semiconductor layer and the high-concentration semiconductor layer, wherein the semiconductor layer corresponding to the gate insulating film region is a high-concentration semiconductor layer containing impurities. The required amount of gate insulating film removal in the removal step is determined according to the amount of addition to the high concentration semiconductor layer and the amount of addition to the low concentration semiconductor layer, implantation energy, and impurity ion species based on the LSS theory. I do.
【００１０】[0010]
【実施例】以下本発明に係るＴＦＴの製造方法について
実施例に基づいて詳述するが、本発明が以下の実施例に
限定される物では無い。EXAMPLES Hereinafter, a method for manufacturing a TFT according to the present invention will be described in detail with reference to examples, but the present invention is not limited to the following examples.
【００１１】図１（ａ）〜（ｄ）は本発明に依るＬＤＤ
構造を有するＭＩＳ型電界効果トランジスタを形成する
ＴＦＴの製造工程を断面で示した図で有る。まず表面が
絶縁性物質で有る基板上にシリコン膜１０１を成膜す
る。この膜厚は１５００Å程度以下が好ましいが、特に
限定される必要も無い。本実施例では５００Åの膜厚に
堆積する。次にゲート絶縁膜１０２を堆積する。ここで
はゲート絶縁膜材として二酸化硅素（ＳｉＯ2 ）膜を選
び電子サイクロトロン共鳴プラズマＣＶＤ法（ＥＣＲ−
ＰＥＣＶＤ法）で１２５０Åの膜厚に堆積する。この他
にも常圧ＣＶＤ法（ＡＰＣＶＤ法）やスパッター法など
でもゲート絶縁膜は形成され得る。続いてゲート電極１
０３を形成する。本実施例ではゲート電極材料として３
０００Åの膜厚を有する燐添加多結晶シリコン膜を用い
たが、これ以外にも金属材料なども可能で有る。ゲート
電極材料堆積後パターニングを行い、ゲート電極１０３
を形成する（図１（ａ））。次に不純物を高濃度に添加
したい領域上のゲート絶縁膜を必要量丈エッチングし、
その領域上のゲート絶縁膜を薄くする（１０４）。本実
施例ではこの薄いゲート絶縁膜１０４の膜厚をゼロとし
た。即ち、不純物を高濃度に添加したい領域の上からゲ
ート絶縁膜を完全に取り除きシリコン面を露出させた。
しかしながらゲート絶縁膜１０２の膜厚と不純物イオン
種及び、打ち込みエネルギーと、添加濃度に応じて、薄
いゲート絶縁膜１０４の膜厚を任意に変え得る。次に添
加したいイオン種１０５を該基板に打ち込む（図１
（ｂ））。本実施例では不純物イオンとして燐を選び+
Ｐ31を６０ＫｅＶで１×１０16ｌ／ｃｍ2 打ち込む。こ
の場合ＬＳＳ理論（Ｊ．Ｌｉｎｄｈａｒｄ ｅｔ ａ
ｌ．Ｍａｔ．Ｆｙｓ．Ｍｅｄｄ．Ｄａｎ．Ｖｉｄ．Ｓｅ
ｌｓｋ３３，Ｎｏ１４，１，１９６３）FIGS. 1A to 1D show an LDD according to the present invention.
FIG. 4 is a cross-sectional view showing a manufacturing process of a TFT for forming a MIS field-effect transistor having a structure. First, a silicon film 101 is formed on a substrate whose surface is made of an insulating material. This film thickness is preferably about 1500 ° or less, but need not be particularly limited. In this embodiment, the film is deposited to a thickness of 500 °. Next, a gate insulating film 102 is deposited. Here, a silicon dioxide (SiO2 ) film is selected as a gate insulating film material, and electron cyclotron resonance plasma CVD (ECR-
The film is deposited to a thickness of 1250 ° by PECVD. In addition, the gate insulating film can be formed by a normal pressure CVD method (APCVD method), a sputtering method, or the like. Then, the gate electrode 1
03 is formed. In this embodiment, 3 is used as the gate electrode material.
Although a phosphorus-added polycrystalline silicon film having a thickness of 2,000 mm was used, other metal materials and the like can be used. After depositing the gate electrode material, patterning is performed to form the gate electrode 103.
Is formed (FIG. 1A). Next, the gate insulating film on the region where the impurity is to be added at a high concentration is etched to a required length,
The gate insulating film on that region is thinned (104). In this embodiment, the thickness of the thin gate insulating film 104 is set to zero. That is, the gate insulating film was completely removed from the region where the impurity was to be added at a high concentration to expose the silicon surface.
However, the thickness of the thin gate insulating film 104 can be arbitrarily changed according to the thickness of the gate insulating film 102, the impurity ion species, the implantation energy, and the added concentration. Next, ion species 105 to be added are implanted into the substrate (FIG. 1).
(B)). In the present embodiment selects phosphorus as an impurity ions+
The P31 at 60KeV implanted1 × 10 16 l / cm 2 . In this case, the LSS theory (J. Lindhard et a
l. Mat. Fys. Medd. Dan. Vid. Se
lsk33 , No14, 1, 1963)
【化１】に依って実効的な添加量を計算すると、シリコン中の投
影飛程ＲP ＝０．０７３μｍ、投影飛程分散△ＲP ＝
０．０２９８μｍでＳｉＯ2 中の投影飛程ＲP ＝０．０
５８６μｍ、投影飛程分散△ＲP ＝０．０２１６μｍで
有る為、不純物を高濃度に添加した領域１０７では７．
８×１０15ｌ／ｃｍ2 相当の打ち込み量となり、ＬＤＤ
領域１０６では１．１×１０13ｌ／ｃｍ2 相当の打ち込
みとなる（図１（ｃ））。イオン打ち込み後、基板に５
００℃２時間程度の熱処理を加え、添加イオンを活性化
する。この活性化は本実施例の如く熱に依り行っても良
いし、又レーザー光照射やラピッド・サーマル・アニー
リング法などで行っても良い。又、不純物元素を水素化
物を原料として、質量分析装置の付いていないイオン打
ち込み装置で添加する場合、活性化熱処理は３５０℃２
時間程度で有っても構わない。例えば燐添加を試みる場
合、ホスフィン（ＰＨ3 ）と水素の混合ガスを原料ガス
として、質量分析装置の付いていないイオン打ち込み装
置にてＰＨX+（Ｘ＝０、１、２、３）やＨ+ 、Ｈ2+を同
時に打ち込む事で、活性化熱処理温度を３５０℃程度以
下へと低く押え、その熱処理時間も２時間程度以下と短
縮可能となる。不純物イオン活性化後、層間絶縁膜１０
８を必要に応じて堆積し、コンタクト・ホールを開口し
てアルミニウムなどで配線１０９をし、ＬＤＤ構造を有
するＴＦＴが完成する（図１（ｄ））。尚、コンタクト
・ホール開口前に質量分析装置の付いていないイオン打
ち込み装置に依り水素（Ｈ+ 、Ｈ2+）を適当量打ち込ん
で、トランジスタ特性を改善しても良い。本実施例では
８０ＫｅＶのエネルギーで水素を５×１０15ｌ／ｃｍ2
打ち込んだ。Embedded image When the effective addition amount is calculated according to the following equation, the projection range in silicon is RP = 0.073 μm, and the projection range dispersion △ RP =
At 0.0298 μm, the projection range RP in SiO2 = 0.0
Since it is 586 μm and the projection range dispersion ΔRP = 0.0216 μm, in the region 107 to which the impurity is added at a high concentration, 7.
The ejection amount is equivalent to 8 × 1015 l / cm2 , and the LDD
In the region 106, the implantation is equivalent to 1.1 × 1013 l / cm2 (FIG. 1C). After ion implantation, 5
A heat treatment at about 00 ° C. for about 2 hours is applied to activate the added ions. This activation may be performed by heat as in this embodiment, or may be performed by laser light irradiation, rapid thermal annealing, or the like. In addition, when an impurity element is added using a hydride as a raw material by an ion implantation apparatus without a mass spectrometer, the activation heat treatment is performed at 350 ° C.
It may be about an hour. For example, when attempting to add phosphorus, a mixed gas of phosphine (PH3 ) and hydrogen is used as a source gas, and PHx+ (X = 0, 1, 2, 3) or H 2 is used in an ion implantation apparatus without a mass spectrometer. By simultaneously implanting+ and H2+ , the activation heat treatment temperature can be kept low to about 350 ° C. or less, and the heat treatment time can be reduced to about 2 hours or less. After the activation of the impurity ions, the interlayer insulating film 10
8 is deposited as necessary, a contact hole is opened, and a wiring 109 is made of aluminum or the like, thereby completing a TFT having an LDD structure (FIG. 1D). The transistor characteristics may be improved by implanting an appropriate amount of hydrogen (H+ , H2+ ) using an ion implanter without a mass spectrometer before opening the contact hole. In this embodiment, hydrogen is supplied at 5 × 1015 l / cm2 at an energy of 80 KeV.
I typed it in.
【００１２】以上説明した工程に依り製作したＴＦＴ特
性の一例Ｉds−Ｖgs曲線を図３３−ａに示した。本実施
例ではトランジスタ・サイズはＬ＝Ｗ＝１０μｍで、不
純物を高濃度に添加した領域１０７の長さが１０μｍ、
ＬＤＤ領域１０６の長さが２μｍで有った。図３３−ｂ
には比較の為従来技術に依って製作したセルフ・アライ
ンＴＦＴの電気的特性図を示した。図３より本発明のＬ
ＤＤ構造ＴＦＴはオン電流の低下は殆ど見られず、且つ
漏洩電流ＩOFF を大幅に低減させている様子が窺い知ら
れる。[0012] One example Ids -Vgs curve of the fabricated TFT characteristics depending on the process described above are shown in FIG. 33-a. In this embodiment, the transistor size is L = W = 10 μm, the length of the region 107 doped with high concentration of impurities is 10 μm,
The length of the LDD region 106 was 2 μm. FIG. 33-b
FIG. 2 shows an electrical characteristic diagram of a self-aligned TFT manufactured according to the prior art for comparison. FIG.
It can be seen that in the TFT having the DD structure, the on-current is hardly reduced and the leakage current IOFF is greatly reduced.
【００１３】本実施例では薄いゲート絶縁膜１０４の膜
厚をゼロとしたが、この膜厚はゲート絶縁膜の膜質、膜
厚、打ち込みイオン種とその量、打ち込みエネルギー、
及び不純物を高濃度に添加する領域１０７とＬＤＤ領域
１０６との濃度比に応じて変えられ、必ずしもゼロにす
る必要は無い。通常、ゲート絶縁膜１０２と層間絶縁膜
１０８の膜質が異なる為、ソース・ドレイン領域に配線
１０９を行う場合、最初に層間絶縁膜１０８にコンタク
ト・ホールを開口し、次にゲート絶縁膜１０２にコンタ
クト・ホールを開口した上で配線を行う等の二回の開口
作業が有り、本実施例ではそれらの内一回を薄いゲート
絶縁膜１０４の作成と兼行させた。こうした手法を取る
事に依り、余分な工程を加える事なく、安定なＬＤＤ構
造ＴＦＴを簡便な工程で作成し得る。In this embodiment, the thickness of the thin gate insulating film 104 is set to zero. However, this thickness is determined by the film quality of the gate insulating film, the film thickness, the type and amount of implanted ions, the implantation energy,
In addition, the concentration can be changed according to the concentration ratio between the region 107 to which the impurity is added at a high concentration and the LDD region 106, and it is not necessarily required to be zero. Normally, since the film quality ofthe gate insulating film 102 and that of the interlayer insulating film 108 are different, when the wiring 109 is formed in the source / drain regions, first, a contact hole is opened in the interlayer insulating film 108, and then the gate insulating film 102 is contacted. There are two opening operations such as wiring after opening a hole. In this embodiment, one of these operations is also used for forming the thin gate insulating film 104. By adopting such a method, a stable LDD structure TFT can be formed by a simple process without adding an extra process.
【００１４】[0014]
【発明の効果】以上述べてきたように、本発明によれ
ば、ＬＤＤ構造を有するＴＦＴを製造するにあたり、高
濃度半導体層上のゲート絶縁膜をＬＳＳ理論に基づいて
必要量だけ除去して薄くし、その後不純物イオンを打ち
込むことで、ゲート絶縁膜の膜厚に影響されることな
く、ソース領域及びドレイン領域の不純物高濃度領域及
び低濃度領域の濃度を自在に設定することが可能とな
り、これによって作成しようとするＴＦＴの特性に応じ
常に最適の高濃度領域及び低濃度領域の不純物濃度及び
濃度比を有する半導体層を簡単な工程で形成することが
可能となり、しかもＴＦＴの微細化も可能となった。し
たがって、本発明においては、液晶ディスプレイの開口
率を高めたり、高精細画素を提供出来る等、アクティブ
・マトリックス液晶ディスプレイの高性能化や低価格化
を実現することができると云う効果も有する。Asdescribed above, according to the present invention,
For example, in manufacturing a TFT having an LDD structure,
Based on LSS theory
Remove only the required amount to make it thinner, and then strike with impurity ions.
Is not affected by the thickness of the gate insulating film.
High impurity concentration regions in the source and drain regions
And low-density areas can be set freely.
Depending on the characteristics of the TFT to be created.
Always optimal impurity concentration of high concentration region and low concentration region and
A semiconductor layer having a concentration ratio can be formed by a simple process.
It has become possible, and furthermore, the miniaturization of the TFT has become possible. I
Accordingly, the present inventionalso has theeffect of realizing higher performance and lower cost of the active matrix liquid crystal display, such as increasing the aperture ratio of the liquid crystal display and providing high definition pixels.
【図１】（ａ）〜（ｄ）は本発明の一実施例を示す薄膜
半導体装置製造の各工程に於ける素子断面図。FIGS. 1A to 1D are cross-sectional views of an element in each step of manufacturing a thin-film semiconductor device according to an embodiment of the present invention.
【図２】（ａ）〜（ｄ）は従来技術に依る薄膜半導体装
置製造の各工程に於ける素子断面図。FIGS. 2A to 2D are cross-sectional views of elements in each step of manufacturing a thin-film semiconductor device according to a conventional technique.
【図３】本発明の効果を示す図。FIG. 3 is a diagram showing the effect of the present invention.
１０１ シリコン膜 １０２ ゲート絶縁膜 １０３ ゲート電極 １０４ 薄いゲート絶縁膜 １０５ 不純物イオン種打ち込み １０６ ＬＤＤ領域 １０７ 不純物を高濃度に添加した領域 １０８ 層間絶縁膜 １０９ 配線 ２０１ 絶縁基板 ２０２ 不純物が高濃度に添加されたソース・ドレイン
領域 ２０３ 真正シリコン膜 ２０４ ゲート絶縁膜 ２０５ ゲート電極 ２０６ 不純物イオン種打ち込み ２０７ チャンネル部 ２０８ ＬＤＤ領域 ２０９ 層間絶縁膜 ２１０ ソース・ドレイン取り出し電極DESCRIPTION OF SYMBOLS 101 Silicon film 102 Gate insulating film 103 Gate electrode 104 Thin gate insulating film 105 Impurity ion implantation 106 LDD region 107 Highly doped region 108 Interlayer insulating film 109 Wiring 201 Insulating substrate 202 Highly doped impurity Source / drain region 203 Authentic silicon film 204 Gate insulating film 205 Gate electrode 206 Impurity ion species implantation 207 Channel portion 208 LDD region 209 Interlayer insulating film 210 Source / drain extraction electrode
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 29/786 H01L 21/336──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl.7 , DB name) H01L 29/78 H01L 29/786 H01L 21/336
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21707091AJP3345756B2 (en) | 1991-08-28 | 1991-08-28 | Method for manufacturing semiconductor device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21707091AJP3345756B2 (en) | 1991-08-28 | 1991-08-28 | Method for manufacturing semiconductor device |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001117186ADivisionJP3417402B2 (en) | 2001-04-16 | 2001-04-16 | Method for manufacturing thin film semiconductor device |
| Publication Number | Publication Date |
|---|---|
| JPH0555255A JPH0555255A (en) | 1993-03-05 |
| JP3345756B2true JP3345756B2 (en) | 2002-11-18 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21707091AExpired - LifetimeJP3345756B2 (en) | 1991-08-28 | 1991-08-28 | Method for manufacturing semiconductor device |
| Country | Link |
|---|---|
| JP (1) | JP3345756B2 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW297142B (en)* | 1993-09-20 | 1997-02-01 | Handotai Energy Kenkyusho Kk | |
| JP5323604B2 (en)* | 2009-07-30 | 2013-10-23 | 株式会社ジャパンディスプレイ | Display device and manufacturing method thereof |
| CN103472646B (en)* | 2013-08-30 | 2016-08-31 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof and display device |
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| JPH0555255A (en) | 1993-03-05 |
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