【０００１】[0001]
【産業上の利用分野】本発明は、半導体搭載用リード付
き基板の製造法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a substrate with leads for mounting a semiconductor.
【０００２】[0002]
【従来の技術】実装される半導体の面積比率を飛躍的に
向上させるものとして、マザー・ボードと別の小型基板
（ドーター・ボード）に複数の裸のＬＳＩチップを直接
実装したマルチチップ・モデュールが提案されている
（NIKKEI MICRODEVICES 1989年12月号、32〜60頁）。2. Description of the Related Art A multi-chip module in which a plurality of bare LSI chips are directly mounted on a mother board and another small board (daughter board) has been proposed as a means for dramatically improving the area ratio of semiconductors to be mounted. Proposed (NIKKEI MICRODEVICES December 1989, pp. 32-60).
【０００３】このマルチチップ・モデュールで、半導体
が搭載される基板はリード付き基板であり、リード付き
基板の製造に使われるリードフレームは、0.15〜0.25mm
厚の金属シートを打ち抜くもしくはエッチングしてパタ
ーンを形成して製造されている。In this multi-chip module, the substrate on which the semiconductor is mounted is a substrate with leads, and the lead frame used for manufacturing the substrate with leads is 0.15 to 0.25 mm.
It is manufactured by punching or etching a thick metal sheet to form a pattern.
【０００４】また、複数の半導体を搭載するマルチチッ
プ・モジュールでは、半導体が搭載される基板で半導体
間の配線も同時に必要となる。このような要求に対し
て、リードフレーム上に配線板を乗せ、配線板上に半導
体搭載の後、配線板周囲に配置したリードと配線板間を
ワイヤやはんだで接続するタイプや、リードフレームと
絶縁基材、銅箔等を積層プレスした後基板上の配線層と
リードをスルーホールやバイアホールで電気的に接続す
るタイプなどが提案されている（NIKKEI MICRODEVICES
1989年12月号、32〜60頁）。Further, in a multi-chip module on which a plurality of semiconductors are mounted, wiring between the semiconductors is also required on a substrate on which the semiconductors are mounted. In response to such demands, a wiring board is mounted on a lead frame, and after mounting a semiconductor on the wiring board, a type of connecting a lead arranged around the wiring board and the wiring board with a wire or solder is used. There has been proposed a type in which insulating layers, copper foil, etc. are laminated and pressed, and the wiring layer and leads on the board are electrically connected with through holes and via holes (NIKKEI MICRODEVICES
December 1989, 32-60).
【０００５】[0005]
【発明が解決しようとする課題】金属シートを打ち抜く
もしくはエッチングしてリードフレームを製造する方法
ではリードを微細化、高密度化すること自体限界があ
り、また微細化、高密度化するとリードフレームがマル
チチップ・モジュールの製造工程中にふらつき位置精度
の面で問題があり、この点からもリードの微細化、高密
度化には限界があった。In a method of manufacturing a lead frame by punching or etching a metal sheet, there is a limit in terms of miniaturization and densification of the lead. During the manufacturing process of the multi-chip module, there is a problem in terms of wobble position accuracy, and from this point, there is a limit to miniaturization and high-density leads.
【０００６】また、複数の半導体を搭載しているマルチ
チップ・モジュールでは半導体間の配線も同時に行うた
めに、新な接続部を多く作ることとなり、信頼性低下や
検査を含む製造工程数が増加しコスト増加の原因となっ
ている。Further, in a multi-chip module having a plurality of semiconductors mounted thereon, wiring between the semiconductors is also performed at the same time, so that many new connection parts are formed, and the number of manufacturing steps including reliability deterioration and inspection increases. Cost increase.
【０００７】本発明は、リードの微細化、高密度化を可
能とし、かつ半導体間接続部の信頼性に優れ、検査を含
む製造工程数が少なくてすむ半導体搭載用リード付き基
板の製造法を提供するものである。The present invention provides a method for manufacturing a substrate with a lead for mounting on a semiconductor, which enables miniaturization and high-density of the lead, has excellent reliability of a connection portion between semiconductors, and requires a small number of manufacturing steps including inspection. To provide.
【０００８】[0008]
【課題を解決するための手段】本発明は、剛性に優れる
金属薄板の上に少なくともリード部を含むリードフレー
ム形状の良導体金属のパターンを形成する工程、リード
部の少なくともアウターリードとなる部分を除いてリー
ドフレーム形状の良導体金属のパターン面を絶縁性基板
に接着させる工程、剛性に優れる金属薄板をエッチング
して少なくともリード部を含むリードフレーム形状のパ
ターンを形成する工程を含むことを特徴とするものであ
る。According to the present invention, there is provided a step of forming a pattern of a good conductor metal in a lead frame shape including at least a lead portion on a thin metal plate having excellent rigidity, excluding at least a portion of the lead portion which becomes an outer lead. Bonding a pattern surface of a good conductor metal in a lead frame shape to an insulating substrate, and etching a thin metal plate having excellent rigidity to form a lead frame shape pattern including at least a lead portion. It is.
【０００９】図１は本発明の一実施例を示すものであ
る。板厚0.05mmの鉄ニッケル４２合金箔１上に、1μｍ
厚のニッケルをめっき２した後、フィルムレジストを用
いてレジストを形成し、次いで電気銅めっきを行い80μ
ｍピッチの配線部と0.3mmピッチのリード部を有するリ
ードフレーム形状の厚さ30μｍ配線パターン３を形成し
た。このようにして得た少なくともリード部を有するリ
ードフレーム形状の配線パターン３の面にガラス布エポ
キシ樹脂プリプレーグ４、両面配線板５、ガラス布エポ
キシ樹脂プリプレーグ４、銅箔６を重ねて（図１(ａ)）
圧着し多層化した（図１(ｂ)）。ガラス布エポキシ樹脂
プリプレーグ４、両面配線板５、銅箔６はリードフレー
ム形状の配線パターン３のリード部のアウターリードと
なる部分に対応する部分が打ち抜かれている。次に、層
間接続部にスルホール８を明け、スルーホールを含む全
面に銅めっき７した（図１(ｃ)）後、両面をリード、ダ
イパッド、必要な配線及び裏面の必要な配線が残るよう
にパターンエッチングした。続いてエッチングストッパ
の１μｍニッケルをエッチング除去した（図１(ｄ)）。
リードフレームのフレーム部を切断除去してリード付き
基板とした。剛性に優れる金属薄板としては、板厚0.01
〜0.1mmの鉄ニッケル合金、銅合金、銅等が好ましい。
剛性に優れる金属薄板の上に形成される少なくともリー
ド部を含むリードフレーム形状の良導体金属としては銅
が好ましい。リードフレーム形状の良導体金属の厚みは
10〜50μｍが好ましい。FIG. 1 shows an embodiment of the present invention. 1μm on iron-nickel 42 alloy foil 1 with 0.05mm thickness
After plating thick nickel 2, a resist is formed using a film resist, and then copper electroplating is performed.
A 30-μm-thick wiring pattern 3 having a lead frame shape having a wiring portion of m pitches and a lead portion of 0.3 mm pitch was formed. A glass cloth epoxy resin prepreg 4, a double-sided wiring board 5, a glass cloth epoxy resin prepreg 4, and a copper foil 6 are superposed on the surface of the lead frame-shaped wiring pattern 3 having at least the lead portions thus obtained (FIG. 1 ( a))
It was compressed and multilayered (FIG. 1 (b)). In the glass cloth epoxy resin pre-preg 4, the double-sided wiring board 5, and the copper foil 6, a part corresponding to a part to be an outer lead of the lead part of the lead frame-shaped wiring pattern 3 is punched. Next, a through hole 8 is formed in the interlayer connection portion, and copper plating 7 is performed on the entire surface including the through hole (FIG. 1 (c)). Pattern etched. Subsequently, 1 μm nickel of the etching stopper was removed by etching (FIG. 1D).
The frame portion of the lead frame was cut and removed to obtain a substrate with leads. For a thin metal sheet with excellent rigidity, a sheet thickness of 0.01
Iron-nickel alloys, copper alloys, copper, etc., of up to 0.1 mm are preferred.
Copper is preferred as a good conductor metal in a lead frame shape including at least a lead portion formed on a thin metal plate having excellent rigidity. The thickness of a good conductor metal in the lead frame shape
10 to 50 μm is preferred.
【００１０】[0010]
【発明の効果】本発明に於いては、次の効果が達成され
る。 (1) リードの幅、間隔を微細にすることができる。 (2) リードフレームの剛性を大にすることができるので
リードのふらつきがなく、高精細で高い位置精度を有す
るリードフレームが得られる。 (3) リード部と必要な配線部を一体化しているため接続
部は増加しない。 (4) 配線部は高密度配線が可能なように良導体金属の厚
みを薄くすることが可能で、リード部は高強度が得られ
るようすることができる。従って、金属の厚みのみなら
ず、材質も使い分けることができ、配線部、リード部共
に最適化が可能になる。According to the present invention, the following effects are achieved. (1) The width and spacing of the leads can be reduced. (2) Since the rigidity of the lead frame can be increased, there is no fluctuation of the lead, and a lead frame having high definition and high positional accuracy can be obtained. (3) Since the leads and necessary wiring are integrated, the number of connections does not increase. (4) The thickness of the good conductor metal can be reduced in the wiring portion so that high-density wiring can be performed, and the lead portion can have high strength. Therefore, not only the thickness of the metal but also the material can be selectively used, and both the wiring portion and the lead portion can be optimized.
【図１】 本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
１．鉄ニッケル４２合金箔 ２．ニッケルめっき ３．配線パターン ４．ガラス布エポキシ樹脂プリプレーグ ５．両面配線板 ６．銅箔 ７．銅めっき ８．スルホール 1. Iron nickel 42 alloy foil 2. Nickel plating 3. Wiring pattern 4. 4. Glass cloth epoxy resin prepreg 5. Double-sided wiring board Copper foil 7. Copper plating 8. Surhole
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3010196AJP2623980B2 (en) | 1991-01-30 | 1991-01-30 | Manufacturing method of substrate with lead for semiconductor mounting |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3010196AJP2623980B2 (en) | 1991-01-30 | 1991-01-30 | Manufacturing method of substrate with lead for semiconductor mounting |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32151096ADivisionJPH09172122A (en) | 1996-12-02 | 1996-12-02 | Manufacture of board provided with semiconductor mounting lead |
| Publication Number | Publication Date |
|---|---|
| JPH04245466A JPH04245466A (en) | 1992-09-02 |
| JP2623980B2true JP2623980B2 (en) | 1997-06-25 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3010196AExpired - Fee RelatedJP2623980B2 (en) | 1991-01-30 | 1991-01-30 | Manufacturing method of substrate with lead for semiconductor mounting |
| Country | Link |
|---|---|
| JP (1) | JP2623980B2 (en) |
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|---|---|---|---|---|
| US7834436B2 (en) | 2008-03-18 | 2010-11-16 | Mediatek Inc. | Semiconductor chip package |
| US7875965B2 (en) | 2008-03-18 | 2011-01-25 | Mediatek Inc. | Semiconductor chip package |
| US8018037B2 (en) | 2009-04-16 | 2011-09-13 | Mediatek Inc. | Semiconductor chip package |
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|---|---|---|---|---|
| JPS6352460A (en)* | 1986-08-22 | 1988-03-05 | Hitachi Ltd | Manufacture of multichip module |
| Publication number | Publication date |
|---|---|
| JPH04245466A (en) | 1992-09-02 |
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| Date | Code | Title | Description |
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| LAPS | Cancellation because of no payment of annual fees |