【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法に関し、特にLDD接
合構造の形成に関するものである。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to the formation of an LDD junction structure.
LSI開発においては、高集積化に伴い様々な困難な問
題が続出しており、そのために新構造のトランジスタ開
発も積極的に行われている。このような環境下において
提案されたトランジスタの１つとしてポリシリコンから
の不純物の拡散を利用してソース・ドレインを形成する
PSDトランジスタ（Polysilicon Source/Drain Tr.）が
ある。従来技術としては、このPSDTr.の製作工程を第２
図に示す。In the LSI development, various difficult problems continue to occur along with the high integration, and for this reason, the development of a transistor with a new structure is being actively performed. One of the proposed transistors under such environment is to form the source / drain by utilizing the diffusion of impurities from polysilicon.
There is a PSD transistor (Polysilicon Source / Drain Tr.). As the conventional technology, the manufacturing process of this PSD Tr.
Shown in the figure.
まず、半導体基板１上に選択的にフィールド酸化膜２
を形成し、このフィールド酸化膜２上にポリシリコン３
を堆積させる。次に層間絶縁膜５を堆積させ、その一部
であるチャネル領域７をRIE等によりパターニングで形
成する（第２図（ａ））。First, the field oxide film 2 is selectively formed on the semiconductor substrate 1.
Is formed, and polysilicon 3 is formed on the field oxide film 2.
Deposit. Next, the interlayer insulating film 5 is deposited, and a part of the channel region 7 is formed by patterning by RIE or the like (FIG. 2A).
次にチャネル領域７にゲート酸化膜８を熱酸化により
形成し、そのゲート酸化膜８上にポリシリコン６を堆積
させる（第２図（ｂ））。Next, a gate oxide film 8 is formed in the channel region 7 by thermal oxidation, and polysilicon 6 is deposited on the gate oxide film 8 (FIG. 2 (b)).
次にチャネル領域７上で、Ｔ字型になるようにポリシ
リコン６とゲート酸化膜８のパターニングをRIE等でエ
ッチングし、ゲート電極10を形成する（第２図
（ｃ））。Then, on the channel region 7, patterning of the polysilicon 6 and the gate oxide film 8 is performed by RIE or the like so as to form a T shape, and a gate electrode 10 is formed (FIG. 2 (c)).
次にＮチャネルの接合形成のために不純物として低濃
度の燐（P+）を垂直にポリシリコン３中に注入し、熱処
理を加え、低濃度領域11を形成する。更に高濃度のヒ素
（As+）を垂直に注入し、熱処理を行い、高濃度領域12
を形成する。この工程により、第２図（ｄ）に示す接合
が形成され、DDD接合（Double Diffused Drain Junctio
n）と呼ばれる構造が得られる。このような構造にする
ことでドレイン領域における電界を緩和し、このためホ
ットキャリア耐性が向上し、信頼性が向上する。Next, low-concentration phosphorus (P+ ) is vertically injected into the polysilicon 3 as an impurity for forming an N-channel junction, and heat treatment is applied to form a low-concentration region 11. Higher concentration arsenic (As+ ) is vertically injected and heat treatment is performed to
To form. By this process, the junction shown in FIG. 2D is formed, and the DDD junction (Double Diffused Drain Junctio
A structure called n) is obtained. With such a structure, the electric field in the drain region is relaxed, so that the hot carrier resistance is improved and the reliability is improved.
しかしながら、DDD接合より更に信頼性が向上する接
合構造にLDD接合（Lightly Doped Drain Junction）が
ある。このLDD構造にPSDTr.を構成することは、PSDTr.
のゲート電極がＴ字型になりソース／ドレインのポリシ
リコン上を覆っているために困難であるので、この形状
のトランジスタでは高信頼性を達成することができない
という問題点があった。However, there is LDD junction (Lightly Doped Drain Junction) as a junction structure that further improves reliability than DDD junction. Configuring PSDTr. In this LDD structure is
It is difficult because the gate electrode has a T-shape and covers the polysilicon of the source / drain. Therefore, there is a problem that the transistor of this shape cannot achieve high reliability.
この発明は上記のような問題点を解消するためになさ
れたもので、LDD構造にできることにより、高信頼性が
得られる新構造PSDトランジスタの製造方法を得ること
を目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to obtain a method of manufacturing a PSD transistor having a new structure, which is highly reliable because it can have an LDD structure.
この発明に係る新構造PSDトランジスタの製造方法
は、接合の形成において、第一層のポリシリコン，層間
絶縁膜形成後に、層間絶縁膜越しに低濃度不純物を第一
層のポリシリコン中に注入するようにし、高濃度不純物
の第一層の多結晶シリコン膜中への注入はＴ字型ゲート
電極形成後に行い、熱処理によりLDD構造を得られるよ
うにしたものである。In the method of manufacturing the PSD PSD of the new structure according to the present invention, in forming a junction, after forming the first layer polysilicon and the interlayer insulating film, a low concentration impurity is injected into the first layer polysilicon through the interlayer insulating film. Thus, the implantation of the high-concentration impurity into the polycrystalline silicon film of the first layer is performed after the T-shaped gate electrode is formed, and the LDD structure can be obtained by the heat treatment.
本発明におけるPSDトランジスタは、低濃度不純物を
第一層の絶縁膜越しに注入するので、第一層の絶縁膜形
成時の熱により多結晶シリコン膜からの拡散が生じてチ
ャネル領域に進入することがなくなり、その後Ｔ字型ゲ
ート電極形成後に高濃度不純物を注入するため、高信頼
性のPSDトランジスタをLDD接合構造により達成できる。Since the PSD transistor of the present invention injects a low-concentration impurity through the insulating film of the first layer, heat from forming the insulating film of the first layer causes diffusion from the polycrystalline silicon film to enter the channel region. And the high-concentration impurity is implanted after the T-shaped gate electrode is formed, so that a highly reliable PSD transistor can be achieved by the LDD junction structure.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例による半導体装置の製造
方法であるLDD構造を持つPSDトランジスタの製作工程を
示し、以下本製造方法について説明する。FIG. 1 shows a process of manufacturing a PSD transistor having an LDD structure, which is a method of manufacturing a semiconductor device according to an embodiment of the present invention. This manufacturing method will be described below.
まず、半導体基板１上に選択的にフィールド酸化膜２
を形成し、このフィールド酸化膜２上に第１ポリシリコ
ン膜３を堆積させ、層間絶縁膜として酸化膜５を堆積さ
せる。First, the field oxide film 2 is selectively formed on the semiconductor substrate 1.
Then, a first polysilicon film 3 is deposited on the field oxide film 2, and an oxide film 5 is deposited as an interlayer insulating film.
次に低濃度不純物の注入を上記酸化膜５越しに行う。
この時の注入条件はポリシリコン３の膜厚2000Å、酸化
膜５の膜厚2000Åとした場合200keVで、1013/cm2台のリ
ン（P+）の注入であり、ポリシリコン膜３中に分布のピ
ーク４がくるようにする（第１図（ａ））。Then, a low concentration impurity is implanted through the oxide film 5.
The implantation conditions at this time are 200 keV when the film thickness of the polysilicon 3 is 2000 Å and the film thickness of the oxide film 5 is 2000 Å, and 1013 / cm2 of phosphorus (P+ ) is injected into the polysilicon film 3. The peak 4 of the distribution is set to come (FIG. 1 (a)).
次にその一部をRIE等によりパターニングを行い、チ
ャネル領域７を形成する。次にチャネル領域７にゲート
酸化膜８を熱酸化により形成し、そのゲート酸化膜８上
に第２のポリシリコン６を堆積させる（第１図
（ｂ））。Next, a part thereof is patterned by RIE or the like to form the channel region 7. Next, the gate oxide film 8 is formed in the channel region 7 by thermal oxidation, and the second polysilicon 6 is deposited on the gate oxide film 8 (FIG. 1 (b)).
次にチャネル領域７上で、Ｔ字型になるようにポリシ
リコン６と酸化膜５のパターニングをRIE等でエッチン
グし、ゲート電極10を形成する。Next, on the channel region 7, the polysilicon 6 and the oxide film 5 are patterned so as to have a T-shape and etched by RIE or the like to form a gate electrode 10.
次にＴ字型ゲート電極10をマスクとして、高濃度不純
物であるヒ素（As+）を1015/cm2台で注入する（第１図
（ｃ））。Next, using the T-shaped gate electrode 10 as a mask, arsenic (As+ ) which is a high-concentration impurity is implanted at a level of 1015 / cm2 (FIG. 1 (c)).
次に熱処理を行い、第一層のポリシリコン膜３中に存
在したリン（P+）４をチャネル領域７以外の第一層のポ
リシリコン層３直下のシリコン基板１内に、ヒ素（A
s+）９をチャネル領域７から離れたシリコン基板１内に
拡散させる。これにより、チャネル領域７の近傍には低
濃度不純物接合11が形成され、その外側には高濃度不純
物接合12が形成される。Next, heat treatment is performed to remove phosphorus (P+ ) 4 existing in the first-layer polysilicon film 3 into the silicon substrate 1 immediately below the first-layer polysilicon layer 3 other than the channel region 7 by arsenic (A
s+ ) 9 is diffused into the silicon substrate 1 away from the channel region 7. As a result, the low-concentration impurity junction 11 is formed near the channel region 7, and the high-concentration impurity junction 12 is formed outside thereof.
このようにして形成される装置は接合構造がLDD構造
となるために、ホットキャリア耐性が向上し、高信頼性
のPSDトランジスタが形成できる。In the device thus formed, the junction structure is the LDD structure, so that the hot carrier resistance is improved and a highly reliable PSD transistor can be formed.
なお上記実施例においては、低濃度不純物，高濃度不
純物を注入してから、一回の熱処理によりLDD構造を得
るようにしたが、低濃度不純物を注入し、チャネル領域
形成後に熱処理を加え、低濃度不純物をシリコン基板内
に拡散して活性化を行い、高濃度不純物はその後，注
入，熱処理を行いLDD構造を得るようにしてもよい。In the above embodiment, the LDD structure is obtained by performing the heat treatment once after the low concentration impurities and the high concentration impurities are implanted. The LDD structure may be obtained by diffusing a concentration impurity into the silicon substrate for activation and then implanting and heat treating the high concentration impurity.
以上のように、この発明によれば新構造PSDトランジ
スタの作製において、第一層のポリシリコン，層間絶縁
膜形成後に、層間絶縁膜越しに低濃度不純物をポリシリ
コン中に注入するようにし、高濃度不純物の第一層の多
結晶シリコン膜中への注入はＴ字型ゲート電極形成後に
行い、熱処理によりLDD構造を得るようにしたため、チ
ャネル領域に不純物が拡散することがなく、接合構造を
LDD構造とすることが可能になり、高信頼性のPSDトラン
ジスタを作製できる効果がある。As described above, according to the present invention, in the fabrication of a new-structure PSD transistor, after forming the first-layer polysilicon and the interlayer insulating film, a low-concentration impurity is injected into the polysilicon through the interlayer insulating film, The implantation of the concentration impurities into the polycrystalline silicon film of the first layer is performed after the T-shaped gate electrode is formed, and the LDD structure is obtained by the heat treatment, so that the impurities are not diffused into the channel region and the junction structure is formed.
The LDD structure can be obtained, and there is an effect that a highly reliable PSD transistor can be manufactured.
第１図はこの発明の一実施例による半導体装置の製造方
法の工程、及び装置の断面を示す図、第２図は従来の半
導体装置の製造方法の工程、及び装置の断面を示す図で
ある。 図において１は半導体基板、２は分離酸化膜、３は第一
ポリシリコン膜、４は低濃度不純物（P+）層、５は層間
絶縁膜、６は第二ポリシリコン膜、７はチャネル領域、
８はゲート酸化膜、９は高濃度不純物（As+）層、10は
ゲート電極、11は低濃度不純物接合、12は高濃度不純物
接合である。 なお図中同一符号は同一又は相当部分を示す。FIG. 1 is a diagram showing steps of a method for manufacturing a semiconductor device and a cross section of the device according to an embodiment of the present invention, and FIG. 2 is a diagram showing steps of a method for manufacturing a conventional semiconductor device and a cross section of the device. . In the figure, 1 is a semiconductor substrate, 2 is an isolation oxide film, 3 is a first polysilicon film, 4 is a low concentration impurity (P+ ) layer, 5 is an interlayer insulating film, 6 is a second polysilicon film, and 7 is a channel region. ,
Reference numeral 8 is a gate oxide film, 9 is a high-concentration impurity (As+ ) layer, 10 is a gate electrode, 11 is a low-concentration impurity junction, and 12 is a high-concentration impurity junction. The same reference numerals in the drawings indicate the same or corresponding parts.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1138594AJP2544806B2 (en) | 1989-05-30 | 1989-05-30 | Method for manufacturing semiconductor device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1138594AJP2544806B2 (en) | 1989-05-30 | 1989-05-30 | Method for manufacturing semiconductor device |
| Publication Number | Publication Date |
|---|---|
| JPH033246A JPH033246A (en) | 1991-01-09 |
| JP2544806B2true JP2544806B2 (en) | 1996-10-16 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1138594AExpired - Fee RelatedJP2544806B2 (en) | 1989-05-30 | 1989-05-30 | Method for manufacturing semiconductor device |
| Country | Link |
|---|---|
| JP (1) | JP2544806B2 (en) |
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| JP5576506B2 (en) | 2010-12-24 | 2014-08-20 | 本田技研工業株式会社 | Vehicle seat back structure |
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