JP2008244191A - Manufacturing method of component-embedded substrate - Google Patents
Manufacturing method of component-embedded substrateDownload PDFInfo
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- JP2008244191A JP2008244191AJP2007083397AJP2007083397AJP2008244191AJP 2008244191 AJP2008244191 AJP 2008244191AJP 2007083397 AJP2007083397 AJP 2007083397AJP 2007083397 AJP2007083397 AJP 2007083397AJP 2008244191 AJP2008244191 AJP 2008244191A
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- component
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- metal particles
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Abstract
Translated fromJapaneseDescription
Translated fromJapanese本発明は部品内蔵基板の製造方法に関するものであり、電子部品、特に、半導体素子を内蔵した部品内蔵基板における電子部品の実装密度を高めるための構成に特徴のある部品内蔵基板の製造方法に関するものである。 The present invention relates to a method of manufacturing a component-embedded substrate, and more particularly to a method of manufacturing a component-embedded substrate characterized by a configuration for increasing the mounting density of electronic components in a component-embedded substrate incorporating a semiconductor element. It is.
近年の携帯情報機器等の小型化・高性能化に伴って、携帯情報機器等に搭載する半導体装置モジュール等の小型化・高密度実装化が求められており、それに伴って半導体素子等の電子部品自体も小型化され、電子部品に設けるバンプ電極等の間隔が狭くなっている。 With recent downsizing and higher performance of portable information devices, etc., there has been a demand for downsizing and high-density mounting of semiconductor device modules and the like mounted on portable information devices. The components themselves are also miniaturized, and the intervals between bump electrodes and the like provided on the electronic components are narrowed.
このような高密度実装の要請に応えるために、半導体チップや受動部品を多層回路基板の表面に実装していた従来の表面実装に代えて、半導体チップ等を多層回路基板の中に埋め込む部品内蔵基板が開発されている（例えば、特許文献１参照）。 In order to meet the demand for such high-density mounting, instead of the conventional surface mounting in which semiconductor chips and passive components are mounted on the surface of the multilayer circuit board, a built-in component in which the semiconductor chip is embedded in the multilayer circuit board A substrate has been developed (see, for example, Patent Document 1).
この部品内蔵基板においては、表面実装に比べて電子部品を配置する自由度が高くなるとともに、電子部品間の配線の最適化により高周波特性を改善することができる等の利点がある。 This component-embedded substrate has advantages that the degree of freedom for arranging electronic components is higher than that of surface mounting, and that high-frequency characteristics can be improved by optimizing the wiring between the electronic components.
現在は、このような部品内蔵基板は、高密度実装の要請の大きな携帯電話機器に、携帯電話に求められる各種の機能の内の一部の機能を切り出したモジュールとして使用されているが、内蔵する電子部品の種類を増やすことによって、メインボード等への適用も可能になる。 Currently, such component-embedded boards are used as modules that cut out some of the various functions required for mobile phones in mobile phone devices that require high-density mounting. By increasing the types of electronic components to be used, application to a main board or the like becomes possible.
また、この部品内蔵基板においては、多層回路基板上に電子部品を実装する場合には、フリップチップ方式が採用されており、このフリップチップ方式の接合の一つとして、接着剤を硬化させると同時に高荷重を印加してＡｕスタッドバンプを押し潰すことにより多層回路基板の内層回路電極とをコンタクトさせる圧接方式がある（例えば、特許文献２参照）。 In addition, in this component built-in substrate, when mounting electronic components on a multilayer circuit board, a flip chip method is adopted, and as one of the flip chip method joints, the adhesive is cured at the same time. There is a pressure contact method in which an Au stud bump is crushed by applying a high load to contact an inner layer circuit electrode of a multilayer circuit board (see, for example, Patent Document 2).
この接合方式は、接着剤を硬化させるときの収縮力と、Ａｕスタッドバンプと多層回路基板の内層回路電極を押しつぶしたときの反発力を利用して、接触を維持させることにより電気的接続を維持するものである。
近年の半導体素子の高性能化に伴い、Ａｕスタッドバンプが挟ピッチ化されており、これに伴いＡｕスタッドバンプのサイズも小さくなる傾向にある。
このことにより、接合時に高荷重を必要とする圧接方式では、ファインピッチ用の小さなバンプを潰すことにより、半導体素子と多層回路基板の内層回路間のクリアランスが狭くなるため、製造中のパーティクルを挟み込み、チップ回路を破損するという問題が生じている。As the performance of semiconductor devices in recent years has increased, Au stud bumps have become narrower pitches, and accordingly, the size of Au stud bumps tends to decrease.
As a result, in the pressure welding method that requires a high load at the time of bonding, crushing small bumps for fine pitch narrows the clearance between the semiconductor element and the inner circuit of the multilayer circuit board, so that the particles being manufactured are sandwiched. The problem of damaging the chip circuit has arisen.
一方、荷重を低くし、クリアランスを確保すると、Ａｕスタッドバンプと多層回路基板の内層回路電極を押しつぶしたときの反発力が不足し、金属スタッドバンプが浮き上がって多層回路基板の内層回路電極間で断線するという問題が生じる。 On the other hand, if the load is reduced and the clearance is secured, the repulsive force when crushing the Au stud bump and the inner layer circuit electrode of the multilayer circuit board is insufficient, and the metal stud bump rises and the wire breaks between the inner layer circuit electrodes of the multilayer circuit board Problem arises.
このように、圧接方式をファインピッチなＡｕスタッドバンプが形成されている半導体素子に用いると、金属スタッドバンプが浮き上ることによる接続不良や、互いに隣接するＡｕスタッドバンプが潰されて変形することにより接触する短絡等の接合限界が生じるという問題がある。 In this way, when the pressure contact method is used for a semiconductor element on which fine-pitch Au stud bumps are formed, a connection failure due to the metal stud bumps floating, or the adjacent Au stud bumps being crushed and deformed. There is a problem that a joining limit such as a short circuit that comes in contact occurs.
そこで、本出願人は、鋭意研究の結果、Ａｕスタッドバンプの表面に低温での合金接合が可能なＡｇナノ粒子やＳｎナノ粒子を転写して合金接合で半導体チップを多層回路基板上に表面実装することを提案している（必要ならば、特願２００６−０２６３２９参照）。 Therefore, as a result of diligent research, the present applicant has transferred surface-mounted semiconductor chips onto a multilayer circuit board by transferring Ag nanoparticles and Sn nanoparticles capable of alloy bonding at a low temperature onto the surface of Au stud bumps. (See Japanese Patent Application No. 2006-026329 if necessary).
しかし、半導体集積回路装置等の電子部品の小型化による半導体モジュールの高密度実装化は表面実装型の半導体モジュールに限られるものではなく、電子部品を内蔵した部品内蔵基板にも求められている。 However, high-density mounting of semiconductor modules by miniaturization of electronic components such as semiconductor integrated circuit devices is not limited to surface-mount type semiconductor modules, and is also required for component-embedded substrates that incorporate electronic components.
したがって、本発明は、部品内蔵基板に内蔵する電子部品の接続端子と多層回路基板の内層回路の接続電極とを低荷重且つ低温で接続することを目的とする。 Accordingly, an object of the present invention is to connect a connection terminal of an electronic component built in a component-embedded substrate and a connection electrode of an inner layer circuit of a multilayer circuit board at a low load and a low temperature.
図１は本発明の原理的構成図であり、ここで図１を参照して、本発明における課題を解決するための手段を説明する。
図１参照
上記課題を解決するために、本発明は、電子部品１の接続端子２と多層回路基板３の内層回路４の接続電極５とを接続するとともに、電子部品１を覆うように多層配線構造８を設けた部品内蔵基板の製造方法において、接続端子２と接続電極５との間に平均粒径が５０ｎｍ〜２００ｎｍのナノ粒径の金属粒子６を介在させる工程と、金属粒子６を焼結させて接続端子２と接続電極５との電気的接続を得る工程とを有することを特徴とする。FIG. 1 is a block diagram showing the principle of the present invention, and means for solving the problems in the present invention will be described with reference to FIG.
1, in order to solve the above-described problem, the present invention connects the
このように、金属粒子６を用いてフリップチップボンディングすることによって、低荷重且つ低温での接合が可能になるため、半導体素子と多層回路基板３の内層回路４間のクリアランスを損なうことなく確実な電気的接続が可能になり、それによって、部品内蔵基板の高密度実装化と信頼性の向上が可能になる。 As described above, since the flip chip bonding using the
この場合の金属粒子６としては、Ａｇからなる金属粒子６或いは接続端子２及び接続電極５の少なくとも一方と合金化する金属粒子６、例えば、Ｓｎ、Ｂｉ、Ｚｎ、Ｎｉ、Ｉｎの内の少なくとも一種類の金属からなる金属粒子６を使用することが、低温における接合のために必要になる。 In this case, the
また、上述の金属粒子６を用いた場合には、金属粒子６を焼結させる工程における焼結温度を２５０℃以下にしても接合が可能になる。
即ち、ナノサイズの金属粒子６を用いた場合には、その金属の融点以下で金属粒子間がセラミックのように焼結して、バルクに近い状態になるため、低温での結合が可能になる。Further, when the
That is, when nano-sized
例えば、Ａｇナノ粒子を用いた場合には、Ａｇの融点９６０．８℃に対して２００℃での接合が可能になり、荷重を与えなくても良好な電気的接触状態を実現することができる。
なお、ミクロンサイズのＡｇフィラーを用いた場合には、接続端子２の下に補足されたＡｇフィラーに高荷重をかけてＡｇフィラー間の接触面積を大きくしなければ良好な接触状態を確保することができない。For example, when Ag nanoparticles are used, bonding at 200 ° C. is possible with respect to the melting point of Ag of 960.8 ° C., and a good electrical contact state can be realized without applying a load. .
When a micron-sized Ag filler is used, a good contact state should be ensured unless a high load is applied to the Ag filler captured under the
この場合、金属粒子６を接続端子２と接続電極５との間に介在させる方法としては、金属粒子６を合成樹脂中に分散させた材料を接続端子２に転写することが最も典型的な方法であり、多層回路基板３の内層回路４上に特別な処理を施すことなく、ファインピッチの接続端子２に対して均一な量の金属粒子６の供給が可能になる。 In this case, the most typical method for interposing the
また、このように、金属粒子６をエポキシ樹脂等の合成樹脂に分散させることによって、金属が焼結したときの材料強度だけでなく、合成樹脂が硬化したときの強度を加えることにより、接合強度を上げることが可能となる。 In addition, by dispersing the
また、アンダーフィル樹脂を設ける工程としては、接続端子２と接続電極５とを接続した後に、電子部品１と多層回路基板３との間に封止用の合成樹脂を注入する工程でも良く、樹脂封止工程が簡単になる。 The step of providing the underfill resin may be a step of injecting a synthetic resin for sealing between the
或いは、接続端子２と接続電極５とを接続する前に、多層回路基板３上に封止用の合成樹脂を予め形成しておき、接続端子２を金属粒子６を介して接続電極５に圧接させたのち、接続端子２と接続電極５との接続及び合成樹脂の硬化とを同時的に行う工程であっても良い。 Alternatively, before connecting the
この場合、封止樹脂７の硬化工程において発生する電子部品１と多層回路基板３の内層回路４の熱膨張係数の差から生じる接合部に加わる応力を封止樹脂７内に分散させ、接続端子２の破断が生ずることがないので、接合信頼性を向上することができる。 In this case, the stress applied to the joint resulting from the difference in thermal expansion coefficient between the
また、電子部品１を覆う多層回路構造を形成するためには、アンダーフィル樹脂となる合成樹脂を硬化させたのち、プリプレグを用いて電子部品１を覆うように、内層回路４と電気的に接続する多層配線構造８を形成することが望ましい。 Further, in order to form a multilayer circuit structure covering the
上述の部品内蔵基板の製造方法を用いて部品内蔵基板を製造することによって、信頼性の高い高実装密度の部品内蔵基板の実現が可能になる。 By manufacturing the component-embedded substrate using the above-described method for manufacturing a component-embedded substrate, it is possible to realize a component-embedded substrate with high reliability and high mounting density.
本発明によれば、低荷重で接合を行っても、Ａｕスタッドバンプと多層回路基板の内層回路電極は、良好な接合状態を維持でき、また、半導体素子等の電子部品と多層回路基板の内層回路間のクリアランスを確保できるため、部品内蔵基板の高信頼性化及び高密度実装化に寄与するところが大きい。 According to the present invention, even when bonding is performed with a low load, the Au stud bump and the inner layer circuit electrode of the multilayer circuit board can maintain a good bonding state, and an electronic component such as a semiconductor element and the inner layer of the multilayer circuit board can be maintained. Since the clearance between the circuits can be secured, it greatly contributes to the high reliability and high density mounting of the component-embedded substrate.
ここで、図２乃至図４を参照して、本発明の実施の形態における接合原理を説明する。
図２参照
まず、半導体チップ等の電子部品１１に設けたＡｕスタッドバンプ１２の先端に金属ナノ粒子１４を含んだ接点材料１３を設ける。
この場合の接点材料１３はエポキシ樹脂等の合成樹脂１５中に平均粒径が５０ｎｍ〜２００ｎｍの金属ナノ粒子１４を分散させたものであり、典型的には転写法によってＡｕスタッドバンプ１２の先端に付着させる。Here, with reference to FIG. 2 thru | or FIG. 4, the joining principle in embodiment of this invention is demonstrated.
See Figure 2
First, the contact material 13 including the
In this case, the contact material 13 is obtained by dispersing
また、金属ナノ粒子１４としては、Ａｇナノ粒子或いはＳｎナノ粒子が典型的なものであるが、Ａｇ、Ｓｎ以外にＢｉ、Ｚｎ、Ｎｉ、或いはＩｎからなる金属ナノ粒子を用いても良く、さらには、Ａｇ−Ｓｎナノ粒子等のそれらの合金ナノ粒子を用いても良いものである。 The
次いで、先端に接点材料１３を付着させたＡｕスタッドバンプ１２を多層回路基板２１の内層回路に設けたＣｕ層、又は、Ｃｕ層／Ｎｉ／Ａｕ構造（表面がＡｕ）のバンプ電極２２に圧接させたのち、２５０℃以下で金属ナノ粒子１４同士を溶融接合させる。 Next, the
この時、Ｃｕ層／Ｎｉ／Ａｕ構造（表面がＡｕ）のバンプ電極２２に対してＳｎ等のＡｕとの合金化が可能な金属ナノ粒子１４を用いた場合には、Ａｕスタッドバンプ１２及びバンプ電極２２の表面のＡｕ層との間でＡｕＳｎ合金等の合金化により接合が行われることになる。
また、Ｃｕ層／Ｎｉ／Ａｕ構造（表面がＡｕ）のバンプ電極２２の代わりにＣｕ層からなるバンプ電極を用いた場合も同様に、Ｓｎ等の合金化により接合が行われる。At this time, when
Similarly, when a bump electrode made of a Cu layer is used instead of the
図３参照
図３は、Ａｇナノ粒子を用いた場合の接合部の概念的要部断面図であり、Ａｕスタッドバンプ１２とバンプ電極２２を構成するＡｕ層２４との間にＡｇナノ粒子が焼結化したＡｇ焼結層２５が介在して良好な電気的接触状態を実現している。See Figure 3
FIG. 3 is a conceptual cross-sectional view of a joint portion using Ag nanoparticles, in which Ag nanoparticles are sintered between the
図４参照
図４は、Ｓｎナノ粒子を用いた場合の接合部の概念的要部断面図であり、Ａｕスタッドバンプ１２とバンプ電極２２を構成するＡｕ層２４との間にＳｎナノ粒子が合金化したＡｕＳｎ層２７が形成され合金化により強固で良好な電気的接触状態を実現している。
なお、この場合、Ａｕスタッドバンプ１２の周辺部においては合金化せずに焼結化したＳｎ焼結層２６が存在する。See Figure 4
FIG. 4 is a conceptual cross-sectional view of a joint portion when Sn nanoparticles are used. AuSn in which Sn nanoparticles are alloyed between the
In this case, an Sn sintered layer 26 that is sintered without being alloyed is present in the peripheral portion of the
このような、接合を形成したのち、以降は、従来の部品内蔵基板の製造程度と同様にアンダーフィル樹脂を充填したのち、プリプレグを用いた多層配線基板の製造工程を利用して上部の多層配線構造を形成することによって部品内蔵基板が完成する。 After forming such a bond, after that, after filling the underfill resin in the same manner as the manufacturing of the conventional component-embedded substrate, the upper multilayer wiring using the manufacturing process of the multilayer wiring substrate using the prepreg is performed. A component-embedded substrate is completed by forming the structure.
次に、図５及び図６を参照して本発明の実施例１の部品内蔵基板の製造工程を説明する。
図５参照
まず、平均粒径が５０ｎｍ〜２００ｎｍ、例えば、１００ｎｍのＡｇナノ粒子をエポキシ樹脂に分散させた接点材料３２を転写ステージ３１上に形成する。
この場合に、転写ステージ３１にはスキージ（図示を省略）が取り付けられており、スキージと転写ステージ３１のギャップを調整することにより、接点材料３２の厚さを例えば、１０μｍとする。Next, the manufacturing process of the component built-in substrate according to the first embodiment of the present invention will be described with reference to FIGS.
See Figure 5
First, the
In this case, a squeegee (not shown) is attached to the transfer stage 31, and the thickness of the
次いで、接点材料３２が未乾燥・未硬化の状態で半導体素子４０を例えば、５００ｇの荷重で転写ステージ３１上に押しつけ、半導体素子４０に設けたＡｕスタッドバンプ４１の先端部に接点材料３２を転写する。
なお、この場合の半導体素子４０は、例えば、８．５ｍｍ角のサイズであり、また、Ａｕスタッドバンプ４１の高さは例えば、３０μｍであり、このＡｕスタッドバンプ４１を例えば、５０μｍの間隔で６８０個形成している。Next, the
In this case, the
次いで、例えば、フリップチップボンダＦＣＢ−２Ｍ（パナソニックＦＳエンジニアリング製商品型番）を用いて、接点材料３２を転写後の半導体素子４０を厚さが０．３５ｍｍの多層回路基板の内層回路５０に設けたＣｕ／Ｎｉ／Ａｕ構造のパッド５１と位置合わせし、次いで、２５０℃以下、例えば、２００℃の加熱温度で、荷重２ｋｇの条件で１０秒間接合を行う。 Next, for example, by using a flip chip bonder FCB-2M (product model number manufactured by Panasonic FS Engineering), the
この時、上述のように、接点材料３２中のＡｇナノ粒子同士が２００℃の温度においてセラミックのように焼結して接合するとともに、接点材料３２の母材となるエポキシ樹脂が硬化して接合をより強固なものにする。 At this time, as described above, the Ag nanoparticles in the
次いで、シアネート系の合成樹脂５３、例えば、Ｕ８４４３（ナミックス製商品型番）を、例えば、６０℃に加熱したホットプレート上で半導体素子４０と内層回路５０との間にシリンジ５２を用いて注入する。 Next, a cyanate-based synthetic resin 53, for example, U8443 (Namics product model number) is injected between the
図６参照
次いで、恒温槽を用いて、例えば、１５０℃で２時間の加熱処理を行うことによって合成樹脂５３を硬化させて封止樹脂５４とする。See FIG.
Next, using a thermostatic bath, for example, heat treatment is performed at 150 ° C. for 2 hours to cure the synthetic resin 53 to obtain the sealing resin 54.
以降は、半導体素子４０の実装部に対応する開口部を形成したプリプレグ５５を介して、後で接続ビア５６となる突起状の銀ペーストバンプを形成した内層回路５０に、接続ビア、及び、配線パターンを形成した積層体を積層し、多層配線構造５７を形成することによって、本発明の実施例１の部品内蔵基板が完成する。 Thereafter, via vias and
この実施例１の部品内蔵基板に対して、接合信頼性の試験として、接合信頼性試験項目である吸湿−リフロー性評価を模擬的に行う模擬吸湿リフロー試験を行った。
この模擬吸湿−リフローの評価方法は、実装後のサンプルを温度８５℃、湿度８５％、で１２時間吸湿させた後、リフロー工程の最大温度である２５０℃にしたホットプレート上で２分間放置して、疑似吸湿−リフロー後の電気的導通の変化を測定した。A simulated moisture absorption reflow test was performed on the component-embedded substrate of Example 1 as a bonding reliability test in which a moisture absorption-reflow property evaluation, which is a bonding reliability test item, was simulated.
In this simulated moisture absorption-reflow evaluation method, the mounted sample is absorbed at a temperature of 85 ° C. and a humidity of 85% for 12 hours, and then left on a hot plate at 250 ° C. which is the maximum temperature of the reflow process for 2 minutes. The change in electrical continuity after pseudo moisture absorption and reflow was measured.
このときの合否判定は、導通抵抗の上昇率が５％以下の場合を合格としたが、実施例１の部品内蔵基板の場合には、サンプル数を５０とした場合に、導通抵抗の上昇率が５％以下であり、良好な接合信頼性が得られた。 In the pass / fail judgment at this time, the case where the increase rate of the conduction resistance was 5% or less was accepted, but in the case of the component-embedded substrate of Example 1, the increase rate of the conduction resistance when the number of samples was 50. Was 5% or less, and good bonding reliability was obtained.
また、この実施例１の部品内蔵基板に対して、超音波映像装置ＦＳ２００（日立建機ファインテック製商品型番）を用いて接合部の観察を行ったところ、各サンプルに接合部に剥離が観察されず、また、このときの半導体素子４０と多層回路基板の内層回路５０のクリアランスは約１４μｍであり、接合信頼性および半導体素子４０と多層回路基板の内層回路５０のクリアランスの確保が両立できた。 Moreover, when the joint part was observed with respect to the component built-in substrate of Example 1 using an ultrasonic imaging device FS200 (product model number manufactured by Hitachi Construction Machinery Finetech Co., Ltd.), peeling was observed at each joint part in each sample. In addition, the clearance between the
次に、図７及び図８を参照して本発明の実施例２の部品内蔵基板の製造工程を説明する。
図７参照
まず、実施例１と同様に、平均粒径が５０ｎｍ〜２００ｎｍ、例えば、１００ｎｍのＳｎナノ粒子をエポキシ樹脂に分散させた接点材料３２を転写ステージ３１上に形成する。
この場合に、転写ステージ３１にはスキージ（図示を省略）が取り付けられており、スキージと転写ステージ３１のギャップを調整することにより、接点材料３２の厚さを例えば、１０μｍとする。Next, the manufacturing process of the component built-in substrate according to the second embodiment of the present invention will be described with reference to FIGS.
See FIG.
First, similarly to Example 1, a
In this case, a squeegee (not shown) is attached to the transfer stage 31, and the thickness of the
次いで、接点材料３２が未乾燥・未硬化の状態で半導体素子４０を例えば、５００ｇの荷重で転写ステージ３１上に押しつけ、半導体素子４０に設けたＡｕスタッドバンプ４１の先端部に接点材料３２を転写する。
なお、この場合の半導体素子４０は、例えば、８．５ｍｍ角のサイズであり、また、Ａｕスタッドバンプ４１の高さは例えば、３０μｍであり、このＡｕスタッドバンプ４１を例えば、５０μｍの間隔で６８０個形成している。Next, the
In this case, the
次いで、例えば、１２０℃で予備加熱処理することによって、転写した接点材料中の溶剤成分を除去するとともに、Ｓｎナノ粒子の仮焼成を行う。 Next, for example, by preheating at 120 ° C., the solvent component in the transferred contact material is removed, and Sn nanoparticles are pre-fired.
次いで、例えば、塗布機ＦＡＤ３２０ｓ（武蔵エンジニアリング製商品型番）を用いて、例えば、厚さが０．２ｍｍの多層回路基板の内層回路６０上に封止樹脂となる合成樹脂６２、例えば、ＵＦＲ１０７（ナガセケムテックス製商品型番）を例えば、１００μｍの厚さに塗布し、フリップチップボンダ、例えば、ＦＣＢ−２Ｍ（パナソニックＦＳエンジニアリング製商品型番）を用いて、転写後の半導体素子４０のＡｕスタッドバンプ４１を内層回路６０に設けたＣｕ／Ｎｉ／Ａｕ構造のパッド６１と位置合わせする。 Next, for example, using a coating machine FAD320s (product model number manufactured by Musashi Engineering), for example, a synthetic resin 62 that becomes a sealing resin on the
図８参照
次いで、加熱温度２００℃、荷重２ｋｇの条件で１０秒間接合を行う。
この時、接点材料３２は１２０℃における予備加熱により溶剤成分が除去されており、また、Ｓｎナノ粒子も仮焼成されているので、荷重２ｋｇで押圧した際に、塗布されている合成樹脂６２をパッド６１上から押し出す際に、接点材料３２が押し出されることがなく、接点材料３２中のＳｎナノ粒子同士の接合を介してパッド６１とＡｕスタッドバンプ４１が接合されるとともに、接点材料３２の母材となるエポキシ樹脂が硬化して接合をより強固なものにする。See FIG.
Next, bonding is performed for 10 seconds under the conditions of a heating temperature of 200 ° C. and a load of 2 kg.
At this time, since the solvent component is removed from the
次いで、恒温槽を用いて、例えば、１５０℃で２時間の加熱処理を行うことによって合成樹脂６２を硬化させて封止樹脂６３とする。 Next, using a thermostat, for example, heat treatment is performed at 150 ° C. for 2 hours to cure the synthetic resin 62 to obtain the sealing resin 63.
以降は、半導体素子４０の実装部に対応する開口部を形成したプリプレグ６４を介して、後で接続ビア６５となる突起状の銀ペーストバンプを形成した内層回路６０に、接続ビア、及び、配線パターンを形成した積層体を積層し、多層配線構造６６を形成することによって、本発明の実施例２の部品内蔵基板が完成する。 Thereafter, the connection vias and the wirings are connected to the
この実施例２においては、封止樹脂６３の硬化工程において発生する半導体素子４０と多層回路基板の内層回路６０の熱膨張係数の差から生じる接合部に加わる応力を封止樹脂６３内に分散させることができ、それによって、Ａｕスタッドバンプ４１の破断が生ずることがないので、接合信頼性をさらに向上することができる。 In the second embodiment, the stress applied to the joint caused by the difference in thermal expansion coefficient between the
この実施例２の部品内蔵基板に対して、上述の模擬吸湿リフロー試験を行ったところ、サンプル数を５０とした場合に、実施例２の部品内蔵基板における導通抵抗の上昇率は５％以下であり、良好な接合信頼性が得られていることが確認された。 When the simulated moisture absorption reflow test was performed on the component-embedded substrate of Example 2, the increase rate of the conduction resistance in the component-embedded substrate of Example 2 was 5% or less when the number of samples was 50. It was confirmed that good bonding reliability was obtained.
また、この実施例２の部品内蔵基板に対して、上述の超音波映像装置による接合部の観察を行ったところ、各サンプルの接合部に剥離が観察されず、また、このときの半導体素子４０と多層回路基板の内層回路６０のクリアランスは約１４μｍであり、接合信頼性および半導体素子４０と多層回路基板の内層回路６０のクリアランスの確保が両立できた。 Further, when the joint portion of the component built-in substrate of Example 2 was observed by the above-described ultrasonic imaging apparatus, no peeling was observed at the joint portion of each sample, and the
次に、図９乃至図１２を参照して本発明の実施例３の部品内蔵基板の製造工程を説明する。
図９参照
まず、実施例１と同様に、平均粒径が５０ｎｍ〜２００ｎｍ、例えば、１５０ｎｍのＡｇナノ粒子をエポキシ樹脂に分散させた接点材料３２を転写ステージ３１上に形成する。
この場合に、転写ステージ３１にはスキージ（図示を省略）が取り付けられており、スキージと転写ステージ３１のギャップを調整することにより、接点材料３２の厚さを例えば、１０μｍとする。Next, a manufacturing process of the component built-in substrate according to the third embodiment of the present invention will be described with reference to FIGS.
Refer to FIG. 9 First, as in Example 1, a
In this case, a squeegee (not shown) is attached to the transfer stage 31, and the thickness of the
次いで、接点材料３２が未乾燥・未硬化の状態で半導体素子４０を例えば、５００ｇの荷重で転写ステージ３１上に押しつけ、半導体素子４０に設けたＡｕスタッドバンプ４１の先端部に接点材料３２を転写する。
なお、この場合の半導体素子４０は、例えば、８．５ｍｍ角のサイズであり、また、Ａｕスタッドバンプ４１の高さは例えば、３０μｍであり、このＡｕスタッドバンプ４１を例えば、５０μｍの間隔で６８０個形成している。Next, the
In this case, the
次いで、例えば、１２０℃で予備加熱処理することによって、転写した接点材料中の溶剤成分を除去するとともに、Ａｇナノ粒子の仮焼成を行う。 Next, for example, by preheating at 120 ° C., the solvent component in the transferred contact material is removed, and the Ag nanoparticles are temporarily fired.
次いで、例えば、塗布機ＦＡＤ３２０ｓ（武蔵エンジニアリング製商品型番）を用いて、例えば、厚さが０．２ｍｍの多層回路基板を構成するコア基板７０上に封止樹脂となる合成樹脂７２、例えば、ＵＦＲ１０７（ナガセケムテックス製商品型番）を例えば、１００μｍの厚さに塗布し、フリップチップボンダ、例えば、ＦＣＢ−２Ｍ（パナソニックＦＳエンジニアリング製商品型番）を用いて、転写後の半導体素子４０のＡｕスタッドバンプ４１をコア基板７０に設けたＣｕからなるパッド７１と位置合わせする。 Next, for example, using a coating machine FAD320s (product model number manufactured by Musashi Engineering Co., Ltd.), for example, a synthetic resin 72 serving as a sealing resin on the
図１０参照
次いで、加熱温度２００℃、荷重２ｋｇの条件で１０秒間接合を行う。
この時、接点材料３２は１２０℃における予備加熱により溶剤成分が除去されており、また、Ａｇナノ粒子も仮焼成されているので、荷重２ｋｇで押圧した際に、塗布されている合成樹脂７２をパッド７１上から押し出す際に、接点材料３２が押し出されることがなく、接点材料３２中のＡｇナノ粒子同士の接合を介してパッド７１とＡｕスタッドバンプ４１が接合されるとともに、接点材料３２の母材となるエポキシ樹脂が硬化して接合をより強固なものにする。See FIG.
Next, bonding is performed for 10 seconds under the conditions of a heating temperature of 200 ° C. and a load of 2 kg.
At this time, since the solvent component is removed from the
次いで、恒温槽を用いて、例えば、１５０℃で２時間の加熱処理を行うことによって合成樹脂７２を硬化させて封止樹脂７３とする。 Next, using a thermostatic bath, for example, heat treatment is performed at 150 ° C. for 2 hours to cure the synthetic resin 72 to obtain a sealing
次いで、半導体素子４０の実装部に対応する開口部を形成したプリプレグ７４を介して、両側から銅箔７７，７８に樹脂７９，８０を付着させた樹脂付き銅箔７５，７６を積層する。 Subsequently, resin-coated copper foils 75 and 76 in which resins 79 and 80 are attached to the copper foils 77 and 78 are laminated from both sides through a
図１１参照
次いで、樹脂７９，８０を硬化させる。
次いで、次に、ドリルを用いてスルーホール８１，８２を形成したのち、無電解Ｃｕメッキ及び電解Ｃｕメッキを用いて、スルーホール８１，８２にメッキを施すとともに、銅箔７７，７８の表面にもメッキを施してＣｕメッキ層８３を形成する。See FIG.
Next, the
Next, after forming the through
図１２参照
次いで、レジストパターン（図示は省略）を用いて、Ｃｕメッキ層８３及び銅箔７７，７８を所定形状にエッチングすることによって配線８４を形成する。
最後にソルダーレジスト８５を形成することによって、本発明の実施例３の部品内蔵基板が完成する。See FIG.
Next, the
Finally, by forming the solder resist 85, the component built-in substrate of Example 3 of the present invention is completed.
この実施例３においては、封止樹脂７３の硬化工程において発生する半導体素子４０と多層回路基板のコア基板７０の熱膨張係数の差から生じる接合部に加わる応力を封止樹脂７３内に分散させることができ、それによって、Ａｕスタッドバンプ４１の破断が生ずることがないので、接合信頼性をさらに向上することができる。 In the third embodiment, the stress applied to the joint portion resulting from the difference in thermal expansion coefficient between the
この実施例３の部品内蔵基板に対して、上述の模擬吸湿リフロー試験を行ったところ、サンプル数を５０とした場合に、実施例３の部品内蔵基板における導通抵抗の上昇率は５％以下であり、良好な接合信頼性が得られていることが確認された。 When the above simulated moisture absorption reflow test was performed on the component-embedded substrate of Example 3, when the number of samples was 50, the increase rate of the conduction resistance in the component-embedded substrate of Example 3 was 5% or less. It was confirmed that good bonding reliability was obtained.
また、この実施例３の部品内蔵基板に対して、上述の超音波映像装置による接合部の観察を行ったところ、各サンプルの接合部に剥離が観察されず、また、このときの半導体素子４０と多層回路基板のコア基板７０のクリアランスは約１５μｍであり、接合信頼性および半導体素子４０と多層回路基板のコア基板７０のクリアランスの確保が両立できた。 Further, when the joint portion of the component built-in substrate of Example 3 was observed by the above-described ultrasonic imaging apparatus, no peeling was observed at the joint portion of each sample, and the
次に、本発明の効果を確認するための比較実験を行ったので説明する。
〔比較例１〕
この比較例１においては、フリップチップボンディング工程において、Ａｕスタッドバンプに荷重をかけると同時に、接着剤の硬化を行う圧接方式を用いた。
具体的には、実施例１と同様の部材を用いて、塗布機ＦＡＤ３２０ｓ（武蔵エンジニアリング製商品型番）を用いて、厚さ０．３５ｍｍの多層回路基板の内層回路上に封止樹脂ＵＦＲ１０７（ナガセケムテックス製商品型番）を塗布し、フリップチップボンダＦＣＢ−２Ｍ（パナソニックＦＳエンジニアリング製商品型番）を用いて、半導体素子を位置合わせした後、加熱温度２００℃、荷重２ｋｇで１０秒間接合を行い、最後に恒温槽を用いて１５０℃で２時間硬化させた。Next, a comparative experiment for confirming the effect of the present invention will be described.
[Comparative Example 1]
In this comparative example 1, in the flip chip bonding process, a pressure contact method in which a load is applied to the Au stud bump and at the same time the adhesive is cured is used.
Specifically, using the same member as in Example 1, using a coating machine FAD320s (product model number manufactured by Musashi Engineering), a sealing resin UFR107 (Nagase) is formed on the inner layer circuit of a multilayer circuit board having a thickness of 0.35 mm. After applying the Chemtex product model) and aligning the semiconductor elements using the flip chip bonder FCB-2M (Panasonic FS Engineering product model number), bonding is performed for 10 seconds at a heating temperature of 200 ° C. and a load of 2 kg. Finally, it was cured at 150 ° C. for 2 hours using a thermostatic bath.
この比較例１の部品内蔵基板に対して、上述の模擬吸湿リフロー試験を行ったところ、５０サンプル中２８サンプルが不良となった。 When the above simulated moisture absorption reflow test was performed on the component-embedded substrate of Comparative Example 1, 28 samples out of 50 samples were defective.
この比較例１の部品内蔵基板の不良サンプルを断面研磨し、観察した結果、Ａｕスタッドバンプと多層回路基板の内層回路電極の接触部に浮きが見られた。
これは、Ａｕスタッドバンプの潰れ量が少なかったため、接合荷重不足により、接合部が断線したものと推測される。
また、このときの半導体素子と内層回路のクリアランスは平均で１３μｍであった。As a result of observing the cross section of the defective sample of the component built-in substrate of Comparative Example 1 and observing it, floating was observed at the contact portion between the Au stud bump and the inner layer circuit electrode of the multilayer circuit substrate.
This is presumed that the joining portion was disconnected due to insufficient joining load because the amount of collapse of the Au stud bump was small.
The clearance between the semiconductor element and the inner layer circuit at this time was 13 μm on average.
〔比較例２〕
また、比較例２においては、接合工程における荷重を８ｋｇとした以外は、上述の比較例１と全く同じ条件で部品内蔵基板を作製した。
この比較例１の部品内蔵基板に対して、上述の模擬吸湿リフロー試験を行ったところ、５０サンプル中３サンプルが不良となった。[Comparative Example 2]
In Comparative Example 2, a component-embedded substrate was produced under exactly the same conditions as in Comparative Example 1 except that the load in the joining process was 8 kg.
When the above simulated moisture absorption reflow test was performed on the component-embedded substrate of Comparative Example 1, 3 samples out of 50 samples were defective.
この比較例２の部品内蔵基板に対して、上述の超音波映像装置による接合部の観察を行ったところ、接合部の半導体素子中央部に剥離が観察された。
さらに、この接合サンプルを断面研磨し、ＳＥＭ（走査型電子顕微鏡）を用いて観察した結果、接合部の中央は異物を起点とした剥離が生じていた。
また、この時の半導体素子と多層回路基板の内層回路のクリアランスは、４μｍしかなかった。When the joint part was observed on the component-embedded substrate of Comparative Example 2 by the above-described ultrasonic imaging apparatus, peeling was observed at the central part of the semiconductor element of the joint part.
Furthermore, as a result of cross-polishing this bonded sample and observing it using an SEM (scanning electron microscope), the center of the bonded portion was peeled off starting from a foreign material.
At this time, the clearance between the semiconductor element and the inner circuit of the multilayer circuit board was only 4 μm.
以上の比較実験から明らかなように、同じ加圧条件及び加熱条件であっても、金属ナノ粒子を用いることによって接合部が焼結した金属或いは合金化した金属による金属間結合による接合が形成されるため、単なる、封止樹脂による圧接方式に比べてクリアランスを損なうことなく良好な電気的接触を実現することができる。 As is clear from the comparative experiment described above, even when the same pressure and heating conditions are used, the joint is formed by the metal-metal bond between the sintered metal or the alloyed metal by using the metal nanoparticles. Therefore, it is possible to realize good electrical contact without impairing the clearance as compared with a simple pressure welding method using a sealing resin.
また、接合に際しては過大の荷重をかける必要がないため、Ａｕスタッドバンプが押し潰されて隣接するＡｕスタッドバンプと接触して短絡が発生することもないので、歩留り或いは信頼性が向上する。 Further, since it is not necessary to apply an excessive load at the time of joining, the Au stud bump is crushed and does not contact with the adjacent Au stud bump to cause a short circuit, so that the yield or reliability is improved.
以上、本発明の各実施例を説明してきたが、本発明は各実施例に記載された構成・条件等に限られるものではなく各種の変更が可能であり、例えば、上記半導体チップのサイズ或いはＡｕスタッドバンプのサイズ及びピッチは単なる一例であり、各種のサイズの半導体チップに適用されるものである。 Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example, the size of the semiconductor chip or The size and pitch of the Au stud bumps are merely examples, and are applied to semiconductor chips of various sizes.
また、上記の各実施例においては、接点材料を構成する金属ナノ粒子としてＡｇナノ粒子を用いているが、Ａｇナノ粒子に限られるものではなく、Ｓｎナノ粒子を用いても良いものであり、この場合には、Ａｕと合金化するので、Ａｕスタッドバンプ及びパッドの表面のＡｕ層と合金化して接合が強固になる。 In each of the above embodiments, Ag nanoparticles are used as the metal nanoparticles constituting the contact material. However, the present invention is not limited to Ag nanoparticles, and Sn nanoparticles may be used. In this case, since it is alloyed with Au, it is alloyed with the Au layer on the surface of the Au stud bump and the pad, thereby strengthening the bonding.
また、金属ナノ粒子は、Ａｇ、Ｓｎに限られるものではなく、Ｂｉ、Ｚｎ、Ｎｉ或いはＩｎからなるナノ粒子を用いても良いものであり、さらには、Ａｇ−Ｓｎ合金ナノ粒子等のこれらの金属の合金ナノ粒子を用いても良いものである。 In addition, the metal nanoparticles are not limited to Ag and Sn, and nanoparticles made of Bi, Zn, Ni, or In may be used. Furthermore, these Ag-Sn alloy nanoparticles and the like may be used. Metal alloy nanoparticles may also be used.
また、上記の各実施例においては、接点材料の転写工程において、接点材料が未乾燥・未硬化の状態で行っているが、予めプリベークにより、例えば、１２０℃のプリベークにより半乾燥・予備焼結した状態転写を行っても良いものである。 Further, in each of the above embodiments, the contact material is transferred in an undried and uncured state in the contact material transfer step, but is pre-baked, for example, pre-baked at 120 ° C. and semi-dried / pre-sintered The transferred state may be performed.
ここで、再び、図１を参照して、本発明の詳細な特徴を改めて説明する。
再び、図１参照
（付記１） 電子部品１の接続端子２と多層回路基板３の内層回路の接続電極５とを接続するとともに、前記電子部品１を覆うように多層配線構造８を設けた部品内蔵基板の製造方法において、前記接続端子２と前記接続電極５との間に平均粒径が５０ｎｍ〜２００ｎｍのナノ粒径の金属粒子６を介在させる工程と、前記金属粒子６を焼結させて前記接続端子２と前記接続電極５との電気的接続を得る工程とを有することを特徴とする部品内蔵基板の製造方法。
（付記２） 上記金属粒子６として、上記接続端子２及び接続電極５の少なくとも一方と合金化する金属粒子６を使用することを特徴とする付記１記載の部品内蔵基板の製造方法。
（付記３） 上記金属粒子６が、Ａｇ、Ｓｎ、Ｂｉ、Ｚｎ、Ｎｉ、Ｉｎの内の少なくとも一種類の金属からなることを特徴とする付記１または２に記載の部品内蔵基板の製造方法。
（付記４） 上記金属粒子６を焼結させる工程における焼結温度が２５０℃以下であることを特徴とする付記１乃至３のいずれか１に記載の部品内蔵基板の製造方法。
（付記５） 上記金属粒子６を上記接続端子２と上記接続電極５との間に介在させる工程において、前記金属粒子６を合成樹脂中に分散させた材料を前記接続端子２に転写することを特徴とする付記１乃至４のいずれか１に記載の部品内蔵基板の製造方法。
（付記６） 上記接続端子２と上記接続電極５とを接続した後に、上記電子部品１と上記多層回路基板３との間に封止用の合成樹脂を注入する工程を有することを特徴とする付記１乃至３のいずれか１に記載の部品内蔵基板の製造方法。
（付記７） 上記接続端子２と上記接続電極５とを接続する前に、上記多層回路基板３上に封止用の合成樹脂を予め形成しておき、前記接続端子２を上記金属粒子６を介して前記接続電極５に圧接させたのち、前記接続端子２と前記接続電極５との接続及び前記合成樹脂の硬化とを同時的に行うことを特徴とする付記１乃至３のいずれか１に記載の部品内蔵基板の製造方法。
（付記８） 上記合成樹脂を硬化させたのち、プリプレグを用いて上記電子部品１を覆うように、上記内層回路と電気的に接続する多層配線構造８を形成する工程を有することを特徴とする付記１乃至５のいずれか１に記載の部品内蔵基板の製造方法。
（付記９） 付記１乃至８のいずれか１に記載の部品内蔵基板の製造方法を用いて製造された部品内蔵基板。Here, the detailed features of the present invention will be described again with reference to FIG.
Again see Figure 1
(Supplementary Note 1) A method of manufacturing a component-embedded board in which the
(Additional remark 2) The
(Additional remark 3) The said
(Additional remark 4) The sintering temperature in the process of sintering the said
(Supplementary Note 5) In the step of interposing the
(Additional remark 6) It has the process of inject | pouring the synthetic resin for sealing between the said
(Appendix 7) Before connecting the
(Additional remark 8) It has the process of forming the
(Additional remark 9) The component built-in board manufactured using the manufacturing method of the component built-in board of any one of
本発明の活用例としては、半導体集積回路チップを内蔵した部品内蔵基板が典型的なものであるが、内蔵される電子部品は半導体集積回路チップに限られるものではなく、Ｌ，Ｃ，Ｒ等の受動部品でも良く、或いは、薄膜ＳＡＷデバイス等でも良く、内蔵される電子部品は限定されないものである。 As a practical example of the present invention, a component-embedded substrate incorporating a semiconductor integrated circuit chip is typical, but the built-in electronic component is not limited to a semiconductor integrated circuit chip, and L, C, R, etc. The passive component may be a thin film SAW device or the like, and the built-in electronic component is not limited.
１ 電子部品
２ 接続端子
３ 多層回路
４ 内層回路
５ 接続電極
６ 金属粒子
７ 封止樹脂
８ 多層配線構造
１１ 電子部品
１２ Ａｕスタッドバンプ
１３ 接点材料
１４ 金属ナノ粒子
１５ 合成樹脂
２１ 多層回路基板
２２ バンプ電極
２３ Ｎｉ層
２４ Ａｕ層
２５ Ａｇ焼結層
２６ Ｓｎ焼結層
２７ ＡｕＳｎ層
３１ 転写ステージ
３２ 接点材料
４０ 半導体素子
４１ Ａｕスタッドバンプ
５０ 内層回路
５１ パッド
５２ シリンジ
５３ 合成樹脂
５４ 封止樹脂
５５ プリプレグ
５６ 接続ビア
５７ 多層配線構造
６０ 内層回路
６１ パッド
６２ 合成樹脂
６３ 封止樹脂
６４ プリプレグ
６５ 接続ビア
６６ 多層配線構造
７０ コア基板
７１ パッド
７２ 合成樹脂
７３ 封止樹脂
７４ プリプレグ
７５，７６ 樹脂付き銅箔
７７，７８ 銅箔
７９，８０ 樹脂
８１，８２ スルーホール
８３ Ｃｕメッキ層
８４ 配線
８５ ソルダーレジストDESCRIPTION OF
Claims (5)
Translated fromJapanesePriority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| JP2007083397AJP2008244191A (en) | 2007-03-28 | 2007-03-28 | Manufacturing method of component-embedded substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007083397AJP2008244191A (en) | 2007-03-28 | 2007-03-28 | Manufacturing method of component-embedded substrate |
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|---|---|
| JP2008244191Atrue JP2008244191A (en) | 2008-10-09 |
Family
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| JP2007083397APendingJP2008244191A (en) | 2007-03-28 | 2007-03-28 | Manufacturing method of component-embedded substrate |
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| JP (1) | JP2008244191A (en) |
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| JP2003174141A (en)* | 2001-09-27 | 2003-06-20 | Dt Circuit Technology Co Ltd | Semiconductor device and method for manufacturing the same |
| JP2004146731A (en)* | 2002-10-28 | 2004-05-20 | Mitsubishi Electric Corp | Method for manufacturing multilayer wiring substrate |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010070103A1 (en)* | 2008-12-19 | 2010-06-24 | 3D Plus | Method for the collective production of electronic modules for surface mounting |
| FR2940521A1 (en)* | 2008-12-19 | 2010-06-25 | 3D Plus | COLLECTIVE MANUFACTURING METHOD OF ELECTRONIC MODULES FOR SURFACE MOUNTING |
| US8359740B2 (en) | 2008-12-19 | 2013-01-29 | 3D Plus | Process for the wafer-scale fabrication of electronic modules for surface mounting |
| JP2011228422A (en)* | 2010-04-19 | 2011-11-10 | Dainippon Printing Co Ltd | Wiring board incorporating components, and method of manufacturing the same |
| KR20140125417A (en)* | 2012-02-08 | 2014-10-28 | 크레인 일렉트로닉스, 아이엔씨. | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module |
| JP2015508235A (en)* | 2012-02-08 | 2015-03-16 | クレーン エレクトロニクス、インコーポレーテッド | Multilayer electronic device assembly and method for embedding electrical circuit elements in a three-dimensional module |
| US9888568B2 (en) | 2012-02-08 | 2018-02-06 | Crane Electronics, Inc. | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module |
| KR102103196B1 (en) | 2012-02-08 | 2020-04-22 | 크레인 일렉트로닉스, 아이엔씨. | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module |
| US11172572B2 (en) | 2012-02-08 | 2021-11-09 | Crane Electronics, Inc. | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module |
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