JP2004119944A - Semiconductor module and mounting substrate - Google Patents
Semiconductor module and mounting substrateDownload PDFInfo
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- JP2004119944A JP2004119944AJP2002285226AJP2002285226AJP2004119944AJP 2004119944 AJP2004119944 AJP 2004119944AJP 2002285226 AJP2002285226 AJP 2002285226AJP 2002285226 AJP2002285226 AJP 2002285226AJP 2004119944 AJP2004119944 AJP 2004119944A
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Abstract
Description
Translated fromJapanese【０００１】
【発明の属する技術分野】
本発明は、半導体チップをＰｂフリーはんだを用いて実装基板に実装した半導体モジュールおよびその実装基板に関するものである。
【０００２】
【従来の技術】
半導体チップを実装基板（以下、適宜、「基板」という。）に実装（ダイボンディング）する場合、半導体チップの電極と基板の配線層とをはんだ接合することが多い。このとき、良好なはんだ接合性の確保のために、溶けたはんだが配線層上で濡れ広がる程度（つまり、はんだ濡れ性）が重要となる。
従来使用されてきた主なはんだは、錫鉛共晶はんだ等のＳｎ−Ｐｂ系はんだであった。このＳｎ−Ｐｂ系はんだははんだ濡れ性が適度に良好であり、非常に扱い易いものであった。勿論、Ｓｎ−Ｐｂ系はんだを使用しても、酸化雰囲気ではんだ接合するような場合は、Ｃｕ等の配線層上に形成された酸化被膜やはんだ自身の酸化皮膜によって溶けたはんだが弾かれて、はんだ濡れ性が低下することがある。そこで、フラックス入りはんだを使用してはんだ接合性を確保する場合もあるが、フラックスによる半導体の汚染の心配やフラックスから発生するガスがボイド発生原因になる等の理由により、最近では水素還元雰囲気中等でフラックスなしのＳｎ−Ｐｂ系はんだによる接合がなされることが多くなっている。
【０００３】
ところが、Ｐｂを含有したはんだを使用した機材が廃棄等されると、そのＰｂが土壌等に溶出して環境破壊を生じるおそれがある。このため、電器メーカ等を中心にＳｎ−Ｐｂ系はんだからＰｂフリーはんだへの移行が現在進められている。このＰｂフリーはんだとして、多種のはんだが提案されているが、従来のＳｎ−Ｐｂ系はんだに匹敵する良好なはんだ濡れ性等を備えたものは得られていない。
フラックスを使用しない場合のはんだ濡れ性は、はんだの成分で決ることから、現在では、配線層等の表面性状を調整して、そのはんだ濡れ性を良好な状態とする開発が盛んになされている。例えば、次に挙げるような公報（特許文献１〜６）に関連した記載がある。なお、特許文献７として挙げた公報は、Ｐｂフリーはんだに関するものでも、実装基板や配線層の表面性状に関するものでもないが、はんだ濡れ性を部分的に制御した一例として参考までに挙げた。
【０００４】
【特許文献１】
特許３１１６３３２号公報
【特許文献２】
特開２００２−１８０２８５号公報
【特許文献３】
特開２０００−２１６５２４号公報
【特許文献４】
特開平１１−１７３２１号公報
【特許文献５】
特開平１０−２５１８６０号公報
【特許文献６】
特開平５−２９５１７号公報
【特許文献７】
特開平４−９６２５６号公報
【０００５】
【発明が解決しようとする課題】
上記公報に開示された提案等を利用すれば、はんだ濡れ性が良好となり、電極および配線層間の未はんだ部分やはんだ層中に生じていたボイドが抑制、防止されることとなる。
しかし、例えば、配線層の最表層にＡｕめっきを施した場合のように、はんだ濡れ性が著しく改善された結果、溶けたＰｂフリーはんだが想定していた電極の接合面を超えて流出するという新たな問題を本発明者は見出した。勿論、はんだ量の調整等によりはんだの流出を抑制することも考えられるが、適切なはんだ接合性を確保するには、所定厚さ以上のはんだ層（つまり、所定量のはんだ）が必要となる。
本発明は、このような事情に鑑みてなされたものである。つまり、Ｐｂフリーはんだの基板配線層上でのはんだ濡れ性を良好にした場合であっても、そのＰｂフリーはんだが想定した領域を超えて流出しない半導体モジュールを提供することを目的とする。また、そのような半導体モジュールの製造に適した実装基板を提供する。
【０００６】
【課題を解決するための手段】
本発明者は、この課題を解決すべく鋭意研究し、試行錯誤を重ねた結果、電極が接合される接合面の周囲に、はんだ濡れ性が改善されたＰｂフリーはんだの流出を抑止するための流出抑止手段を設けることを思いつき、本発明の半導体モジュール等を完成させるに至った。
（半導体モジュール）
すなわち、本発明の半導体モジュールは、少なくとも一方の主面に電極を有する半導体チップと、該電極の接合される接合面を有する配線層を備える実装基板とからなり、該電極と該接合面とが鉛（Ｐｂ）フリーはんだで接合された半導体モジュールであって、
前記実装基板は、前記接合面の周囲に設けられると共に前記Ｐｂフリーはんだが該接合面付近外に流出するのを抑止する流出抑止手段を備えることを特徴とする。
【０００７】
本発明の半導体モジュールによると、Ｐｂフリーはんだとその接合面とのはんだ濡れ性が相当良好であっても、想定外の領域へのＰｂフリーはんだの流出が流出抑止手段により抑止される。従って、接合面のはんだ濡れ性がある程度以上に良好であれば、その表面性状にさほど拘ることもなく、所望のはんだ層を従来よりも形成し易くなる。
例えば、接合面にＡｕめっき等を施して、Ｐｂフリーはんだのはんだ濡れ性を著しく改善した場合であっても、流出抑止手段により、そのはんだが周囲の配線層等へ流出することがない。このため、配線間の短絡防止やワイヤボンディングしたい領域へのはんだ流出を防止できる。そして、流出抑止手段によりはんだの濡れ広がる領域の制御も可能となるので、はんだ層の厚さ管理も容易となる。
【０００８】
ここで、はんだ濡れ性について付言しておく。本発明の場合、Ｐｂフリーはんだと配線層（接合面）とのはんだ濡れ性は、電極および配線層の間にあるはんだ層にボイドや未はんだ部分ができない程度に、良好であるが必要である。しかし、その程度以上のはんだ濡れ性は必ずしも必要ではない。従って、はんだ濡れ性の程度やはんだ層厚さ等の設定によっては、必ずしも流出抑止手段までＰｂフリーはんだが到達していなくても良い。
ただ、本発明の流出抑止手段を設けることにより、はんだ濡れ性が非常に良い場合、つまり、はんだが流出し易い場合でも、何ら問題を生じない。つまり、本発明の流出抑止手段を設けることで、Ｐｂフリーはんだの性状や配線層の表面性状等を細かく設定する必要が無く、半導体モジュールの設計自由度が増し、その製造も容易となる。
【０００９】
なお、はんだ濡れ性は、周知のとおり、接合面とはんだとの接触角によって優劣が決せられ、接触角が小さい程、はんだ濡れ性は良好となる。
また、本発明でいう接合面は、半導体チップの電極がはんだ付けされる、配線層上の想定領域を意味する。簡単にいうなら、Ｐｂフリーはんだの広がりが許容される領域を意味する。その広さは、電極と同程度でも、電極よりも広くても良い。
【００１０】
（実装基板）
本発明は、上記半導体モジュールとしてのみならず、そこで使用される実装基板としても把握することができる。
すなわち、本発明は、半導体チップの少なくとも一方の主面に設けられた電極がＰｂフリーはんだによって接合される接合面を有する配線層が形成された実装基板であって、
前記接合面の周囲に設けられ、前記Ｐｂフリーはんだが該接合面付近外に流出するのを抑止する流出抑止手段を備えることを特徴とする実装基板であっても良い。
【００１１】
【発明の実施の形態】
実施形態を挙げて本発明をより詳細に説明する。以下に説明する内容は、半導体モジュールのみならず、実装基板にも適宜該当する。
（１）流出抑止手段
本発明でいう流出抑止手段は、加熱されて溶け出したＰｂフリーはんだの流出を抑止するものであれば足る。接合面の周囲に設けられている限り、その形状（特に、開口部形状）や材質を問わない。その単純なものとして、例えば、Ｐｂフリーはんだの流出を遮蔽する遮蔽塀を考えることができる。しかし、半導体モジュールの小型化を図る観点から、流出抑止手段は薄く、生産性の良いものが好ましい。そこで、例えば、その流出抑止手段が、前記接合面よりもはんだ濡れ性が悪いはんだレジストからなると好適である。
【００１２】
はんだレジストを用いると、スクリーン印刷等により、基板上に、自在に、薄く、容易に設けることが可能となる。はんだレジストの形状は、接合面の周囲を縁取った線状でも、面状でも良い。はんだレジストは、接合面よりもはんだ濡れ性が悪ければ、その分、はんだの流出抑止効果がある。もっとも、完全にはんだの流出を防止するには、流出してきたはんだを弾く程度にはんだ濡れ性が悪いものが好ましい。Ｐｂフリーはんだの成分にもよるが、このようなはんだレジストとして、例えば、エポキシ系樹脂やアクリル系樹脂等がある。
【００１３】
はんだレジストを設けるのとは逆に、半導体チップの電極が接合される接合面付近のみ、はんだ濡れ性を良くするようにしても良い。つまり、配線層は、母層と該母層よりもはんだ濡れ性の良い被覆層とからなり、接合面をその被覆層で形成し、流出抑止手段をその母層で形成するようにしても良い。
この場合もはんだレジストを形成した場合と同様、接合面付近外へのはんだの流出が被覆層のない母層部分で抑止される。このとき、その流出を完全に防止するには、その母層がはんだを弾く程度にはんだ濡れ性が悪いものが好ましい。
この母層は、例えば、ＣｕまたはＡｌを主成分とする第１層とこの第１層上に形成されたＮｉを主成分とする第２層である。この第２層（Ｎｉ層）がはんだレジストと同様の働きをすることとなる。もっとも、この第２層は、Ｐｂフリーはんだと配線層との接合性を確保する上で非常に有効な働きをする。特に、第１層がＡｌを主成分とする場合に、Ｎｉ層（第２層）が重要となる。また、ワイヤボンディングを行う上でも、このＮｉ層の存在が有効となる。
【００１４】
とはいえ、そのＮｉ層（第２層）は、接合時におけるＰｂフリーはんだの濡れ性が悪い。そこで、接合面には、ＡｕまたはＡｇを主成分とする貴金属層が被覆されていると好ましい。この貴金属層の形成には、無電解めっきの一種であるフラッシュめっき、蒸着等が考えられる。
上述のようにはんだ濡れ性の差を利用したもの以外に、前記流出抑止手段は、前記接合面の周囲に設けた、Ｐｂフリーはんだの流出を抑止する流出抑止溝からなっても良い。
【００１５】
この流出抑止溝を設けると、流出した余分なはんだはその溝に流れこみ、その溝で囲まれた領域外へはんだが流出することが抑止される。この場合、接合面と外部との電気的導通を確保するために、接合面の周囲にある配線層を、立体的若しくは平面的に、少なくとも部分的に残存させておく必要がある。例えば、流出抑止溝の深さを配線層厚さの半分程度としたり、流出抑止溝を完全な環状とせず、溝を設けない部分を残す等である。
このように流出抑止手段としては、種々の形態を考えることができる。もっとも、接合面付近のみに、部分めっき等を行ったり、流出抑止溝を形成したりすることは生産効率の向上を図り難い。そこで、前述のはんだレジストをスクリーン印刷等する方が、生産コストの観点から現状は優位である。
【００１６】
（２）半導体チップ
半導体チップは、その種類、形状、規格、大きさ等は問わないが、当然、配線層の接合面にはんだ付けされる電極を有するものである。例えば、半導体チップが（パワー）ＭＯＳＦＥＴ、（パワー）ＩＧＢＴ等の場合、その電極は、正電極（ソース、エミッタ）、負電極（ドレイン、コレクタ）および制御電極（ゲート）等となる。
【００１７】
本発明では、電極の表面に対するＰｂフリーはんだの濡れ性について特に限定はしないが、はんだ接合性の確保に、両者のはんだ濡れ性が良好な程好ましいのはいうまでもない。もっとも、通常の半導体チップの電極であれば、電極の表面にＡｇやＡｕのめっきが施してあることが多いから、電極とＰｂフリーはんだとの間で十分なはんだ接合性が得られ、特に問題とはならない。
また、載置した基板の配線層（接合面）上に、はんだシート等を介在させて、その上に半導体チップを重ねて置くような場合、電極とＰｂフリーはんだとの間では、配線層（接合面）とＰｂフリーはんだとの間のような問題も生じない。
【００１８】
（３）Ｐｂフリーはんだ
Ｐｂフリーはんだには、Ｓｎ−Ａｇ系はんだ、Ｓｎ−Ａｇ−Ｃｕ系はんだ、Ｓｎ−Ｚｎ系はんだ、Ｓｎ−Ａｇ−Ｃｕ−Ｂｉ系はんだ等、多種多様なものがある。それぞれの特徴を生かして、各製品毎に使い分けがなされる。しかし、なかでも、信頼性、接合耐久性、融点等の点で、Ｓｎ−３％Ａｇ−０．５％ＣｕやＳｎ−３．５％Ａｇ（単位：質量％）が好ましい。
【００１９】
（４）用途
本発明の半導体モジュールは、その用途が限定されるものではないが、高信頼性が求められる機器に適する。特に、温度変化（温度サイクル）等の使用環境変化が激しい車載用機器に、本発明の半導体モジュールは適する。はんだ流出の抑止に伴い、良好なはんだ接合性が得られ、また、はんだ厚さの管理も容易となるため、安定した実装品質の、信頼性の高い半導体モジュールが得られる。
【００２０】
なお、ここでいう信頼性には、放熱不良等に伴う半導体チップの異常高温破壊の防止、温度変化サイクルの熱応力に伴うはんだ層クラック進行の防止等である。このような熱に関する信頼性は、パワーエレクトロニクス用半導体チップを基板に実装する場合、特に重要となる。
【００２１】
【実施例】
以下に、本発明の半導体モジュールに係る実施例を挙げて、より詳細に本発明を説明する。
（第１実施例）
本発明に係る第１実施例である半導体モジュール１００は、三相誘導電動機（三相モータ）の駆動制御用のインバータ装置に使用されるものである。図１は、半導体モジュール１００の要部断面図である。
半導体モジュール１００は、セラミックス配線基板（実装基板）１０と、その上に実装された半導体チップ２０と、両者間に介在するＰｂフリーはんだからなるはんだ層３０とからなる。
【００２２】
セラミックス配線基板１０は、セラミックス基板１１と、この両面に張られた配線層１２とからなる。配線層１２は、ベース層となるＡｌ層（第１層）１２１と、その上にめっきしたＮｉ層（第２層）１２２と、さらに、その上にめっきしたＡｕ層（被覆層）１２３とからなる。Ａｌ層１２１とＮｉ層１２２とによって母層が形成される。なお、Ｎｉ層１２２もＡｕ層１２３も、ともに無電解めっきにより形成される。特に、Ａｕ層１２３は、フラッシュめっきと呼ばれ、薄いめっき層からなる。
【００２３】
半導体チップ２０はＩＧＢＴ素子からなり、そのコレクタ電極２１が配線層１２に面している。そして、Ｓｎ−３％Ａｇ−０．５％Ｃｕ（質量％）の組成をもつＰｂフリーはんだからなるはんだシート３０’（図２）が溶解凝固して、コレクタ電極２１はセラミックス配線基板１０の配線層１２にはんだ付けされ、両者間にはんだ層３０が形成される。
【００２４】
ところで、配線層１２の最表層にはＡｕ層１２３が設けてあるため、Ｐｂフリーはんだであっても、はんだ濡れ性が非常に良い。従って、前記はんだシート３０’を加熱し溶解させると、そのはんだは広範囲に濡れ広がり得る。
しかし、本実施例の場合、セラミックス配線基板１０の配線層１２上にスクリーン印刷されたはんだレジスト（流出抑止手段）４０が、半導体チップ２０の外周囲を完全に縁取っている。このため、Ａｕ層１２３上で濡れ広がったはんだも、このはんだレジスト４０で流出が食止められ、それ以上、濡れ広がることはない。ちなみに、このはんだレジスト４０の材質は、例えば、エポキシ系樹脂やアクリル系樹脂である。
【００２５】
こうして、本実施例の場合、Ｐｂフリーはんだが想定した領域外へ流出することが防止され、Ｐｂフリーはんだが配線層１２上の所定域に接合された接合面１３が形成される。
なお、図１は、便宜上、Ａｕ層１２３上にはんだ層３０が形成されているように描かれているが、現実には、はんだ付け後にＡｕ層１２３がはんだ付け前の状態のまま残存している必要はない。はんだシート３０’の溶解と共に、そのＡｕ層１２３の少なくとも一部が溶解し、はんだ層３０中にＡｕが混在するからである。
【００２６】
次に、この半導体モジュール１００の製造方法について説明する。
先ず、市販または特別に製作した両面にＡｌからなる配線層が形成されたセラミックス配線基板を用意する。この両面に、順にＮｉめっき、Ａｕフラッシュめっきを施す（めっき工程）。めっき層の厚さは、Ｎｉ層が約５μｍ、Ａｕ層が約０．０５μｍ程度である。前述したように、いずれも無電解めっきである。
さらに、このセラミックス配線基板上に、前述したはんだレジストを所定の平面形状にスクリーン印刷する（レジスト印刷工程）。こうして得られたものが、前述のセラミックス配線基板１０である。
このセラミックス配線基板１０の配線層１２上に、はんだシート３０’、半導体チップ２０の順で載置する。この状態を、耐熱製のカーボン治具８０、９０で、位置決め固定をする。この様子を図２に示す。
【００２７】
次に、カーボン治具８０、９０によって固定されたワークを、水素還元リフロー炉に流す。先ず、ワークが水素雰囲気中を通ることで、水素の還元作用により、ワークの各表面（電極、配線層、はんだシート等の表面）から酸化膜が除去される（酸化膜除去工程）。これにより、各部のはんだ濡れ性が向上する。次に、ワークが高温雰囲気中を通り加熱されることで、はんだが溶融する（加熱工程）。そして、その後冷却されてはんだが凝固し（凝固工程）、半導体チップ１０のセラミックス配線基板１０への実装（ダイボンディング）は終了する。
【００２８】
（第２実施例）
本実施例の半導体モジュール２００の要部断面図を図３に示す。この半導体モジュール２００は、第１実施例に示した縁取り線状のはんだレジスト４０を、それよりも広い面状のはんだレジスト４０’としたものである。なお、図３では、第１実施例の図１と実質的に同じ部材には同じ符合を付して示した（以下の実施例についても同様）。
【００２９】
（第３実施例）
本実施例の半導体モジュール３００の要部断面図を図４に示す。この半導体モジュール３００は、前述したＮｉ層１２２とＡｕ層１２３とのはんだ濡れ性の相違を利用したものである。つまり、第１実施例のようなはんだレジストを設けず、単に、Ａｕ層１２３’の設ける領域を、想定した接合面１３の範囲に限定したものである。Ｎｉ層１２２のはんだ濡れ性はＡｕ層１２３’のはんだ濡れ性よりも悪いため、Ｎｉ層１２２ではＰｂフリーはんだが弾かれる。このため、わざわざ第１実施例のようなはんだレジスト層を設けるまでもなく、余分なはんだの濡れ広がりを制御することができる。
Ａｕ層１２３’の領域を接合面１３の所望領域に限定する方法として、例えば、その部分のみにＡｕめっきを施す方法や、一旦、全面にＡｕめっきを施して不要な部分を機械的または化学的に除去する方法がある。
【００３０】
（第４実施例）
本実施例の半導体モジュール４００の要部断面図を図５に示す。この半導体モジュール４００は、前述した配線層１２の表面に、半導体チップ２０の外周を取囲むような流出抑止溝１２５を設けたものである。本実施例では、流出抑止溝１２５での電気的導通をも確保するために、その溝深さを配線層厚さの約１／２程度とした。勿論、溝を設けない部分を形成して、その部分で電気的導通部分を確保しても良いし、配線層上で孤立した部分とは、ワイヤボンディング等で導通を確保しても良い。それらの場合、流出抑止溝の溝深さをさらに深くすることができる。
【００３１】
流出抑止溝の断面形状は、矩形状でも円形状でもそれ以外でも良い。また、その深さや幅を調整することで、その溝に流れ込むはんだ量を調整できる。
このような溝加工は、光学的な微細加工の他、エッチングのような化学的処理によっても行える。なお、セラミックス基板１１自体に予め溝を形成しておいて、その上に配線層をめっき等して、流出抑止溝が形成されるようにしても良い。
【図面の簡単な説明】
【図１】本発明の第１実施例である半導体モジュールの要部断面図である。
【図２】その製造工程の一部を示す断面図である。
【図３】本発明の第２実施例である半導体モジュールの要部断面図である。
【図４】本発明の第３実施例である半導体モジュールの要部断面図である。
【図５】本発明の第４実施例である半導体モジュールの要部断面図である。
【符号の説明】
１００ 半導体モジュール
１０ セラミックス配線基板（実装基板）
１２ 配線層
１２１ Ａｌ層（第１層）
１２２ Ｎｉ層（第２層）
１２３ Ａｕ層（被覆層）
２０ 半導体チップ
３０ はんだ層（Ｐｂフリーはんだ）
４０ はんだレジスト[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor module in which a semiconductor chip is mounted on a mounting board using Pb-free solder, and to a mounting board for the same.
[0002]
[Prior art]
When a semiconductor chip is mounted (die-bonded) on a mounting substrate (hereinafter, appropriately referred to as a “substrate”), an electrode of the semiconductor chip and a wiring layer of the substrate are often soldered. At this time, the degree to which the melted solder spreads on the wiring layer (that is, the solder wettability) is important to ensure good solder jointability.
The main solder conventionally used has been Sn-Pb based solder such as tin-lead eutectic solder. This Sn-Pb solder had moderately good solder wettability and was very easy to handle. Of course, even if the Sn-Pb solder is used, when soldering is performed in an oxidizing atmosphere, the solder melted by the oxide film formed on the wiring layer such as Cu or the oxide film of the solder itself is repelled. The solder wettability may be reduced. Therefore, solder joints may be secured by using flux-containing solder.However, recently, in a hydrogen-reducing atmosphere, etc., due to concerns such as contamination of the semiconductor by the flux and gas generated from the flux, voids may be generated. Therefore, bonding with a flux-free Sn—Pb-based solder is often performed.
[0003]
However, when the equipment using the solder containing Pb is discarded, the Pb may be eluted into the soil or the like, causing environmental destruction. For this reason, the shift from Sn-Pb-based solder to Pb-free solder is currently being promoted mainly by electric appliance manufacturers. As the Pb-free solder, various types of solders have been proposed, but no solder having good solder wettability comparable to that of the conventional Sn-Pb-based solder has been obtained.
Since the solder wettability when no flux is used is determined by the components of the solder, developments are currently underway to adjust the surface properties of the wiring layer and the like to make the solder wettability good. . For example, there are descriptions related to the following publications (Patent Documents 1 to 6). The publication cited as Patent Document 7 does not relate to Pb-free solder or the surface properties of a mounting board or a wiring layer, but is cited for reference as an example of partially controlling the solder wettability.
[0004]
[Patent Document 1]
Japanese Patent No. 3116332 [Patent Document 2]
JP 2002-180285 A [Patent Document 3]
JP 2000-216524 A [Patent Document 4]
JP-A-11-17321 [Patent Document 5]
JP-A-10-251860 [Patent Document 6]
JP-A-5-29517 [Patent Document 7]
JP-A-4-96256
[Problems to be solved by the invention]
If the proposals and the like disclosed in the above-mentioned publications are used, the solder wettability will be good, and voids generated in the unsoldered portions between the electrodes and the wiring layers and in the solder layers will be suppressed and prevented.
However, for example, as in the case where Au plating is applied to the outermost layer of the wiring layer, as a result of remarkably improved solder wettability, the melted Pb-free solder flows out beyond the expected electrode bonding surface. The inventor has found a new problem. Of course, it is conceivable to suppress the outflow of solder by adjusting the amount of solder, but a solder layer having a predetermined thickness or more (that is, a predetermined amount of solder) is required to secure appropriate solder jointability. .
The present invention has been made in view of such circumstances. That is, it is an object of the present invention to provide a semiconductor module in which the Pb-free solder does not flow out of an expected area even when the solder wettability of the Pb-free solder on the substrate wiring layer is improved. Further, the present invention provides a mounting board suitable for manufacturing such a semiconductor module.
[0006]
[Means for Solving the Problems]
The inventor of the present invention has conducted intensive studies to solve this problem, and as a result of repeated trial and error, as a result, to prevent the outflow of Pb-free solder with improved solder wettability around the joint surface where the electrodes are joined. We came up with the idea of providing an outflow suppressing means, and completed the semiconductor module and the like of the present invention.
(Semiconductor module)
That is, the semiconductor module of the present invention includes a semiconductor chip having an electrode on at least one main surface, and a mounting substrate having a wiring layer having a bonding surface to which the electrode is bonded, wherein the electrode and the bonding surface are A semiconductor module joined by lead (Pb) -free solder,
The mounting board is provided around the joint surface and includes outflow suppressing means for preventing the Pb-free solder from flowing out of the vicinity of the joint surface.
[0007]
According to the semiconductor module of the present invention, even if the solder wettability between the Pb-free solder and its joint surface is considerably good, the outflow of the Pb-free solder to an unexpected area is suppressed by the outflow suppressing means. Therefore, if the solder wettability of the joint surface is better than a certain level, it becomes easier to form a desired solder layer than before, without being concerned with the surface properties.
For example, even when the joint surface is plated with Au or the like and the solder wettability of the Pb-free solder is remarkably improved, the solder does not flow out to the surrounding wiring layer or the like by the flow-out suppressing means. For this reason, it is possible to prevent short-circuiting between wirings and prevent solder from flowing out to a region where wire bonding is desired. Since the outflow suppressing means can control the region where the solder spreads, the thickness of the solder layer can be easily controlled.
[0008]
Here, the solder wettability is additionally described. In the case of the present invention, the solder wettability between the Pb-free solder and the wiring layer (joining surface) needs to be good enough that voids and unsolder portions are not formed in the solder layer between the electrode and the wiring layer. . However, a solder wettability higher than that is not always necessary. Therefore, depending on the setting of the degree of solder wettability, the thickness of the solder layer, and the like, the Pb-free solder does not necessarily have to reach the outflow suppressing means.
However, by providing the outflow suppressing means of the present invention, there is no problem even when the solder wettability is very good, that is, even when the solder easily flows out. In other words, by providing the outflow suppressing means of the present invention, it is not necessary to finely set the properties of the Pb-free solder, the surface properties of the wiring layer, and the like, so that the degree of freedom in designing the semiconductor module is increased and its manufacture is facilitated.
[0009]
As is well known, the solder wettability is determined by the contact angle between the joint surface and the solder, and the smaller the contact angle, the better the solder wettability.
In addition, the bonding surface in the present invention means an assumed area on a wiring layer to which electrodes of a semiconductor chip are soldered. To put it simply, it means a region where the spread of the Pb-free solder is allowed. The area may be equal to or wider than the electrode.
[0010]
(Mounting board)
The present invention can be understood not only as the above-described semiconductor module but also as a mounting board used therein.
That is, the present invention is a mounting board on which a wiring layer having a bonding surface to which electrodes provided on at least one main surface of a semiconductor chip are bonded by Pb-free solder is formed,
The mounting substrate may be provided with outflow suppressing means provided around the bonding surface and for preventing the Pb-free solder from flowing out of the vicinity of the bonding surface.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention will be described in more detail with reference to embodiments. The contents described below apply not only to the semiconductor module but also to the mounting board as appropriate.
(1) Outflow inhibiting means The outflow inhibiting means in the present invention is sufficient as long as it is capable of inhibiting the outflow of the heated and melted Pb-free solder. The shape (particularly, the shape of the opening) and the material are not limited as long as it is provided around the joining surface. As a simple one, for example, a shielding wall that shields outflow of Pb-free solder can be considered. However, from the viewpoint of reducing the size of the semiconductor module, the outflow suppressing means is preferably thin and has good productivity. Therefore, for example, it is preferable that the outflow suppressing means be made of a solder resist having lower solder wettability than the bonding surface.
[0012]
When a solder resist is used, it can be freely, thinly, and easily provided on a substrate by screen printing or the like. The shape of the solder resist may be a linear shape bordering the periphery of the joint surface or a planar shape. If the solder wettability of the solder resist is lower than that of the joint surface, the solder resist has the effect of suppressing the outflow of the solder. However, in order to completely prevent the outflow of the solder, it is preferable that the solder has low wettability enough to repel the outflowing solder. Although it depends on the components of the Pb-free solder, such a solder resist includes, for example, an epoxy resin or an acrylic resin.
[0013]
Contrary to the provision of the solder resist, the solder wettability may be improved only in the vicinity of the joint surface where the electrodes of the semiconductor chip are joined. That is, the wiring layer may include a mother layer and a coating layer having better solder wettability than the mother layer, and the bonding surface may be formed by the coating layer, and the outflow suppressing means may be formed by the mother layer. .
In this case, similarly to the case where the solder resist is formed, the outflow of the solder to the vicinity of the joint surface is suppressed in the base layer portion without the coating layer. At this time, in order to completely prevent the outflow, it is preferable that the base layer has poor solder wettability such that the base layer repels the solder.
The mother layer is, for example, a first layer mainly composed of Cu or Al and a second layer mainly composed of Ni formed on the first layer. This second layer (Ni layer) functions similarly to the solder resist. However, the second layer has a very effective function in securing the bonding property between the Pb-free solder and the wiring layer. In particular, when the first layer is mainly composed of Al, the Ni layer (second layer) is important. Also, the presence of this Ni layer is effective in performing wire bonding.
[0014]
However, the Ni layer (second layer) has poor wettability of the Pb-free solder at the time of joining. Therefore, it is preferable that the bonding surface be covered with a noble metal layer containing Au or Ag as a main component. The noble metal layer may be formed by flash plating, vapor deposition, or the like, which is a type of electroless plating.
In addition to the method using the difference in solder wettability as described above, the outflow inhibiting means may be formed by an outflow inhibiting groove provided around the joint surface for inhibiting the outflow of Pb-free solder.
[0015]
When the outflow prevention groove is provided, excess solder that has flowed out flows into the groove, and the outflow of the solder out of the region surrounded by the groove is suppressed. In this case, in order to secure electrical continuity between the bonding surface and the outside, it is necessary to leave the wiring layer around the bonding surface at least partially in a three-dimensional or planar manner. For example, the depth of the outflow inhibiting groove is set to about half of the thickness of the wiring layer, or the outflow inhibiting groove is not formed in a complete annular shape, and a portion where no groove is provided is left.
As described above, various forms can be considered as the outflow suppressing means. However, it is difficult to improve production efficiency by performing partial plating or the like or forming outflow prevention grooves only near the joint surface. Therefore, screen printing of the above-mentioned solder resist is currently superior from the viewpoint of production cost.
[0016]
(2) Semiconductor chip The semiconductor chip is not limited in its type, shape, standard, size and the like, but naturally has an electrode to be soldered to the joint surface of the wiring layer. For example, when the semiconductor chip is a (power) MOSFET, a (power) IGBT, or the like, its electrodes are a positive electrode (source, emitter), a negative electrode (drain, collector), a control electrode (gate), and the like.
[0017]
In the present invention, the wettability of the Pb-free solder to the surface of the electrode is not particularly limited, but it goes without saying that the better the solder wettability of both is, the better the solder joint property is. However, in the case of ordinary semiconductor chip electrodes, since the surface of the electrode is often plated with Ag or Au, sufficient solder jointability can be obtained between the electrode and the Pb-free solder, which is a particular problem. Does not.
Further, when a semiconductor chip is overlaid on a wiring layer (joining surface) of a mounted substrate with a solder sheet or the like interposed therebetween, a wiring layer ( There is no problem between the joint surface) and the Pb-free solder.
[0018]
(3) Pb-free solder There are various types of Pb-free solder, such as Sn-Ag solder, Sn-Ag-Cu solder, Sn-Zn solder, Sn-Ag-Cu-Bi solder. Taking advantage of each feature, each product is used properly. However, among these, Sn-3% Ag-0.5% Cu and Sn-3.5% Ag (unit: mass%) are preferable in terms of reliability, joining durability, melting point and the like.
[0019]
(4) Use The semiconductor module of the present invention is not limited in its use, but is suitable for equipment requiring high reliability. In particular, the semiconductor module of the present invention is suitable for in-vehicle equipment in which use environment changes such as temperature changes (temperature cycles) are severe. With the prevention of solder outflow, good solder jointability can be obtained, and the solder thickness can be easily controlled, so that a highly reliable semiconductor module with stable mounting quality can be obtained.
[0020]
Note that the reliability here refers to prevention of abnormal high-temperature destruction of the semiconductor chip due to poor heat radiation, prevention of solder layer crack progress due to thermal stress in a temperature change cycle, and the like. Such reliability regarding heat is particularly important when a semiconductor chip for power electronics is mounted on a substrate.
[0021]
【Example】
Hereinafter, the present invention will be described in more detail with reference to examples according to the semiconductor module of the present invention.
(First embodiment)
A
The
[0022]
The
[0023]
The
[0024]
By the way, since the
However, in the case of this embodiment, the solder resist (outflow prevention means) 40 screen-printed on the
[0025]
In this way, in the case of the present embodiment, the Pb-free solder is prevented from flowing out of the assumed area, and the
In FIG. 1, for convenience, the
[0026]
Next, a method for manufacturing the
First, a ceramic wiring board having a commercially available or specially manufactured wiring layer made of Al formed on both surfaces is prepared. Ni plating and Au flash plating are sequentially applied to both surfaces (plating step). The thickness of the plating layer is about 5 μm for the Ni layer and about 0.05 μm for the Au layer. As described above, all are electroless plating.
Further, the above-mentioned solder resist is screen-printed on the ceramic wiring substrate in a predetermined planar shape (resist printing step). The result is the above-described
On the
[0027]
Next, the work fixed by the carbon jigs 80 and 90 flows into a hydrogen reduction reflow furnace. First, an oxide film is removed from each surface (the surface of an electrode, a wiring layer, a solder sheet, or the like) of the work by the reduction action of hydrogen by passing the work in a hydrogen atmosphere (an oxide film removing step). Thereby, the solder wettability of each part is improved. Next, the solder is melted by heating the work through the high-temperature atmosphere (heating step). Then, after cooling, the solder is solidified (solidification step), and the mounting of the
[0028]
(Second embodiment)
FIG. 3 is a cross-sectional view of a main part of the
[0029]
(Third embodiment)
FIG. 4 is a cross-sectional view of a main part of the
As a method of limiting the region of the
[0030]
(Fourth embodiment)
FIG. 5 is a cross-sectional view of a main part of the
[0031]
The cross-sectional shape of the outflow prevention groove may be rectangular, circular, or any other shape. Also, by adjusting the depth and width, the amount of solder flowing into the groove can be adjusted.
Such groove processing can be performed by chemical processing such as etching, in addition to optical fine processing. A groove may be formed in the ceramic substrate 11 itself in advance, and a wiring layer may be plated thereon to form the outflow suppressing groove.
[Brief description of the drawings]
FIG. 1 is a sectional view of a main part of a semiconductor module according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a part of the manufacturing process.
FIG. 3 is a sectional view of a main part of a semiconductor module according to a second embodiment of the present invention.
FIG. 4 is a sectional view of a main part of a semiconductor module according to a third embodiment of the present invention.
FIG. 5 is a sectional view of a main part of a semiconductor module according to a fourth embodiment of the present invention.
[Explanation of symbols]
100
12
122 Ni layer (second layer)
123 Au layer (coating layer)
20
40 Solder resist
Claims (7)
Translated fromJapanese該電極の接合される接合面を有する配線層を備える実装基板とからなり、
該電極と該接合面とが鉛（Ｐｂ）フリーはんだで接合された半導体モジュールであって、
前記実装基板は、前記接合面の周囲に設けられると共に前記Ｐｂフリーはんだが該接合面付近外に流出するのを抑止する流出抑止手段を備えることを特徴とする半導体モジュール。A semiconductor chip having electrodes on at least one main surface,
A mounting substrate comprising a wiring layer having a bonding surface to which the electrodes are bonded,
A semiconductor module in which the electrode and the joining surface are joined with lead (Pb) -free solder,
The semiconductor module according to claim 1, wherein the mounting board is provided around the joint surface and includes outflow suppressing means for preventing the Pb-free solder from flowing out of the vicinity of the joint surface.
前記接合面は該被覆層により形成され、
前記流出抑止手段は該母層により形成される請求項１に記載の半導体モジュール。The wiring layer includes a mother layer and a coating layer having better solder wettability than the mother layer,
The joining surface is formed by the coating layer;
2. The semiconductor module according to claim 1, wherein said outflow suppressing means is formed by said mother layer.
前記接合面の周囲に設けられ、前記Ｐｂフリーはんだが該接合面付近外に流出するのを抑止する流出抑止手段を備えることを特徴とする実装基板。A mounting substrate on which a wiring layer having a bonding surface to which electrodes provided on at least one main surface of a semiconductor chip are bonded by Pb-free solder is formed,
A mounting board provided around the joining surface, the outflow inhibiting means for inhibiting the Pb-free solder from flowing out of the vicinity of the joining surface;
Priority Applications (1)
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| JP2002285226AJP2004119944A (en) | 2002-09-30 | 2002-09-30 | Semiconductor module and mounting substrate |
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| JP2002285226AJP2004119944A (en) | 2002-09-30 | 2002-09-30 | Semiconductor module and mounting substrate |
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| JP2008288415A (en)* | 2007-05-18 | 2008-11-27 | Fuji Electric Device Technology Co Ltd | Semiconductor device and manufacturing method of semiconductor device |
| JP2009054690A (en)* | 2007-08-24 | 2009-03-12 | Denso Corp | Lead frame structure |
| US7601625B2 (en) | 2004-04-20 | 2009-10-13 | Denso Corporation | Method for manufacturing semiconductor device having solder layer |
| JP2010123780A (en)* | 2008-11-20 | 2010-06-03 | Sony Corp | Mounting substrate, method of manufacturing the same, and display device and method of manufacturing the same |
| US8050048B2 (en) | 2007-04-29 | 2011-11-01 | Freescale Semiconductor, Inc. | Lead frame with solder flow control |
| JP2014203947A (en)* | 2013-04-04 | 2014-10-27 | 株式会社デンソー | Semiconductor device |
| JP2015032765A (en)* | 2013-08-06 | 2015-02-16 | 三菱電機株式会社 | Semiconductor device |
| US10658324B2 (en) | 2015-10-09 | 2020-05-19 | Mitsubishi Electric Corporation | Semiconductor device |
| WO2022059288A1 (en)* | 2020-09-18 | 2022-03-24 | 住友電気工業株式会社 | Semiconductor device |
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| US7601625B2 (en) | 2004-04-20 | 2009-10-13 | Denso Corporation | Method for manufacturing semiconductor device having solder layer |
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| JPWO2022059288A1 (en)* | 2020-09-18 | 2022-03-24 |
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