【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置製造に
係り、チャンバ内に放電用ガスを導入しプラズマ化する
ことによりウェハ基板に対しエッチングや成膜等の表面
処理を施す半導体装置の製造方法及びプラズマ処理装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and a method of manufacturing a semiconductor device in which a surface treatment such as etching or film formation is performed on a wafer substrate by introducing a discharge gas into a chamber to generate plasma. And a plasma processing apparatus.
【０００２】[0002]
【従来の技術】半導体製造ラインには各種プラズマ処理
装置が配設される。ドライエッチング装置もその一つで
あり、通常、チャンバー内はグロー放電領域でプラズマ
を発生させる。これにより、導入した反応ガスをプラズ
マ化し、所定のエッチング処理を施す。2. Description of the Related Art Various plasma processing apparatuses are installed in a semiconductor manufacturing line. The dry etching device is one of them, and normally, plasma is generated in the glow discharge region in the chamber. As a result, the introduced reaction gas is turned into plasma and subjected to a predetermined etching treatment.
【０００３】上記プラズマ処理中、異常放電が発生する
ことがある。ここでは、チャンバー内壁の凹凸状態、導
入される反応ガスの処理条件などによって発生するアー
ク等を含む異常放電をいう。異常放電によりチャンバー
内壁や電極が損傷すれば、金属汚染の原因となる。ま
た、ウェハへの異常放電発生は、ウェハ基板処理表面の
予定外の変形、損傷や破壊の原因になり、耐性劣化や電
気的致命傷が与えられることが少なくない。An abnormal discharge may occur during the plasma treatment. Here, it means an abnormal discharge including an arc or the like generated depending on the uneven state of the inner wall of the chamber, the processing conditions of the reaction gas introduced, and the like. If the inner wall of the chamber or the electrode is damaged by the abnormal discharge, it causes metal contamination. Further, the occurrence of abnormal discharge on a wafer causes undesired deformation, damage, or destruction of the surface of the wafer substrate to be processed, which often causes deterioration of resistance or fatal electrical damage.
【０００４】上記異常放電に関し、チャンバー内のアー
ク発光をモニタするために窓を設け異常放電を検出する
技術はあるが、応答速度、感度共に低い。石英からなる
窓はエッチング雰囲気に曝されるので表面荒れ、反応生
成物の堆積などが避けられず、処理時間が長くなると窓
の透過率が減少し、感度はますます低下する。Regarding the above-mentioned abnormal discharge, there is a technique for detecting the abnormal discharge by providing a window for monitoring arc emission in the chamber, but the response speed and sensitivity are low. Since the window made of quartz is exposed to the etching atmosphere, surface roughness and deposition of reaction products are unavoidable, and the transmittance of the window decreases as the processing time increases, and the sensitivity further decreases.
【０００５】[0005]
【発明が解決しようとする課題】特にウェハへの異常放
電発生は、処理中には発見され難く、大量のウェハにつ
いて基板処理表面のオーバーエッチング等を含む予定外
の変形、さらには損傷や破壊、耐性劣化や電気的致命傷
が与えられる可能性がある。処理後にウェハ全数の外観
検査等を行い、放電異常の有無を確認せざるを得ない状
況であった。In particular, the occurrence of abnormal discharge on a wafer is difficult to detect during processing, and undesired deformation including over-etching of the substrate processing surface of a large number of wafers, and further damage and destruction, There is a possibility of deterioration of resistance and electric fatal injury. After the processing, the appearance of all the wafers was inspected, and it was unavoidable to confirm the presence or absence of discharge abnormality.
【０００６】本発明は上記のような事情を考慮してなさ
れたもので、チャンバー内の放電異常を容易にリアルタ
イムでモニタ可能とし、大量の不良生産を防止する半導
体装置の製造方法及びプラズマ処理装置を提供しようと
するものである。The present invention has been made in consideration of the above circumstances, and a semiconductor device manufacturing method and a plasma processing apparatus capable of easily monitoring a discharge abnormality in a chamber in real time and preventing a large amount of defective production. Is to provide.
【０００７】[0007]
【課題を解決するための手段】本発明の［請求項１］に
係る半導体装置の製造方法は、電極間に基板の載置され
るチャンバー内が、供給される反応ガスの放電によって
プラズマ化され、基板表面をプラズマ処理する半導体装
置の製造方法であって、前記プラズマによる処理中の放
電異常が、前記電極間に印加される高周波電力に関する
整合時の所定範囲より大きい被制御値の変動に伴う電圧
変化によってモニタされることを特徴とする。According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a chamber in which a substrate is placed between electrodes is turned into plasma by discharge of a supplied reaction gas. A method of manufacturing a semiconductor device in which a substrate surface is plasma-treated, wherein a discharge abnormality during the plasma treatment is accompanied by a change in a controlled value larger than a predetermined range at the time of matching regarding high-frequency power applied between the electrodes. It is characterized by being monitored by a voltage change.
【０００８】上記本発明に係る半導体装置の製造方法に
よれば、チャンバー内で放電異常が起こると、通常グロ
ー放電を保つようにしている電極間の高周波電力に関す
る整合時、所定範囲より大きな被制御値が与えられるよ
うになる。その変動に対する電圧変化を捉えることによ
り、処理基板に悪影響を及ぼす放電異常の検出がリアル
タイムで実施できる。According to the method of manufacturing a semiconductor device according to the present invention, when abnormal discharge occurs in the chamber, when the high frequency power between the electrodes is adjusted so as to normally maintain glow discharge, the controlled area larger than a predetermined range is controlled. The value will be given. By catching the voltage change with respect to the fluctuation, it is possible to detect the discharge abnormality that adversely affects the processing substrate in real time.
【０００９】なお、上記［請求項１］に係る［請求項
２］として、上記整合時の被制御値は前記高周波電力の
電圧に対する電流の位相が調整される第１の被制御値と
負荷側のインピーダンスの絶対値が調整される第２の被
制御値を含むことを特徴とする。すなわち、放電異常で
あると第１、第２の被制御値の与えられ方が所定範囲よ
り大きい電圧変化をみることとなる。[0009] As [Claim 2] according to [Claim 1], the controlled value at the time of matching is the first controlled value with which the phase of the current with respect to the voltage of the high frequency power is adjusted and the load side. A second controlled value for which the absolute value of the impedance of is adjusted. That is, if the discharge is abnormal, a voltage change in which the first and second controlled values are given is larger than the predetermined range.
【００１０】本発明の［請求項３］に係る半導体装置の
製造方法は、電極間に基板の載置されるチャンバー内
が、供給される反応ガスの放電によってプラズマ化さ
れ、基板表面をプラズマ処理する半導体装置の製造方法
であって、前記プラズマによる処理中の放電異常が、前
記電極間における前記基板の固定に利用される静電吸着
の電圧変化によってモニタされることを特徴とする。According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, the inside of the chamber in which the substrate is placed between the electrodes is turned into plasma by the discharge of the supplied reaction gas, and the substrate surface is plasma-treated. The method of manufacturing a semiconductor device according to claim 1, wherein the abnormal discharge during the treatment with the plasma is monitored by a voltage change of electrostatic attraction used for fixing the substrate between the electrodes.
【００１１】上記本発明に係る半導体装置の製造方法に
よれば、電極間における基板の固定に利用される静電吸
着の電圧変化に着目する。チャンバー内で放電異常が起
こると、通常のグロー放電状態とは異なる静電吸着時の
電圧変化がみられる。この電圧変動を捉えることによ
り、処理基板に悪影響を及ぼす放電異常の検出がリアル
タイムで実施できる。In the method of manufacturing a semiconductor device according to the present invention, attention is paid to the voltage change of electrostatic attraction used for fixing the substrate between the electrodes. When an abnormal discharge occurs in the chamber, a voltage change during electrostatic attraction, which is different from the normal glow discharge state, is observed. By catching this voltage fluctuation, it is possible to detect in real time a discharge abnormality that adversely affects the processing substrate.
【００１２】本発明の［請求項４］に係る半導体装置の
製造方法は、［請求項１］〜［請求項３］いずれかに係
り、前記モニタ結果に応じて前記電極間への電圧印加を
制御することを特徴とする。また、本発明の［請求項
５］に係る半導体装置の製造方法は、［請求項１］〜
［請求項３］いずれかに係り、前記モニタ結果は放電異
常の頻度を計数したデータであり、このデータに応じて
前記電極間への電圧印加を制御することを特徴とする。
モニタ結果により電圧印加を停止する制御も含まれ、処
理基板に対し、異常放電による被害は最小限に抑えられ
る。The method of manufacturing a semiconductor device according to [Claim 4] of the present invention relates to any one of [Claim 1] to [Claim 3], and a voltage is applied between the electrodes according to the monitoring result. It is characterized by controlling. The semiconductor device manufacturing method according to [Claim 5] of the present invention includes [Claim 1] to [Claim 1].
[Claim 3] The monitoring result is data obtained by counting the frequency of discharge abnormality, and the voltage application between the electrodes is controlled according to the data.
Control including stopping voltage application according to the monitoring result is also included, and damage to the processing substrate due to abnormal discharge can be minimized.
【００１３】本発明の［請求項６］に係るプラズマ処理
装置は、電極間に基板を載置し真空中で少なくとも反応
ガス供給及び排気がなされるチャンバーと、前記電極間
に放電用の電圧を与え、前記反応ガスの供給されたチャ
ンバー内にプラズマを発生させる高周波電源と、前記高
周波電源から前記電極間に印加される高周波電力が少な
くともインピーダンス整合される整合回路部と、前記整
合回路部による整合時の所定範囲より大きい被制御値の
変動に伴う電圧変化を検出する電圧モニタ制御部と、を
具備したことを特徴とする。According to a sixth aspect of the present invention, there is provided a plasma processing apparatus in which a substrate is placed between electrodes and at least a reaction gas is supplied and exhausted in a vacuum, and a discharge voltage is applied between the electrodes. A high-frequency power source for generating plasma in the chamber supplied with the reaction gas, a matching circuit section in which high-frequency power applied between the electrodes from the high-frequency power source is at least impedance-matched, and matching by the matching circuit section And a voltage monitor control unit that detects a voltage change associated with a change in a controlled value that is larger than a predetermined time range.
【００１４】上記本発明に係るプラズマ処理装置によれ
ば、チャンバー内で放電異常が起こると、通常グロー放
電を保つようにしている整合回路部の被制御値が、所定
範囲より大きく変動する。その変動に対する電圧変化を
電圧モニタ制御部が捉える。これにより、処理基板に悪
影響を及ぼす放電異常の検出がリアルタイムで実施でき
る。According to the above plasma processing apparatus of the present invention, when an abnormal discharge occurs in the chamber, the controlled value of the matching circuit section which normally maintains the glow discharge fluctuates more than a predetermined range. The voltage monitor control unit catches the voltage change due to the fluctuation. As a result, it is possible to detect a discharge abnormality that adversely affects the processing substrate in real time.
【００１５】本発明の［請求項７］に係るプラズマ処理
装置は［請求項６］に係り、前記整合回路部は、前記電
極を含む前記チャンバー内の負荷側への高周波電力の電
圧に対する電流の位相及びインピーダンスの絶対値の検
出器と、この検出器に応じて位相を調整する電圧制御を
伴う第１の制御部及びインピーダンスを調整する電圧制
御を伴う第２の制御部とを含み、前記モニタ部は前記第
１の制御部及び第２の制御部からの電圧制御による所定
範囲外の電圧変化を検出することを特徴とする。A plasma processing apparatus according to [Claim 7] of the present invention is related to [Claim 6], wherein the matching circuit section supplies a current to a load high frequency power voltage in the chamber including the electrode. The monitor includes a detector of absolute values of phase and impedance, a first control unit with voltage control that adjusts the phase according to the detector, and a second control unit with voltage control that adjusts the impedance. The unit is configured to detect a voltage change outside a predetermined range due to the voltage control from the first control unit and the second control unit.
【００１６】本発明の［請求項８］に係るプラズマ処理
装置は、［請求項６］または［請求項７］に係り、前記
電圧モニタ制御部に応じて前記高周波電源からの電力供
給が制御されるインターロック回路を具備したことを特
徴とする。これにより、放電異常に応じて高周波電源か
ら電極への電力供給が自動的に停止される。処理基板に
対し、異常放電による被害は最小限に抑えられる。A plasma processing apparatus according to [Claim 8] of the present invention relates to [Claim 6] or [Claim 7], and the power supply from the high frequency power source is controlled according to the voltage monitor control unit. It is characterized by including an interlock circuit. As a result, the power supply from the high frequency power supply to the electrodes is automatically stopped according to the discharge abnormality. Damage to the processed substrate due to abnormal discharge is minimized.
【００１７】本発明の［請求項９］に係るプラズマ処理
装置は、電極間に静電吸着を利用して基板を載置し真空
中で少なくとも反応ガス供給及び排気がなされるチャン
バーと、前記電極間に放電用の電圧を与え、前記反応ガ
スの供給されたチャンバー内にプラズマを発生させる高
周波電源と、前記高周波電源から前記電極間に印加され
る高周波電力が少なくともインピーダンス整合される整
合回路部と、前記基板における静電吸着の電圧変化を検
出する電圧モニタ制御部と、を具備したことを特徴とす
る。According to a ninth aspect of the present invention, there is provided a plasma processing apparatus in which a substrate is placed between electrodes by electrostatic attraction and at least a reaction gas is supplied and exhausted in a vacuum, and the electrodes are provided. A high-frequency power supply that applies a discharge voltage between them to generate plasma in the chamber to which the reaction gas is supplied, and a matching circuit unit in which high-frequency power applied between the electrodes from the high-frequency power supply is at least impedance-matched. And a voltage monitor control unit for detecting a voltage change of electrostatic attraction on the substrate.
【００１８】上記本発明に係るプラズマ処理装置によれ
ば、チャンバー内で通常グロー放電を保つようにしてい
る電極間において放電異常が起こると、基板の固定に利
用される静電吸着の電圧変化は大きくなる。その電圧変
化を電圧モニタ制御部が捉える。これにより、処理基板
に悪影響を及ぼす放電異常の検出がリアルタイムで実施
できる。According to the above-described plasma processing apparatus of the present invention, when a discharge abnormality occurs between the electrodes that normally maintain glow discharge in the chamber, the voltage change of electrostatic attraction used for fixing the substrate is suppressed. growing. The voltage monitor control unit captures the voltage change. As a result, it is possible to detect a discharge abnormality that adversely affects the processing substrate in real time.
【００１９】本発明の［請求項１０］に係るプラズマ処
理装置は、［請求項９］に係り、前記電圧モニタ制御部
に応じて前記高周波電源からの電力供給が制御されるイ
ンターロック回路を具備したことを特徴とする。これに
より、放電異常に応じて高周波電源から電極への電力供
給が自動的に停止される。処理基板に対し、異常放電に
よる被害は最小限に抑えられる。A plasma processing apparatus according to [Claim 10] of the present invention relates to [Claim 9], and comprises an interlock circuit in which power supply from the high frequency power source is controlled in accordance with the voltage monitor control unit. It is characterized by having done. As a result, the power supply from the high frequency power supply to the electrodes is automatically stopped according to the discharge abnormality. Damage to the processed substrate due to abnormal discharge is minimized.
【００２０】[0020]
【発明の実施の形態】図１は、本発明の第１実施形態に
係る半導体装置の製造方法及びプラズマ処理装置を説明
するものであり、プラズマ処理装置としてドライエッチ
ング装置の概略構成を示している。チャンバー１１内に
は、被処理基板である半導体ウェハＷａｆの載置される
カソード電極１２が配されている。カソード電極１２に
は高周波電源１４からの高周波（ＲＦ）電力が整合回路
部１３を介して印加される。カソード電極１２に対する
アノード電極１５はここではチャンバー１１の上壁であ
り、接地されている。このチャンバー１１の上壁には導
入される反応ガス等のガス供給口１６も設けられてい
る。チャンバー１１の側面下部にはガス排出口１７が設
けられている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 illustrates a method of manufacturing a semiconductor device and a plasma processing apparatus according to a first embodiment of the present invention, and shows a schematic structure of a dry etching apparatus as a plasma processing apparatus. . In the chamber 11, a cathode electrode 12 on which a semiconductor wafer Waf, which is a substrate to be processed, is placed is arranged. Radio frequency (RF) power from a radio frequency power supply 14 is applied to the cathode electrode 12 through a matching circuit unit 13. The anode electrode 15 with respect to the cathode electrode 12 is the upper wall of the chamber 11 here and is grounded. A gas supply port 16 for the reaction gas to be introduced is also provided on the upper wall of the chamber 11. A gas outlet 17 is provided in the lower portion of the side surface of the chamber 11.
【００２１】上記カソード電極１２、アノード電極１５
間において高周波電源１４からの高周波電力が整合回路
部１３を介して印加される。これにより、通常、グロー
放電領域を保ちつつ供給される反応ガスによるプラズマ
が発生され、半導体ウェハＷａｆへのエッチング処理が
なされる。The cathode electrode 12 and the anode electrode 15
In the meantime, the high frequency power from the high frequency power supply 14 is applied through the matching circuit unit 13. As a result, plasma is generally generated by the reaction gas supplied while maintaining the glow discharge region, and the semiconductor wafer Waf is etched.
【００２２】この実施形態ではプラズマによる処理中に
放電異常が起こった場合、整合回路部１３での高周波電
力に関する整合において所定範囲より大きい被制御値の
変動が認められることに着目して、その被制御値の変動
に伴う電圧変化によって放電異常を検出する。図では、
整合回路部１３から得られる少なくとも整合時の所定範
囲より大きい被制御値の変動に伴う電圧変化を検出する
電圧モニタ制御部１８が設けられている。In this embodiment, when a discharge abnormality occurs during the treatment with plasma, attention is paid to the fact that variation in the controlled value larger than a predetermined range is recognized in the matching regarding the high frequency power in the matching circuit section 13, Discharge abnormality is detected by the voltage change accompanying the change of the control value. In the figure,
A voltage monitor control unit 18 is provided which detects a voltage change resulting from a change in a controlled value which is obtained from the matching circuit unit 13 and which is at least larger than a predetermined range at the time of matching.
【００２３】電圧モニタ制御部１８はチャンバー１１内
の放電異常の状態をオペレータに知らせるような表示部
に繋がってもよい。さらに図では電圧モニタ制御部１８
に応じて高周波電源１４からの電力供給が制御されるイ
ンターロック回路１９を備える例を示した。インターロ
ック回路１９は電圧モニタ制御部１８に応じて高周波電
源１４からの電力供給を停止し、エッチング処理の中断
をすることができる。インターロック回路１９の設置に
限らず、警報器等の配備でオペレータに知らせるように
してもよい。The voltage monitor control unit 18 may be connected to a display unit for notifying the operator of the abnormal discharge state in the chamber 11. Further, in the figure, the voltage monitor control unit 18
The example in which the interlock circuit 19 in which the power supply from the high frequency power supply 14 is controlled according to the above is provided is shown. The interlock circuit 19 can stop the power supply from the high frequency power supply 14 in response to the voltage monitor control unit 18 to interrupt the etching process. Not only the interlock circuit 19 is installed, but an operator may be notified by disposing an alarm device or the like.
【００２４】放電異常の程度によってはエッチング処理
を中断する必要のないこともある。電圧モニタ制御部１
８はモニタ結果として例えばレベル別に分けた放電異常
の頻度を計数したデータであることも考えられる。この
データに応じてインターロック回路１９の制御を判定し
てもよい。Depending on the degree of abnormal discharge, it may not be necessary to interrupt the etching process. Voltage monitor controller 1
It is also conceivable that 8 is data obtained by counting the frequency of discharge abnormalities classified by level as a monitoring result. The control of the interlock circuit 19 may be determined according to this data.
【００２５】図２は、図１に関し整合回路部１３を中心
とした回路ブロック図である。高周波電力ＲＦを入力
し、このＲＦは、検出器２１を介して接地間の可変コン
デンサ２２による負荷の影響及びインダクタンス回路２
３及び可変コンデンサ２４を介してインピーダンス及び
位相が制御され本体負荷側のチャンバー１１内の電極間
へ印加される。FIG. 2 is a circuit block diagram centering on the matching circuit section 13 with respect to FIG. High frequency power RF is input, and this RF affects the load due to the variable capacitor 22 between the ground and the inductance circuit 2 via the detector 21.
The impedance and the phase are controlled via 3 and the variable capacitor 24, and applied between the electrodes in the chamber 11 on the main body load side.
【００２６】検出器２１は、入力される高周波電力ＲＦ
に関する負荷側のインピーダンスの絶対値と電圧に対す
る電流の位相を検出する。検出器２１のインピーダンス
の絶対値検出信号Ｓ１は演算制御部２５へ供給される。
演算制御部２５はインピーダンス整合を自動的に行うモ
ーター制御信号を生成し、電磁モータ２６により可変コ
ンデンサ２２が操作される。一方、検出器２１の電圧に
対する電流の位相検出信号Ｓ２は演算制御部２７へ供給
される。演算制御部２７は電流の位相を自動的に適合さ
せるモーター制御信号を生成し、電磁モータ２８により
可変コンデンサ２４が操作される。すなわち、可変コン
デンサ２２、２４の調整により負荷側チャンバー１１内
（電極間）のインピーダンス整合及び電流位相調整、い
わゆるマッチングがなされる。The detector 21 receives the input high frequency power RF
The absolute value of the impedance on the load side and the phase of the current with respect to the voltage are detected. The absolute value detection signal S1 of the impedance of the detector 21 is supplied to the arithmetic control unit 25.
The arithmetic control unit 25 generates a motor control signal for automatically performing impedance matching, and the electromagnetic motor 26 operates the variable capacitor 22. On the other hand, the current phase detection signal S2 with respect to the voltage of the detector 21 is supplied to the arithmetic control unit 27. The arithmetic control unit 27 generates a motor control signal that automatically adjusts the phase of the current, and the variable capacitor 24 is operated by the electromagnetic motor 28. That is, by adjusting the variable capacitors 22 and 24, impedance matching in the load side chamber 11 (between the electrodes) and current phase adjustment, that is, matching is performed.
【００２７】図３は、上記整合回路部１３の被制御値で
あるＴＵＮＥ値、ＬＯＡＤ値の特性波形図である。ＴＵ
ＮＥ値は上記検出器２１で得た電圧に対する電流の位相
適合用の可変コンデンサ２４における０〜１００％でみ
た調整値である。ＬＯＡＤ値は上記インピーダンスの絶
対値整合用の可変コンデンサ２２における０〜１００％
でみた調整値である。FIG. 3 is a characteristic waveform diagram of the TUNE value and the LOAD value which are the controlled values of the matching circuit section 13. TU
The NE value is an adjustment value when the variable capacitor 24 for phase matching of the current with respect to the voltage obtained by the detector 21 is viewed from 0 to 100%. The LOAD value is 0 to 100% in the variable capacitor 22 for absolute value matching of the above impedance.
This is the adjusted value.
【００２８】図２、図３を参照して説明する。高周波電
力ＲＦが入力されると、検出器２１から負荷側（チャン
バー１１内）のインピーダンスの絶対値検出信号と電圧
に対する電流の位相検出信号が得られる。チャンバー１
１内に放電異常があれば、上記ＴＵＮＥ値及びＬＯＡＤ
値またはいずれかの値において、規定範囲以外の調整値
が認められる。このような可変コンデンサ２４，２２に
おける電圧変化をリアルタイムでモニタする。Description will be made with reference to FIGS. 2 and 3. When the high frequency power RF is input, the detector 21 obtains a load side (inside the chamber 11) impedance absolute value detection signal and a current phase detection signal with respect to voltage. Chamber 1
If there is a discharge abnormality within 1, the above TUNE value and LOAD
Adjustment values outside the specified range are allowed for the value or any value. The voltage change in such variable capacitors 24 and 22 is monitored in real time.
【００２９】図３において、例えば破線３１，３２の変
移波形は、何らかの原因で放電が立たず、処理不能に陥
った状態である。このような異常状況に伴う電圧変化を
利用して図１に示す電圧モニタ制御部１８は、オペレー
タが確認できるように構成される。あるいはさらに図１
に示したようにインターロック回路１９の制御に利用す
る。In FIG. 3, for example, the transition waveforms of the broken lines 31 and 32 are in a state where the discharge is not generated for some reason and the process cannot be performed. The voltage monitor control unit 18 shown in FIG. 1 is configured to be confirmed by the operator by utilizing the voltage change associated with such an abnormal situation. Alternatively still FIG.
It is used to control the interlock circuit 19 as shown in FIG.
【００３０】上記実施形態の方法及びプラズマ装置によ
れば、チャンバー内で放電異常が起こると、通常グロー
放電を保つようにしている整合回路部１３の被制御値、
インピーダンス絶対値検出信号、位相検出信号、これら
に従って可変コンデンサ２４におけるＴＵＮＥ値、可変
コンデンサ２２におけるＬＯＡＤ値は、所定範囲より大
きく変動する。その変動に対する電圧変化を電圧モニタ
制御部１８が捉える。これにより、処理基板に悪影響を
及ぼす放電異常の検出がリアルタイムで実施できる。ま
た、このような放電異常に応じて高周波電源１４から電
極１２，１５間への電力供給が自動的に停止される。こ
の結果、処理基板である半導体ウェハＷａｆに対し、異
常放電による被害は最小限に抑えられる。According to the method and plasma device of the above-mentioned embodiment, when the discharge abnormality occurs in the chamber, the controlled value of the matching circuit section 13 which normally maintains the glow discharge,
The impedance absolute value detection signal, the phase detection signal, the TUNE value in the variable capacitor 24, and the LOAD value in the variable capacitor 22 according to these signals fluctuate more than a predetermined range. The voltage monitor control unit 18 catches the voltage change due to the fluctuation. As a result, it is possible to detect a discharge abnormality that adversely affects the processing substrate in real time. In addition, the power supply from the high frequency power supply 14 between the electrodes 12 and 15 is automatically stopped in response to such a discharge abnormality. As a result, damage to the semiconductor wafer Waf, which is the processing substrate, due to abnormal discharge is minimized.
【００３１】図４は、本発明の第２実施形態に係る半導
体装置の製造方法及びプラズマ処理装置を説明するもの
であり、プラズマ装置としてドライエッチング装置の概
略構成を示している。前記図１と同様の個所には同一の
符号を付す。図１の構成に比べて、異常放電を検出する
方法が異なり、電圧モニタ制御部１８の代りに電圧モニ
タ制御部４８が設けられている。その他の構成は図１と
同様である。FIG. 4 illustrates a method of manufacturing a semiconductor device and a plasma processing apparatus according to a second embodiment of the present invention, and shows a schematic structure of a dry etching apparatus as a plasma apparatus. The same parts as those in FIG. 1 are designated by the same reference numerals. Compared to the configuration of FIG. 1, the method of detecting abnormal discharge is different, and a voltage monitor control unit 48 is provided instead of the voltage monitor control unit 18. Other configurations are the same as those in FIG.
【００３２】すなわち、チャンバー１１内には、被処理
基板である半導体ウェハＷａｆの載置されるカソード電
極１２が配されている。カソード電極１２には高周波電
源１４からの高周波（ＲＦ）電力が整合回路部１３を介
して印加される。カソード電極１２に対するアノード電
極１５は、接地されたチャンバー１１の上壁であり、反
応ガスの供給口１６も設けられている。チャンバー１１
の側面下部にはガス排出口１６が設けられている。That is, in the chamber 11, the cathode electrode 12 on which the semiconductor wafer Waf, which is the substrate to be processed, is placed is arranged. Radio frequency (RF) power from a radio frequency power supply 14 is applied to the cathode electrode 12 through a matching circuit unit 13. The anode electrode 15 with respect to the cathode electrode 12 is the upper wall of the chamber 11 which is grounded, and the reaction gas supply port 16 is also provided. Chamber 11
A gas outlet 16 is provided on the lower portion of the side surface of the.
【００３３】上記カソード電極１２、アノード電極間に
おいて高周波電源１４からの高周波電力が整合回路部１
３を介して印加される。これにより、通常、グロー放電
領域を保ちつつ供給される反応ガスによるプラズマが発
生され、半導体ウェハＷａｆへのエッチング処理がなさ
れる。The high frequency power from the high frequency power source 14 is applied between the cathode electrode 12 and the anode electrode, and the matching circuit section 1 is provided.
3 is applied. As a result, plasma is generally generated by the reaction gas supplied while maintaining the glow discharge region, and the semiconductor wafer Waf is etched.
【００３４】この実施形態ではプラズマによる処理中に
放電異常が起こった場合、基板の固定に利用されている
静電吸着の電圧変化が大きくなることに着目し、その電
圧変化によって放電異常を検出する。図では、電極１２
の静電吸着から得られる電圧値を検出する電圧モニタ制
御部４８が設けられている。In this embodiment, when a discharge abnormality occurs during plasma processing, attention is paid to the fact that the voltage change of electrostatic attraction used for fixing the substrate increases, and the discharge abnormality is detected by the voltage change. . In the figure, the electrode 12
A voltage monitor control unit 48 for detecting a voltage value obtained from the electrostatic attraction of is provided.
【００３５】図５は、電極１２の静電吸着（ＥＳＣ）電
圧の特性図である。破線５１はチャンバー１１内でアー
ク放電などの異常放電が起こったことを表す。このよう
な異常電圧値が電圧モニタ制御部４８によって検出され
る。FIG. 5 is a characteristic diagram of the electrostatic adsorption (ESC) voltage of the electrode 12. A broken line 51 indicates that abnormal discharge such as arc discharge has occurred in the chamber 11. Such an abnormal voltage value is detected by the voltage monitor control unit 48.
【００３６】電圧モニタ制御部４８は直流電圧アナログ
モニタであり、チャンバー１１内の放電異常の状態をオ
ペレータに知らせるような表示部に繋がってもよい。さ
らに図では電圧モニタ制御部４８に応じて高周波電源１
４からの電力供給が制御されるインターロック回路１９
を備える例を示した。インターロック回路１９は電圧モ
ニタ制御部４８に応じて高周波電源１４からの電力供給
を停止し、エッチング処理の中断をすることができる。
インターロック回路１９の設置に限らず、警報器等の配
備でオペレータに知らせるようにしてもよい。The voltage monitor control unit 48 is a DC voltage analog monitor, and may be connected to a display unit for notifying the operator of the abnormal discharge state in the chamber 11. Further, in the figure, the high frequency power supply 1
4 is controlled by the interlock circuit 19
An example including is shown. The interlock circuit 19 can stop the power supply from the high frequency power supply 14 according to the voltage monitor control unit 48 to interrupt the etching process.
Not only the interlock circuit 19 is installed, but an operator may be notified by disposing an alarm device or the like.
【００３７】上記本発明に係るプラズマ処理装置によれ
ば、チャンバー１１内で通常グロー放電を保つようにし
ている電極間において放電異常が起こると、半導体ウェ
ハＷａｆの固定に利用される静電吸着の電圧変化は大き
くなる（図５参照）。その電圧変化を電圧モニタ制御部
４８が捉える。これにより、処理ウェハに悪影響を及ぼ
す放電異常の検出がリアルタイムで実施できる。これに
より、放電異常に応じて高周波電源から電極への電力供
給が自動的に停止される。この結果、処理ウェハに対
し、異常放電による被害は最小限に抑えられる。According to the above-described plasma processing apparatus of the present invention, when a discharge abnormality occurs between the electrodes which normally maintain the glow discharge in the chamber 11, the electrostatic attraction used for fixing the semiconductor wafer Waf is eliminated. The voltage change becomes large (see FIG. 5). The voltage monitor control unit 48 catches the voltage change. As a result, it is possible to detect the discharge abnormality that adversely affects the processed wafer in real time. As a result, the power supply from the high frequency power supply to the electrodes is automatically stopped according to the discharge abnormality. As a result, damage to the processed wafer due to abnormal discharge is minimized.
【００３８】上記各実施形態の方法及びプラズマ処理装
置によれば、処理基板に悪影響を及ぼす放電異常の検出
がリアルタイムで実施でき、また、放電異常に応じて高
周波電源から電極への電力供給が自動的に停止する制御
も可能である。なお、プラズマ処理装置として、図１、
図４に示すようなドライエッチング装置を示したが、こ
れに限らず、他の構成のドライエッチング装置、または
スパッタ装置等に本発明を用いることができる。According to the method and plasma processing apparatus of each of the above-described embodiments, it is possible to detect the discharge abnormality that adversely affects the processed substrate in real time, and to automatically supply the power from the high frequency power supply to the electrode according to the discharge abnormality. It is also possible to control to stop the movement. As a plasma processing apparatus, as shown in FIG.
Although the dry etching apparatus as shown in FIG. 4 is shown, the present invention is not limited to this, and the present invention can be applied to a dry etching apparatus having another configuration, a sputtering apparatus, or the like.
【００３９】[0039]
【発明の効果】以上説明したように本発明によれば、チ
ャンバー内で放電異常が起こると、通常グロー放電を保
つようにしている電極間の高周波電力に関する整合時、
所定範囲より大きな被制御値が与えられるようになる。
その変動に対する電圧変化を捉えることにより、処理基
板に悪影響を及ぼす放電異常の検出がリアルタイムで実
施できる。あるいは、電極間における基板の固定に利用
される静電吸着の電圧変化を捉えることによりチャンバ
ー内で放電異常の検出がリアルタイムで実施できる。こ
の結果、チャンバー内の放電異常を容易にリアルタイム
でモニタ可能とし、大量の不良生産を防止する半導体装
置の製造方法及びプラズマ処理装置を提供することがで
きる。As described above, according to the present invention, when the discharge abnormality occurs in the chamber, when the high frequency power between the electrodes is normally matched so as to maintain the glow discharge,
A controlled value larger than the predetermined range is given.
By catching the voltage change with respect to the fluctuation, it is possible to detect the discharge abnormality that adversely affects the processing substrate in real time. Alternatively, the discharge abnormality can be detected in real time in the chamber by capturing the voltage change of electrostatic attraction used for fixing the substrate between the electrodes. As a result, a discharge abnormality in the chamber can be easily monitored in real time, and a semiconductor device manufacturing method and a plasma processing apparatus that prevent a large amount of defective production can be provided.
【図１】本発明の第１実施形態に係る半導体装置の製造
方法及びプラズマ処理装置を説明するものであり、プラ
ズマ装置としてドライエッチング装置の概略構成を示し
ている。FIG. 1 is a view for explaining a semiconductor device manufacturing method and a plasma processing apparatus according to a first embodiment of the present invention, showing a schematic configuration of a dry etching apparatus as a plasma apparatus.
【図２】図１に関し整合回路部を中心とした回路ブロッ
ク図である。FIG. 2 is a circuit block diagram centering on a matching circuit portion with respect to FIG.
【図３】図２に示す整合回路部の被制御信号であるＴＵ
ＮＥ値、ＬＯＡＤ値の特性波形図である。FIG. 3 is a TU that is a controlled signal of the matching circuit unit shown in FIG.
It is a characteristic waveform diagram of NE value and LOAD value.
【図４】本発明の第２実施形態に係る半導体装置の製造
方法及びプラズマ処理装置を説明するものであり、プラ
ズマ装置としてドライエッチング装置の概略構成を示し
ている。FIG. 4 is a view for explaining the method for manufacturing a semiconductor device and the plasma processing apparatus according to the second embodiment of the present invention, showing a schematic configuration of a dry etching apparatus as a plasma apparatus.
【図５】図４のドライエッチング装置におけるウェハの
静電吸着（ＥＳＣ）電圧の特性図である。5 is a characteristic diagram of an electrostatic adsorption (ESC) voltage of a wafer in the dry etching apparatus of FIG.
１１…チャンバー１２…カソード電極１３…整合回路部１４…高周波電源１５…アノード電極１６…ガス供給口１７…ガス排出口１８，４８…電圧モニタ制御部１９…インターロック回路２１…検出器２２，２４…可変コンデンサ２３…インダクタンス回路２５，２７…演算制御部２６，２８…電磁モータ３１…ＴＵＮＥ値の変移波形４８…ＬＯＡＤ値の変移波形５１…静電吸着（ＥＳＣ）電圧の異常波形Ｗａｆ…半導体ウェハ11 ... Chamber12 ... Cathode electrode13 ... Matching circuit section14 ... High frequency power supply15 ... Anode electrode16 ... Gas supply port17 ... Gas outlet18, 48 ... Voltage monitor control unit19 ... Interlock circuit21 ... Detector22, 24 ... Variable capacitors23 ... Inductance circuit25, 27 ... Arithmetic control unit26, 28 ... Electromagnetic motor31 ... TUNE value transition waveform48 ... Transition waveform of LOAD value51 ... Abnormal waveform of electrostatic adsorption (ESC) voltageWaf ... Semiconductor wafer
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002085381AJP2003282545A (en) | 2002-03-26 | 2002-03-26 | Semiconductor device manufacturing method and plasma processing apparatus |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002085381AJP2003282545A (en) | 2002-03-26 | 2002-03-26 | Semiconductor device manufacturing method and plasma processing apparatus |
| Publication Number | Publication Date |
|---|---|
| JP2003282545Atrue JP2003282545A (en) | 2003-10-03 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002085381AWithdrawnJP2003282545A (en) | 2002-03-26 | 2002-03-26 | Semiconductor device manufacturing method and plasma processing apparatus |
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