【０００１】[0001]
【発明の属する技術分野】本発明は、シリコン素子を用
いたアナログ高周波スイッチの物理構造に関するもので
ある。The present invention relates to a physical structure of an analog high-frequency switch using a silicon element.
【０００２】[0002]
【従来の技術】アナログ高周波スイッチは、携帯電話を
はじめとする、現代及び次世代の無線通信システムに広
く使われており、そのスイッチ用能動素子としては、性
能、コスト、消費電力、回路面積などの点でＦＥＴを用
いるのが一般的である。アナログ高周波スイッチに要求
される特性としては、低通過損失（オン時）、高アイソ
レーション（オフ時）、高耐圧特性等が挙げられる。2. Description of the Related Art Analog high-frequency switches are widely used in modern and next-generation wireless communication systems such as cellular phones, and active elements for the switches include performance, cost, power consumption, and circuit area. In general, an FET is used in this respect. The characteristics required for the analog high-frequency switch include low pass loss (when on), high isolation (when off), high withstand voltage characteristics, and the like.
【０００３】ＦＥＴを適用したアナログ高周波スイッチ
の構成例として、シリコンｎ型ＭＯＳＦＥＴによるＳＰ
ＳＴ（Single‐Pole Single‐Throw）スイッチの構成を
図４（ａ）に、また、図４（ａ）において信号がＦＥＴ
を通過する様子を模式的に表わした断面図を図４（ｂ）
を示す。As an example of the configuration of an analog high-frequency switch to which an FET is applied, an SP using a silicon n-type MOSFET is used.
FIG. 4A shows the configuration of an ST (Single-Pole Single-Throw) switch, and in FIG.
FIG. 4 (b) is a cross-sectional view schematically showing the state of passing through
Is shown.
【０００４】図４（ａ）において、４１はシリコンｎ型
ＭＯＳＦＥＴ、端子４２，４３はそれぞれソース電極、
ドレイン電極であると同時に、スイッチの入出力端子と
なっている。また、４４はスイッチのオン、オフを制御
するゲート・バイアス端子で、４５はＦＥＴを通過する
信号が端子４４側へ漏洩するのを遮断するための抵抗素
子で、高周波インピーダンスが十分大きくなるように、
通常は数ｋΩ以上の高抵抗を用いる。In FIG. 4 (a), 41 is a silicon n-type MOSFET, terminals 42 and 43 are source electrodes, respectively.
At the same time as being the drain electrode, it is the input / output terminal of the switch. Reference numeral 44 denotes a gate / bias terminal for controlling on / off of the switch, and reference numeral 45 denotes a resistance element for blocking a signal passing through the FET from leaking to the terminal 44 side so that the high-frequency impedance becomes sufficiently large. ,
Usually, a high resistance of several kΩ or more is used.
【０００５】また、図４（ｂ）において、１はｐ型シリ
コンチャネル層、２はｎ＋型シリコンによるソース・コ
ンタクト層、３はｎ＋型シリコンによるドレイン・コン
タクト層、４はゲート電極、５はシリコン酸化膜（Ｓｉ
Ｏ２），６は絶縁膜、７はソース電極、ドレイン電極で
あると同時に金属配線の伝送回路、８はバイア・ホー
ル、４９は通常のシリコン基板である。Further, in FIG. 4 (b), 1 is p-type silicon channel layer, 2 is a source contact layer bythe n + -type silicon, 3 drain contact layer byn + -type silicon, 4 denotes a gate electrode, 5 Is a silicon oxide film (Si
O2) and 6 are insulating films, 7 is a source electrode and a drain electrode, and at the same time, a transmission circuit of metal wiring, 8 is a via hole, and 49 is a normal silicon substrate.
【０００６】動作にあたっては、端子４２から入力した
高周波信号は、金属配線の伝送線路を伝送し、ＭＯＳＦ
ＥＴ４１を通過して、再び金属配線の伝送線路を伝送し
て、端子４３から出力される。ここで、端子４４に印加
する電圧を、ＦＥＴのピンチオフ電圧よりも高くするこ
とにより、図４（ｂ）におけるＦＥＴチャネル層１の基
板への深さ方向が広がり、信号がＦＥＴチャネル層を通
過する抵抗が減少するので、スイッチのオン状態が実現
される。また、端子４４に印加する電圧を、ＦＥＴのピ
ンチオフ電圧よりも低くすることにより、図４（ｂ）に
おけるＦＥＴチャネル層１の基板への深さ方向が狭くな
り、信号がＦＥＴチャネル層を通過する抵抗が増大する
ので、スイッチのオフ状態が実現される。In operation, a high-frequency signal input from a terminal 42 is transmitted through a transmission line of a metal wiring, and
After passing through the ET 41, it is transmitted again through the transmission line of the metal wiring, and is output from the terminal 43. Here, by making the voltage applied to the terminal 44 higher than the pinch-off voltage of the FET, the depth direction of the FET channel layer 1 to the substrate in FIG. 4B is expanded, and the signal passes through the FET channel layer. Since the resistance is reduced, the ON state of the switch is realized. Further, by making the voltage applied to the terminal 44 lower than the pinch-off voltage of the FET, the depth direction of the FET channel layer 1 to the substrate in FIG. 4B becomes narrower, and the signal passes through the FET channel layer. Since the resistance increases, the switch is turned off.
【０００７】ＦＥＴを用いるアナログ高周波スイッチ
は、ハイブリッドＩＣ、すなわち半導体ＦＥＴチップ単
体と、別の基板上で形成された伝送線路等の受動素子の
組み合わせで構成されることもあるが、チップ間を金属
ワイヤ等で結んだ部分の伝送損失が、高周波になるほど
著しく増加する。従って、およそ１ＧＨｚ程度を目安と
して、それよりも高周波領域では、同一の半導体基板上
にＦＥＴと受動素子をプロセス形成する、ＭＭＩＣ（Mo
nolithic Microwave Integrated Circuit）の形で構成
されることが多い。An analog high-frequency switch using an FET may be composed of a hybrid IC, that is, a combination of a semiconductor FET chip alone and a passive element such as a transmission line formed on another substrate. The transmission loss of the portion connected by a wire or the like increases significantly at higher frequencies. Therefore, in the high frequency range, about 1 GHz is used as a guide, and the MMIC (MoIC) in which the FET and the passive element are formed on the same semiconductor substrate in a process.
nolithic Microwave Integrated Circuit).
【０００８】ところで、増幅器のような、利得の向上で
伝送線路の損失を補える能動回路と異なり、スイッチに
おいては，ＦＥＴの低損失化と、伝送線路の低損失化の
両方を達成することが必須である。ところが、通常の回
路プロセス技術では、シリコン基板の抵抗率が低いた
め、信号が基板側に漏洩して低通過損失特性が得られな
い、という問題点があった。（通常のシリコン基板の抵
抗率は１０〜５０Ωｃｍ、半絶縁性ＧａＡｓ基板の抵抗
率は数１００ＭΩｃｍ）By the way, unlike an active circuit, such as an amplifier, which can compensate for a loss in a transmission line by improving a gain, in a switch, it is essential to achieve both a reduction in FET loss and a reduction in transmission line loss. It is. However, in the ordinary circuit process technology, there is a problem that since the resistivity of the silicon substrate is low, a signal leaks to the substrate side and a low pass loss characteristic cannot be obtained. (The resistivity of a normal silicon substrate is 10 to 50 Ωcm, and the resistivity of a semi-insulating GaAs substrate is several 100 MΩcm.)
【０００９】これに対して、トランジスタの下に絶縁体
層を設けて、素子を完全に絶縁するＳＯＩ（Silicon‐O
n-Insulator）構造が提案され、研究が進められてい
る。絶縁体としては、二酸化ケイ素（ＳｉＯ２）が一般
的である。このＳｉＯ２層は、シリコン熱酸化等によっ
て形成されるので、基板もシリコンが適しており、他の
基板材料は、信頼性や既存プロセスとの整合性等から現
実的でない。On the other hand, an insulator layer is provided under the transistor to completely insulate the element.
An n-Insulator) structure has been proposed and research is ongoing. As the insulator, silicon dioxide (SiO2) is generally used. Since the SiO2 layer is formed by thermal oxidation of silicon or the like, silicon is suitable for the substrate, and other substrate materials are not realistic due to reliability, compatibility with existing processes, and the like.
【００１０】ＳＯＩ構造の断面図を、図５に示す。図５
において、１０はシリコン酸化膜であり、１１はシリコ
ンでボディ領域と呼ばれる部分である。なお、その他の
符合１〜９、４９は図４（ｂ）のものと同じである。こ
の構造の特徴は、トランジスタの下に、より比誘電率の
低い絶縁体層が存在することにより、トランジスタの寄
生容量が減少し、トランジスタの性能がさらに高速、低
電力化する、というものである。本構造は、当初はディ
ジタルＬＳＩ回路への適用を想定して考案されたが、ア
ナログ回路においてもトランジスタの高周波特性向上が
期待できることから、増幅器など、シリコンＭＭＩＣへ
の適用の試みが進んでいる。（例えば、原田など、「Ｍ
ＯＳＦＥＴ／ＳＯＩ技術を用いた２ＧＨｚ帯及び４-６
ＧＨｚ帯低雑音アンプ」、電気学会電子回路研究資料EC
T-97-97，p.29-33，1997）FIG. 5 is a sectional view of the SOI structure. FIG.
In the figure, reference numeral 10 denotes a silicon oxide film, and reference numeral 11 denotes a silicon portion called a body region. The other reference numerals 1 to 9 and 49 are the same as those in FIG. The feature of this structure is that the presence of an insulator layer having a lower relative dielectric constant under the transistor reduces the parasitic capacitance of the transistor, and further increases the speed and power of the transistor. . Although this structure was initially devised assuming application to digital LSI circuits, attempts are being made to apply it to silicon MMICs such as amplifiers because analog circuits can be expected to improve the high-frequency characteristics of transistors. (For example, Harada etc., "M
2GHz band and 4-6 using OSFET / SOI technology
GHz-band low-noise amplifier ", IEICE Electronics Circuit Research Material EC
T-97-97, p.29-33, 1997)
【００１１】[0011]
【発明が解決しようとする課題】ところで、ＦＥＴのゲ
ート長やチャネル長は、０.１μｍ〜１μｍの程度で、
絶縁体厚と同程度である。一方、マイクロストリップ線
路やコプレーナ線路に代表される伝送線路の幅は、１０
μｍ〜１０００μｍの程度で絶縁体厚より遥かに大き
く、高周波信号の伝送で生じる実効的な電磁界分布も、
線路幅と同程度以上の広がりを有する。By the way, the gate length and the channel length of the FET are about 0.1 μm to 1 μm.
It is about the same as the insulator thickness. On the other hand, the width of a transmission line represented by a microstrip line or a coplanar line is 10
It is much larger than the insulator thickness in the order of μm to 1000 μm, and the effective electromagnetic field distribution generated by the transmission of the high-frequency signal is also
It has a spread that is at least as large as the line width.
【００１２】コプレーナ線路の電界分布について、この
様子を模式的に表わした断面図を図６に示す。図６にお
いて、６１はコプレーナ線路中心導体、６２は接地導
体、６３はシリコン半導体、６４は絶縁体層、６５はシ
リコン基板、６６は基板側の電気力線、６７はコプレー
ナ線路上の空気側の電気力線である。絶縁体層６４の厚
さは０.１μｍ〜１０μｍ程度で、線路幅に比べて遥か
に薄いから、電気力線６６の殆どは、絶縁体層６４を突
き抜けてシリコン基板６５に広がる。このため、シリコ
ン基板に誘導電流が発生し、線路の伝送損失（誘電体
損）が増加する。シリコンのアナログ高周波スイッチに
おいては、ＳＯＩ構造だけでは不十分である。FIG. 6 is a sectional view schematically showing the state of the electric field distribution of the coplanar line. 6, reference numeral 61 denotes a center conductor of a coplanar line, 62 denotes a ground conductor, 63 denotes a silicon semiconductor, 64 denotes an insulator layer, 65 denotes a silicon substrate, 66 denotes electric lines of force on the substrate side, and 67 denotes an air line on the coplanar line. The lines of electric force. Since the thickness of the insulator layer 64 is about 0.1 μm to 10 μm, which is much smaller than the line width, most of the lines of electric force 66 penetrate the insulator layer 64 and spread to the silicon substrate 65. For this reason, an induced current is generated in the silicon substrate, and the transmission loss (dielectric loss) of the line increases. In a silicon analog high-frequency switch, the SOI structure alone is not sufficient.
【００１３】図４（ａ）と同じ構成で、通常シリコン基
板上ＳＯＩ構造を適用したシリコンＭＭＩＣスイッチの
実験測定結果例を図７に示す。図７（ａ）はスイッチが
オン時の通過損失特性、図７（ｂ）はオフ時のアイソレ
ーション特性である。比較のために、同構成のＧａＡｓ
ＭＭＩＣスイッチの実験測定結果例も記した。図７
（ａ），（ｂ）において、トレース３２,３５はＳＯＩ
構造のスイッチ、７１,７２は通常の構造のスイッチ、
３３,３６はＧａＡｓ ＭＭＩＣスイッチの実測値を示
す。ＳＯＩ構造によって、シリコン基板への信号漏洩が
遮断され、通常の構造のシリコンＭＭＩＣスイッチに比
べて、オン時の通過損失特性が大幅に改善されている
が、線路の誘電体損の存在により、ＧａＡｓ ＭＭＩＣ
スイッチに比べ通過損失特性が劣っている。FIG. 7 shows an example of an experimental measurement result of a silicon MMIC switch having the same configuration as that of FIG. 4A and using a normal SOI structure on a silicon substrate. FIG. 7A shows a pass loss characteristic when the switch is on, and FIG. 7B shows an isolation characteristic when the switch is off. For comparison, GaAs of the same configuration
Examples of experimental measurement results of the MMIC switch are also described. FIG.
In (a) and (b), traces 32 and 35 are SOI
Structure switches, 71 and 72 are normal structure switches,
Reference numerals 33 and 36 denote measured values of the GaAs MMIC switch. The SOI structure blocks signal leakage to the silicon substrate, and greatly improves the pass loss characteristics at the time of ON as compared with the silicon MMIC switch of the normal structure. However, the presence of GaAs due to the dielectric loss of the line causes MMIC
Passing loss characteristics are inferior to switches.
【００１４】本発明の目的は、シリコン高周波スイッチ
のオン状態の通過損失特性、オフ状態のアイソレーショ
ン特性を、同時に改善した高周波スイッチを提供するこ
とにある。通過損失はＦＥＴの通過損失と線路の伝送損
失に分けられるため、この両方を素子構造上の工夫によ
って低減する必要がある。また、低損失スイッチのアイ
ソレーション特性は、能動素子の寄生容量によって決ま
るので、素子構造の工夫によって、同時に寄生容量の低
減をもはかるようにしている。It is an object of the present invention to provide a high-frequency switch in which the on-state passage loss characteristics and the off-state isolation characteristics of a silicon high-frequency switch are simultaneously improved. Since the transmission loss is divided into the transmission loss of the FET and the transmission loss of the line, it is necessary to reduce both of them by contriving the element structure. Further, since the isolation characteristics of the low-loss switch are determined by the parasitic capacitance of the active element, the parasitic capacitance is simultaneously reduced by contriving the element structure.
【００１５】[0015]
【課題を解決するための手段】上記課題を解決するため
に、本発明にあっては、シリコン基板上に形成されたＦ
ＥＴ及び金属配線の信号伝送路を有し、該ＦＥＴのドレ
イン端子とソース端子に信号伝送路が接続され、ドレイ
ン、ソース間のＦＥＴチャネル層を信号が通過する特性
がゲート端子に印加される電圧によってオンまたはオフ
される機能を備えた高周波スイッチにおいて、シリコン
基板とＦＥＴとの間に、シリコンよりも低い誘電率を持
つシリコン酸化膜の絶縁体層をはさんで、該ＦＥＴ及び
信号伝送路が形成されており、かつ該シリコン基板が抵
抗率５００Ωｃｍ以上の高抵抗シリコン基板である構造
を特徴とする。In order to solve the above-mentioned problems, according to the present invention, an F formed on a silicon substrate is provided.
ET and a signal line of metal wiring, a signal transmission line is connected to a drain terminal and a source terminal of the FET, and a voltage applied to a gate terminal is such that a signal passes through an FET channel layer between the drain and the source. In a high-frequency switch having a function of being turned on or off, the FET and the signal transmission path are sandwiched between a silicon substrate and the FET by an insulator layer of a silicon oxide film having a dielectric constant lower than that of silicon. It is characterized in that it is formed and the silicon substrate is a high-resistance silicon substrate having a resistivity of 500 Ωcm or more.
【００１６】[0016]
【発明の実施の形態】本発明のスイッチは、従来のスイ
ッチに比べると、低誘電率シリコン酸化膜層がＦＥＴ及
び伝送線路の下に存在し、なおかつシリコン酸化膜の下
の基板が抵抗率５００Ωｃｍ以上の高抵抗シリコン基板
である点が異なる。「従来の技術」で述べたように、Ｆ
ＥＴスイッチがオン状態の通過損失には、信号がＦＥＴ
チャネルを通過する際の通過損失と、伝送線路を通過す
る際の伝送損失とがある。増幅作用を有する能動回路と
異なり、スイッチにおいては、両者の通過損失を低減し
なければ、実用的な低損失特性は得られない。DESCRIPTION OF THE PREFERRED EMBODIMENTS The switch of the present invention has a low dielectric constant silicon oxide film layer below a FET and a transmission line and a substrate under a silicon oxide film having a resistivity of 500 Ωcm, as compared with a conventional switch. The difference is that it is a high-resistance silicon substrate. As described in the “prior art”, F
When the ET switch is in the ON state, the signal
There is a transmission loss when passing through a channel and a transmission loss when passing through a transmission line. Unlike an active circuit having an amplifying function, a practical low-loss characteristic cannot be obtained in a switch unless the pass loss of both is reduced.
【００１７】本発明によって、ＦＥＴチャネル層の信号
通過特性の低損失化と、伝送線路の低損失化とが同時に
得られるので、はじめて低損失化を実現することが出来
る。また、低誘電率シリコン酸化膜層がＦＥＴの下に存
在することによって、ＦＥＴの寄生容量が低減するの
で、同時に、オフ状態持の高アイソレーション化を実現
することが出来る。According to the present invention, low loss of the signal passing characteristic of the FET channel layer and low loss of the transmission line can be obtained at the same time, so that it is possible to realize low loss for the first time. In addition, since the low dielectric constant silicon oxide film layer is provided under the FET, the parasitic capacitance of the FET is reduced, and at the same time, high isolation with an off state can be realized.
【００１８】「高抵抗」の目安は、通常のシリコン基板
の抵抗率（１０〜５０Ωｃｍ）よりも１桁大きい値であ
る。これにより、基板の損失角ｔａｎδが１桁減少し、
誘電損失が１／１０倍になるので、抵抗率が５００Ωｃ
ｍ程度を境にして、本発明の有効性が現れる。The standard of "high resistance" is a value that is one digit larger than the resistivity (10 to 50 Ωcm) of a normal silicon substrate. This reduces the loss angle tan δ of the substrate by one digit,
Since the dielectric loss becomes 1/10 times, the resistivity is 500Ωc
At about m, the effectiveness of the present invention appears.
【００１９】[0019]
【実施例】以下、本発明の実施例について図面を参照し
て説明する。図１は、高抵抗シリコン基板上のＳＯＩ構
造の上に形成されたシリコンＭＭＩＣスイッチにおけ
る、ＭＯＳＦＥＴ及び金属配線の伝送線路の断面図であ
る。図１において、１はｐ型シリコンチャネル層、２は
ｎ＋型シリコンによるソース・コンタクト層、３はｎ＋
型シリコンによるドレイン・コンタクト層、４はゲート
電極、５はシリコン酸化膜（ＳｉＯ２）、６は絶縁膜、
７はソース電極、ドレイン電極であると同時に金属配線
の伝送線路、８はバイア・ホール、９は高抵抗シリコン
基板、１０はシリコン酸化膜、１１はボディ領域であ
る。ＭＯＳＦＥＴのゲート長及びソース・ドレイン間距
離は、０.１〜１μｍのオーダであるから、まず、スイ
ッチがオン状態の場合、信号がソースコンタクト２から
入ってｐ型シリコンチャネル層１を通過し、ドレイン・
コンタクト層３を出るまでの信号伝送で生じる電界分布
の有効的な拡がり領域は、基板側及び空気側に１μｍ程
度となる。従って、ｐ型シリコンチャネル層１と高抵抗
シリコン基板９との間に挿入された、厚さ数μｍのシリ
コン酸化膜（ＳｉＯ２）１０により、高抵抗シリコン基
板９側への電界分布が遮断され、高抵抗シリコン基板９
に誘起される誘導電流が減少し、ＦＥＴを通過する際の
通過損失は減少する。また、ＳＯＩ構造によって、スイ
ッチがオフ状態の場合にアイソレーション特性を劣化さ
せる要因となる、ＦＥＴ寄生容量Ｃｇｓ，Ｃｇｄ，Ｃｄ
ｓも減少するので、アイソレーション特性も向上する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a MOSFET and a transmission line of metal wiring in a silicon MMIC switch formed on an SOI structure on a high-resistance silicon substrate. In FIG. 1, 1 is a p-type silicon channel layer, 2 is a source contact layer of n+ -type silicon, and 3 is n+
Contact layer 4 of type silicon, 4 is a gate electrode, 5 is a silicon oxide film (SiO2), 6 is an insulating film,
Reference numeral 7 is a source electrode and a drain electrode, and at the same time, a transmission line of a metal wiring, 8 is a via hole, 9 is a high-resistance silicon substrate, 10 is a silicon oxide film, and 11 is a body region. Since the gate length and the distance between the source and the drain of the MOSFET are on the order of 0.1 to 1 μm, first, when the switch is on, a signal enters from the source contact 2 and passes through the p-type silicon channel layer 1. drain·
The effective spread area of the electric field distribution generated by signal transmission until the signal leaves the contact layer 3 is about 1 μm on the substrate side and the air side. Therefore, the electric field distribution toward the high-resistance silicon substrate 9 is cut off by the silicon oxide film (SiO 2) 10 having a thickness of several μm inserted between the p-type silicon channel layer 1 and the high-resistance silicon substrate 9. High resistance silicon substrate 9
The induced current induced in the FET decreases, and the passage loss when passing through the FET decreases. Also, due to the SOI structure, FET parasitic capacitances Cgs, Cgd, and Cd, which cause degradation of isolation characteristics when the switch is in an off state,
Since s is also reduced, the isolation characteristics are also improved.
【００２０】一方、伝送線路においては、高抵抗シリコ
ン基板９の採用によって、伝送損失が減少する。シリコ
ンＭＭＩＣにおけるコプレーナ線路のサイズは、例えば
基板厚６００μｍ、中心導体幅８０μｍ、中心導体−接
地導体間ギャップ５０μｍを選択すると、特性インピー
ダンスが５０Ωの伝送線路が形成される。この場合、周
囲に生じる電界として、線路の上下、数１００μｍ程度
までの媒質の誘電率が支配的となっているので、解析に
おいては、その程度までの媒質を考慮すればよい。今、
伝送損失として、導体損失を考えず、誘電損失のみを考
慮すると、誘電損失（減衰定数）αｄは下記の数式１に
よって与えられる。On the other hand, in the transmission line, the use of the high-resistance silicon substrate 9 reduces transmission loss. When the size of the coplanar line in the silicon MMIC is selected, for example, when the substrate thickness is 600 μm, the center conductor width is 80 μm, and the gap between the center conductor and the ground conductor is 50 μm, a transmission line having a characteristic impedance of 50Ω is formed. In this case, the dielectric constant of the medium up to about several hundred μm above and below the line is dominant as the electric field generated around the medium, so that the medium up to that level may be considered in the analysis. now,
When only the dielectric loss is considered without considering the conductor loss as the transmission loss, the dielectric loss (attenuation constant) αd is given by the following Equation 1.
【数１】(Equation 1)
【００２１】ここで、εｅｆｆは基板（誘電体）の実効
誘電率、σｅｆｆは基板の実効導電率、δは基板の損失
角、（ｔａｎδ）ｅｆｆは実効損失正接である。上記数
式１より、シリコン基板における誘電損失は、基板の導
電率のみで決まり、比例することがわかる。例として、
高抵抗シリコン基板９の抵抗率を１ｋΩｃｍ、通常シリ
コン基板の抵抗率を２０Ωｃｍとすると、１ＧＨｚにお
けるｔａｎδ＝σ／（ωεｒεｏ）はそれぞれ、０.１
５１、７.５５、となる。ただし、εｏは真空の誘電
率、εｒはシリコンの比誘電率で、εｒ＝１１.９であ
る。Here, εeff is the effective dielectric constant of the substrate (dielectric), σeff is the effective conductivity of the substrate, δ is the loss angle of the substrate, and (tanδ) eff is the effective loss tangent. From the above formula 1, it is understood that the dielectric loss in the silicon substrate is determined only by the conductivity of the substrate and is proportional. As an example,
Assuming that the resistivity of the high-resistance silicon substrate 9 is 1 kΩcm and the resistivity of the normal silicon substrate is 20 Ωcm, tanδ = σ / (ωεrεo) at 1 GHz is 0.1.
51, 7.55. Here, εo is the dielectric constant of vacuum, εr is the relative dielectric constant of silicon, and εr = 11.9.
【００２２】これらの値を用いて、市販回路のシミュレ
ータにより予測した、上記サイズのコプレーナ線路の伝
送損失を図２に示す。図２において、トレース２１はＳ
ＯＩ構造と高抵抗シリコン基板上コプレーナ線路の伝導
損失、２２は通常シリコン基板上コプレーナ線路の伝送
損失、２３は半絶縁性ＧａＡｓ基板（抵抗率１００ＭΩ
ｃｍ）上コプレーナ線路の伝送損失を示す。例えば１Ｇ
Ｈｚにおける伝送損失は、高抵抗シリコン基板０.０５
ｄＢ／ｍｍ、通常シリコン基板１.６４ｄＢ／ｍｍ、半
絶縁性ＧａＡｓ基板０.０２ｄＢ／ｍｍとなり、高抵抗
シリコン基板９の採用によって、損失が１.６ｄＢ／ｍ
ｍ改善し、ＧａＡｓ基板にほぼ匹敵する。ＭＭＩＣスイ
ッチの大きさは１〜２ｍｍ角程度で、例えば１ｍｍ角な
らば、ＭＭＩＣ上の電送線路長も同程度であるので、ス
イッチの損失は１.６ｄＢ改善されることになる。FIG. 2 shows the transmission loss of a coplanar line of the above size, which is estimated by using these values by a commercial circuit simulator. In FIG. 2, trace 21 is S
OI structure and conduction loss of a coplanar line on a high-resistance silicon substrate, 22 is a transmission loss of a coplanar line on a silicon substrate, and 23 is a semi-insulating GaAs substrate (resistivity 100 MΩ).
cm) shows the transmission loss of the upper coplanar line. For example, 1G
The transmission loss in Hz is 0.05% for the high-resistance silicon substrate 0.05.
dB / mm, a normal silicon substrate is 1.64 dB / mm, and a semi-insulating GaAs substrate is 0.02 dB / mm, and the adoption of the high-resistance silicon substrate 9 results in a loss of 1.6 dB / m.
m, which is almost equal to that of a GaAs substrate. The size of the MMIC switch is about 1 to 2 mm square. For example, if the size of the MMIC switch is 1 mm square, the length of the transmission line on the MMIC is about the same, so that the loss of the switch is improved by 1.6 dB.
【００２３】図４（ａ）と同じ構成で、高抵抗シリコン
基板上ＳＯＩ構造を適用したＭＭＩＣスイッチの実験測
定結果例を図３に示す。図３（ａ）はスイッチ・オン時
の通過損失特性、図３（ｂ）はスイッチ・オフ時のアイ
ソレーション特性である。図３において、トレース３
１，３４は高抵抗シリコン基板上ＳＯＩ構造のスイッ
チ、３２，３５は通常シリコン基板上ＳＯＩ構造のスイ
ッチ、３３，３６はＧａＡｓＭＭＩＣスイッチの実測値
を示す。高抵抗シリコン基板上ＳＯＩ構造によって、オ
ン時の通過損失特性が、ＧａＡｓＭＭＩＣスイッチにほ
ぼ匹敵するまでに向上している。と同時に、ＳＯＩ構造
によるＦＥＴの低寄生容量化により、オフ時のアイソレ
ーション特性がＧａＡｓＭＭＩＣスイッチよりも向上し
ている。FIG. 3 shows an example of an experimental measurement result of an MMIC switch having the same configuration as that of FIG. 4A and employing the SOI structure on a high-resistance silicon substrate. FIG. 3A shows a pass loss characteristic when the switch is turned on, and FIG. 3B shows an isolation characteristic when the switch is turned off. In FIG. 3, trace 3
Reference numerals 1 and 34 denote switches of an SOI structure on a high resistance silicon substrate, 32 and 35 denote switches of an ordinary SOI structure on a silicon substrate, and 33 and 36 denote measured values of GaAs MMIC switches. Due to the SOI structure on the high-resistance silicon substrate, the passage loss characteristic at the time of ON is improved to be almost equal to that of the GaAs MMIC switch. At the same time, due to the lower parasitic capacitance of the FET having the SOI structure, the isolation characteristics at the time of OFF are improved as compared with the GaAs MMIC switch.
【００２４】[0024]
【発明の効果】以上説明したように、本発明の高周波ス
イッチは、シリコン基板とＦＥＴとの間に、シリコンよ
りも低い誘電率を持つシリコン酸化膜の絶縁体層を挟ん
で、該ＦＥＴ及び信号伝送路が形成されており、かつ該
シリコン基板が抵抗率５００Ωｃｍ以上の高抵抗シリコ
ン基板であるような構造とすることにより、ＦＥＴチャ
ネル層の信号通過特性の低損失化と、伝送線路の低損失
化が同時に得られ、また、ＦＥＴの寄生容量が低減する
ので、スイッチがオン状態時の低損失化と、オフ状態時
の高アイソレーション化を、はじめて同時に実現するこ
とが出来るという、優れた効果を奏する。As described above, the high-frequency switch of the present invention has a structure in which an insulator layer of a silicon oxide film having a dielectric constant lower than that of silicon is interposed between a silicon substrate and an FET. By adopting a structure in which a transmission path is formed and the silicon substrate is a high-resistance silicon substrate having a resistivity of 500 Ωcm or more, a reduction in signal transmission characteristics of the FET channel layer and a reduction in transmission line loss are achieved. And the parasitic capacitance of the FET is reduced, so that it is possible to achieve low loss when the switch is on and high isolation when the switch is off for the first time. To play.
【図１】 本発明の一実施例の断面図を示す。FIG. 1 shows a cross-sectional view of one embodiment of the present invention.
【図２】 市販回路シミュレータによるコプレーナ線路
の伝送損失の計算値を示す。FIG. 2 shows calculated values of transmission loss of a coplanar line by a commercially available circuit simulator.
【図３】 本発明実施例の実験測定結果であり、（ａ）
図はスイッチ・オン時の通過損失特性、（ｂ）図はスイ
ッチ・オフ時のアイソレーション特性を示す。FIG. 3 shows experimental measurement results of an example of the present invention, and (a)
The figure shows the pass loss characteristic when the switch is turned on, and the figure (b) shows the isolation characteristic when the switch is turned off.
【図４】 従来技術による高周波スイッチの例で、
（ａ）図はシリコンｎ型ＭＯＳＦＥＴによるＳＰＳＴ
（Single-Pole Single Throw）スイッチ構成例、（ｂ）
図はＦＥＴスイッチの断面図を示す。FIG. 4 is an example of a high-frequency switch according to the related art;
(A) Figure shows SPST using silicon n-type MOSFET
(Single-Pole Single Throw) switch configuration example, (b)
The figure shows a sectional view of the FET switch.
【図５】 従来技術によるＳＯＩ構造の断面図を示す。FIG. 5 shows a cross-sectional view of a SOI structure according to the prior art.
【図６】 コプレーナ線路の電界分布を示す。FIG. 6 shows an electric field distribution of a coplanar line.
【図７】 従来技術例の実験測定結果であり、（ａ）図
はスイッチ・オン時の通過損失特性、（ｂ）図はスイッ
チ・オフ時のアイソレーション特性を示す。7A and 7B are experimental measurement results of a conventional technique example, in which FIG. 7A shows a pass loss characteristic when the switch is turned on, and FIG. 7B shows an isolation characteristic when the switch is turned off.
１ ｐ型シリコンチャネル層 ２ ｎ＋型シリコンによるソースコンタクト層 ３ ｎ＋型シリコンによるドレイン・コンタクト層 ４ ゲート電極 ５ ゲートのシリコン酸化膜（ＳｉＯ２） ６ 絶縁膜 ７ ソース電極、ドレイン電極、金属配線の伝送線路 ８ バイア・ホール ９ 高抵抗シリコン基板 １０ シリコン酸化膜 １１ ボディ領域 ２１ 本発明実施例の線路の伝送損失を表すトレース ２２ 通常シリコン基板上コプレーナ線路の伝送損失
を表すトレース ２３ 半絶縁性ＧａＡｓ基板上コプレーナ線路の伝送
損失を表すトレース ３１ 本発明実施例のスイッチの通過損失特性を表わ
すトレース ３２ 通常シリコン基板上ＳＯＩ構造のスイッチの通
過損失特性を表すトレース ３３ ＧａＡｓＭＭＩＣスイッチの 通過損失特性を表
すトレース ３４ 本発明実施例のスイッチのアイソレーション特
性を表すトレース ３５ 通常シリコン基板上ＳＯＩ構造のスイッチのア
イソレーション特性を表すトレース ３６ ＧａＡｓＭＭＩＣスイッチのアイソレーション
特性を表すトレース ４１ ｎ型シリコンＭＯＳＦＥＴ ４２ ソース電極、かつスイッチの入出力端子 ４３ ドレイン電極、かつスイッチの入出力端子 ４４ ゲート・バイアス端子 ４５ 高周波遮断用の抵抗素子 ４９ 従来のシリコン基板 ６１ コプレーナ線路中心導体 ６２ コプレーナ線路接地導体 ６３ シリコン半導体層 ６４ 絶縁体層 ６５ シリコン基板 ６６ コプレーナ線路下の基板側の電気力線 ６７ コプレーナ線路上の空気側の電気力線 ７１ 通常構造のシリコンＭＭＩＣスイッチの通過損
失特性を表すトレース ７２ 通常構造のシリコンＭＭＩＣスイッチのアイソ
レーション特性を表すトレース1 p-type silicon channel layer 2 n+ -type silicon source contact layer 3 n+ -type silicon by the drain contact layer 4 gate electrode 5 gate silicon oxide film by (SiO2) 6 insulating film 7 a source electrode, a drain electrode, the metal wiring Transmission line 8 Via hole 9 High-resistance silicon substrate 10 Silicon oxide film 11 Body region 21 Trace representing transmission loss of line according to the present invention 22 Trace representing transmission loss of coplanar line on normal silicon substrate 23 Semi-insulating GaAs substrate Trace representing the transmission loss of the upper coplanar line 31 Trace representing the transmission loss characteristic of the switch of the embodiment of the present invention 32 Trace representing the transmission loss characteristic of the switch having the SOI structure on the silicon substrate 33 Trace representing the transmission loss characteristic of the GaAs MMIC switch 34 The present invention Trace representing the isolation characteristic of the switch of the embodiment 35 Trace representing the isolation characteristic of the switch having the SOI structure on the normal silicon substrate 36 Trace representing the isolation characteristic of the GaAs MMIC switch 41 n-type silicon MOSFET 42 Source electrode and switch input Output terminal 43 Drain electrode and switch input / output terminal 44 Gate / bias terminal 45 High frequency blocking resistor element 49 Conventional silicon substrate 61 Coplanar line center conductor 62 Coplanar line ground conductor 63 Silicon semiconductor layer 64 Insulator layer 65 Silicon substrate 66 Electric field lines on the substrate side below the coplanar line 67 Electric lines of air on the coplanar line 71 Trace showing the passage loss characteristic of the silicon MMIC switch of the normal structure 72 Silicon MM of the normal structure Trace representing the isolation characteristics of the C switch
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9740699AJP2000294786A (en) | 1999-04-05 | 1999-04-05 | High frequency switch |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9740699AJP2000294786A (en) | 1999-04-05 | 1999-04-05 | High frequency switch |
| Publication Number | Publication Date |
|---|---|
| JP2000294786Atrue JP2000294786A (en) | 2000-10-20 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9740699APendingJP2000294786A (en) | 1999-04-05 | 1999-04-05 | High frequency switch |
| Country | Link |
|---|---|
| JP (1) | JP2000294786A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6605829B2 (en) | 2001-07-03 | 2003-08-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US6836172B2 (en) | 2002-05-30 | 2004-12-28 | Nec Compound Semiconductor Devices, Ltd. | Semiconductor switch apparatus including isolated MOS transistors |
| JP2007123823A (en)* | 2005-09-28 | 2007-05-17 | Denso Corp | Semiconductor device and manufacturing method thereof |
| JP2010153786A (en)* | 2008-12-23 | 2010-07-08 | Internatl Business Mach Corp <Ibm> | Semiconductor structure, method for forming semiconductor structure, and method for operating semiconductor device (soi radio frequency switch with enhanced signal fidelity and electric isolation) |
| JP2012217109A (en)* | 2011-04-01 | 2012-11-08 | Mitsubishi Electric Corp | High frequency circuit board |
| US8405147B2 (en) | 2005-07-11 | 2013-03-26 | Peregrine Semiconductor Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
| US8487688B2 (en) | 2010-11-29 | 2013-07-16 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US8536636B2 (en) | 2007-04-26 | 2013-09-17 | Peregrine Semiconductor Corporation | Tuning capacitance to enhance FET stack voltage withstand |
| US8559907B2 (en) | 2004-06-23 | 2013-10-15 | Peregrine Semiconductor Corporation | Integrated RF front end with stacked transistor switch |
| US8583111B2 (en) | 2001-10-10 | 2013-11-12 | Peregrine Semiconductor Corporation | Switch circuit and method of switching radio frequency signals |
| US8604864B2 (en) | 2008-02-28 | 2013-12-10 | Peregrine Semiconductor Corporation | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals |
| US8655287B2 (en) | 2012-02-17 | 2014-02-18 | Kabushiki Kaisha Toshiba | Switch control circuit, semiconductor device, and radio communication device |
| US8723260B1 (en) | 2009-03-12 | 2014-05-13 | Rf Micro Devices, Inc. | Semiconductor radio frequency switch with body contact |
| US8742502B2 (en) | 2005-07-11 | 2014-06-03 | Peregrine Semiconductor Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
| US8923784B2 (en) | 2011-08-31 | 2014-12-30 | Kabushiki Kaisha Toshiba | Semiconductor switch and wireless device |
| US8954902B2 (en) | 2005-07-11 | 2015-02-10 | Peregrine Semiconductor Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
| US9209800B2 (en) | 2013-02-01 | 2015-12-08 | Kabushiki Kaisha Toshiba | High freuency semiconductor switch and wireless device |
| US9406695B2 (en) | 2013-11-20 | 2016-08-02 | Peregrine Semiconductor Corporation | Circuit and method for improving ESD tolerance and switching speed |
| US9419565B2 (en) | 2013-03-14 | 2016-08-16 | Peregrine Semiconductor Corporation | Hot carrier injection compensation |
| US9590674B2 (en) | 2012-12-14 | 2017-03-07 | Peregrine Semiconductor Corporation | Semiconductor devices with switchable ground-body connection |
| US9595945B2 (en) | 2015-03-13 | 2017-03-14 | Kabushiki Kaisha Toshiba | Switch control circuit and switch circuit |
| US9614520B2 (en) | 2015-03-13 | 2017-04-04 | Kabushiki Kaisha Toshiba | Semiconductor switch |
| US9819367B2 (en) | 2016-03-01 | 2017-11-14 | Kabushiki Kaisha Toshiba | Communication circuit |
| US9831857B2 (en) | 2015-03-11 | 2017-11-28 | Peregrine Semiconductor Corporation | Power splitter with programmable output phase shift |
| KR20180016954A (en)* | 2016-08-08 | 2018-02-20 | 인피니언 테크놀로지스 아게 | Apparatus for converting an electrical power of an electromagnetic wave into a dc electrical voltage signal |
| US9948281B2 (en) | 2016-09-02 | 2018-04-17 | Peregrine Semiconductor Corporation | Positive logic digitally tunable capacitor |
| US10122356B2 (en) | 2016-09-20 | 2018-11-06 | Kabushiki Kaisha Toshiba | Semiconductor switch |
| US10153803B2 (en) | 2016-09-20 | 2018-12-11 | Kabushiki Kaisha Toshiba | Receiving circuit, wireless communication module, and wireless communication device |
| US10236872B1 (en) | 2018-03-28 | 2019-03-19 | Psemi Corporation | AC coupling modules for bias ladders |
| US10505530B2 (en) | 2018-03-28 | 2019-12-10 | Psemi Corporation | Positive logic switch with selectable DC blocking circuit |
| US10790390B2 (en) | 2005-07-11 | 2020-09-29 | Psemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
| US10804892B2 (en) | 2005-07-11 | 2020-10-13 | Psemi Corporation | Circuit and method for controlling charge injection in radio frequency switches |
| US10886911B2 (en) | 2018-03-28 | 2021-01-05 | Psemi Corporation | Stacked FET switch bias ladders |
| USRE48965E1 (en) | 2005-07-11 | 2022-03-08 | Psemi Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
| US11476849B2 (en) | 2020-01-06 | 2022-10-18 | Psemi Corporation | High power positive logic switch |
| WO2023163102A1 (en)* | 2022-02-28 | 2023-08-31 | 株式会社村田製作所 | Semiconductor apparatus and semiconductor module |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6605829B2 (en) | 2001-07-03 | 2003-08-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US10622993B2 (en) | 2001-10-10 | 2020-04-14 | Psemi Corporation | Switch circuit and method of switching radio frequency signals |
| US10797694B2 (en) | 2001-10-10 | 2020-10-06 | Psemi Corporation | Switch circuit and method of switching radio frequency signals |
| US9225378B2 (en) | 2001-10-10 | 2015-12-29 | Peregrine Semiconductor Corpopration | Switch circuit and method of switching radio frequency signals |
| US10812068B2 (en) | 2001-10-10 | 2020-10-20 | Psemi Corporation | Switch circuit and method of switching radio frequency signals |
| US8583111B2 (en) | 2001-10-10 | 2013-11-12 | Peregrine Semiconductor Corporation | Switch circuit and method of switching radio frequency signals |
| US6836172B2 (en) | 2002-05-30 | 2004-12-28 | Nec Compound Semiconductor Devices, Ltd. | Semiconductor switch apparatus including isolated MOS transistors |
| US8649754B2 (en) | 2004-06-23 | 2014-02-11 | Peregrine Semiconductor Corporation | Integrated RF front end with stacked transistor switch |
| US9369087B2 (en) | 2004-06-23 | 2016-06-14 | Peregrine Semiconductor Corporation | Integrated RF front end with stacked transistor switch |
| US9680416B2 (en) | 2004-06-23 | 2017-06-13 | Peregrine Semiconductor Corporation | Integrated RF front end with stacked transistor switch |
| US8559907B2 (en) | 2004-06-23 | 2013-10-15 | Peregrine Semiconductor Corporation | Integrated RF front end with stacked transistor switch |
| US10818796B2 (en) | 2005-07-11 | 2020-10-27 | Psemi Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
| USRE48965E1 (en) | 2005-07-11 | 2022-03-08 | Psemi Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
| US9608619B2 (en) | 2005-07-11 | 2017-03-28 | Peregrine Semiconductor Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
| US10622990B2 (en) | 2005-07-11 | 2020-04-14 | Psemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
| US8742502B2 (en) | 2005-07-11 | 2014-06-03 | Peregrine Semiconductor Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
| US10680600B2 (en) | 2005-07-11 | 2020-06-09 | Psemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
| US10790390B2 (en) | 2005-07-11 | 2020-09-29 | Psemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
| US10797172B2 (en) | 2005-07-11 | 2020-10-06 | Psemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
| US8954902B2 (en) | 2005-07-11 | 2015-02-10 | Peregrine Semiconductor Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
| USRE48944E1 (en) | 2005-07-11 | 2022-02-22 | Psemi Corporation | Method and apparatus for use in improving linearity of MOSFETS using an accumulated charge sink |
| US10797691B1 (en) | 2005-07-11 | 2020-10-06 | Psemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
| US9087899B2 (en) | 2005-07-11 | 2015-07-21 | Peregrine Semiconductor Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
| US8405147B2 (en) | 2005-07-11 | 2013-03-26 | Peregrine Semiconductor Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
| US9130564B2 (en) | 2005-07-11 | 2015-09-08 | Peregrine Semiconductor Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
| US10804892B2 (en) | 2005-07-11 | 2020-10-13 | Psemi Corporation | Circuit and method for controlling charge injection in radio frequency switches |
| JP2007123823A (en)* | 2005-09-28 | 2007-05-17 | Denso Corp | Semiconductor device and manufacturing method thereof |
| US10951210B2 (en) | 2007-04-26 | 2021-03-16 | Psemi Corporation | Tuning capacitance to enhance FET stack voltage withstand |
| US9177737B2 (en) | 2007-04-26 | 2015-11-03 | Peregrine Semiconductor Corporation | Tuning capacitance to enhance FET stack voltage withstand |
| US8536636B2 (en) | 2007-04-26 | 2013-09-17 | Peregrine Semiconductor Corporation | Tuning capacitance to enhance FET stack voltage withstand |
| US9024700B2 (en) | 2008-02-28 | 2015-05-05 | Peregrine Semiconductor Corporation | Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device |
| US9197194B2 (en) | 2008-02-28 | 2015-11-24 | Peregrine Semiconductor Corporation | Methods and apparatuses for use in tuning reactance in a circuit device |
| US9293262B2 (en) | 2008-02-28 | 2016-03-22 | Peregrine Semiconductor Corporation | Digitally tuned capacitors with tapered and reconfigurable quality factors |
| US8604864B2 (en) | 2008-02-28 | 2013-12-10 | Peregrine Semiconductor Corporation | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals |
| US8669804B2 (en) | 2008-02-28 | 2014-03-11 | Peregrine Semiconductor Corporation | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals |
| US9106227B2 (en) | 2008-02-28 | 2015-08-11 | Peregrine Semiconductor Corporation | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals |
| JP2010153786A (en)* | 2008-12-23 | 2010-07-08 | Internatl Business Mach Corp <Ibm> | Semiconductor structure, method for forming semiconductor structure, and method for operating semiconductor device (soi radio frequency switch with enhanced signal fidelity and electric isolation) |
| US8916467B2 (en) | 2008-12-23 | 2014-12-23 | International Business Machines Corporation | SOI radio frequency switch with enhanced signal fidelity and electrical isolation |
| US8723260B1 (en) | 2009-03-12 | 2014-05-13 | Rf Micro Devices, Inc. | Semiconductor radio frequency switch with body contact |
| US8866530B2 (en) | 2010-11-29 | 2014-10-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
| USRE46490E1 (en) | 2010-11-29 | 2017-07-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US8487688B2 (en) | 2010-11-29 | 2013-07-16 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2012217109A (en)* | 2011-04-01 | 2012-11-08 | Mitsubishi Electric Corp | High frequency circuit board |
| US8923784B2 (en) | 2011-08-31 | 2014-12-30 | Kabushiki Kaisha Toshiba | Semiconductor switch and wireless device |
| US9525415B2 (en) | 2011-08-31 | 2016-12-20 | Kabushiki Kaisha Toshiba | Radio frequency semiconductor switch |
| US9020448B2 (en) | 2012-02-17 | 2015-04-28 | Kabushiki Kaisha Toshiba | Switch control circuit, semiconductor device, and radio communication device |
| US8655287B2 (en) | 2012-02-17 | 2014-02-18 | Kabushiki Kaisha Toshiba | Switch control circuit, semiconductor device, and radio communication device |
| US9590674B2 (en) | 2012-12-14 | 2017-03-07 | Peregrine Semiconductor Corporation | Semiconductor devices with switchable ground-body connection |
| US9209800B2 (en) | 2013-02-01 | 2015-12-08 | Kabushiki Kaisha Toshiba | High freuency semiconductor switch and wireless device |
| US9461643B2 (en) | 2013-02-01 | 2016-10-04 | Kabushiki Kaisha Toshiba | High freuency semiconductor switch and wireless device |
| US9419565B2 (en) | 2013-03-14 | 2016-08-16 | Peregrine Semiconductor Corporation | Hot carrier injection compensation |
| US9406695B2 (en) | 2013-11-20 | 2016-08-02 | Peregrine Semiconductor Corporation | Circuit and method for improving ESD tolerance and switching speed |
| US9831857B2 (en) | 2015-03-11 | 2017-11-28 | Peregrine Semiconductor Corporation | Power splitter with programmable output phase shift |
| US9614520B2 (en) | 2015-03-13 | 2017-04-04 | Kabushiki Kaisha Toshiba | Semiconductor switch |
| US9595945B2 (en) | 2015-03-13 | 2017-03-14 | Kabushiki Kaisha Toshiba | Switch control circuit and switch circuit |
| US9819367B2 (en) | 2016-03-01 | 2017-11-14 | Kabushiki Kaisha Toshiba | Communication circuit |
| US10630196B2 (en) | 2016-08-08 | 2020-04-21 | Infineon Technologies Ag | Apparatus for converting an electrical power of electromagnetic wave into a DC electrical voltage signal |
| KR101968412B1 (en)* | 2016-08-08 | 2019-04-11 | 인피니언 테크놀로지스 아게 | Apparatus for converting an electrical power of an electromagnetic wave into a dc electrical voltage signal |
| KR20180016954A (en)* | 2016-08-08 | 2018-02-20 | 인피니언 테크놀로지스 아게 | Apparatus for converting an electrical power of an electromagnetic wave into a dc electrical voltage signal |
| US9948281B2 (en) | 2016-09-02 | 2018-04-17 | Peregrine Semiconductor Corporation | Positive logic digitally tunable capacitor |
| US10153803B2 (en) | 2016-09-20 | 2018-12-11 | Kabushiki Kaisha Toshiba | Receiving circuit, wireless communication module, and wireless communication device |
| US10122356B2 (en) | 2016-09-20 | 2018-11-06 | Kabushiki Kaisha Toshiba | Semiconductor switch |
| US10236872B1 (en) | 2018-03-28 | 2019-03-19 | Psemi Corporation | AC coupling modules for bias ladders |
| US10886911B2 (en) | 2018-03-28 | 2021-01-05 | Psemi Corporation | Stacked FET switch bias ladders |
| US11018662B2 (en) | 2018-03-28 | 2021-05-25 | Psemi Corporation | AC coupling modules for bias ladders |
| US10862473B2 (en) | 2018-03-28 | 2020-12-08 | Psemi Corporation | Positive logic switch with selectable DC blocking circuit |
| US10505530B2 (en) | 2018-03-28 | 2019-12-10 | Psemi Corporation | Positive logic switch with selectable DC blocking circuit |
| US11870431B2 (en) | 2018-03-28 | 2024-01-09 | Psemi Corporation | AC coupling modules for bias ladders |
| US11476849B2 (en) | 2020-01-06 | 2022-10-18 | Psemi Corporation | High power positive logic switch |
| US12081211B2 (en) | 2020-01-06 | 2024-09-03 | Psemi Corporation | High power positive logic switch |
| WO2023163102A1 (en)* | 2022-02-28 | 2023-08-31 | 株式会社村田製作所 | Semiconductor apparatus and semiconductor module |
| Publication | Publication Date | Title |
|---|---|---|
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