【０００１】[0001]
【発明の属する技術分野】本発明は、ノート型パーソナ
ル・コンピュータ、ＩＣ（ｉｎｔｅｇｒａｔｅｄｃｉｒ
ｃｕｉｔ）カード、ＭＣＭ（ｍｕｌｔｉ ｃｈｉｐ ｍ
ｏｄｕｌｅ）に用いるインターポーザー（応力緩和層）
などの電子機器に用いて好適なフレキシブル多層回路基
板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a notebook personal computer, an integrated circuit (IC),
unit) card, MCM (multi chip m)
interposer (stress relaxation layer)
The present invention relates to a method for manufacturing a flexible multilayer circuit board suitable for use in electronic devices such as electronic equipment.
【０００２】[0002]
【従来の技術】現在、前記したような電子機器に於いて
は、電子デバイスを高密度に実装することが可能で、且
つ、信号の高速伝播が可能な多層回路基板で特にフレキ
シブルなものが要求されている。2. Description of the Related Art At present, in the above-mentioned electronic equipment, a multilayer circuit board capable of mounting electronic devices at high density and transmitting signals at high speed is required. Have been.
【０００３】従来のフレキシブル回路基板は、配線ピッ
チが１００〔μｍ〕以上のものが多用されていて、多層
化した際の位置合わせ精度はそれほど要求されない為、
ベース・フィルムと熱可塑性フィルムとを組み合わせた
フィルム上に導体配線を形成したものを多層化するフィ
ルム・ラミネート方式のものが主流である。[0003] Conventionally, flexible circuit boards having a wiring pitch of 100 [μm] or more are frequently used, and the positioning accuracy when a multilayer structure is formed is not so required.
The mainstream is a film lamination type in which a conductor film is formed on a film in which a base film and a thermoplastic film are combined to form a multilayer.
【０００４】然しながら、近年、信号を高速伝播させる
為に微細化することが要求され、配線ピッチが２０〔μ
ｍ〕〜１０〔μｍ〕、更には、それ以下の配線ピッチを
もつフレキシブル多層回路基板を形成する技術が必要に
なってきた。However, in recent years, miniaturization is required in order to propagate signals at high speed, and the wiring pitch is 20 μm.
m] to 10 [μm], and a technique for forming a flexible multilayer circuit board having a wiring pitch smaller than that is required.
【０００５】一般に、配線ピッチが２０〔μｍ〕を下回
るような要求に対しては、フィルム・ラミネート法では
熱膨張が原因となって正確なアライメントができず、多
層化することは困難である。In general, when the wiring pitch is less than 20 μm, accurate alignment cannot be performed by the film lamination method due to thermal expansion, and it is difficult to form a multilayer structure.
【０００６】また、位置合わせ精度を向上させる手段と
しては、固定したＡｌからなる金属基板上に積層するビ
ルドアップ法などを適用して目的とする多層回路基板を
形成し、その後、金属基板をエッチングしてフレキシブ
ル多層回路基板を実現する方法も知られているが、金属
基板をエッチングする為、無駄が多くなって高コストと
なる。As means for improving the alignment accuracy, a multilayer circuit board is formed by applying a build-up method or the like on a fixed Al metal substrate, and then the metal substrate is etched. Although a method of realizing a flexible multi-layer circuit board is also known, since the metal substrate is etched, waste is increased and the cost is increased.
【０００７】[0007]
【発明が解決しようとする課題】本発明では、配線ピッ
チが微細なフレキシブル多層回路基板を低コストで製造
することができるようにする。SUMMARY OF THE INVENTION According to the present invention, a flexible multilayer circuit board having a fine wiring pitch can be manufactured at low cost.
【０００８】[0008]
【課題を解決するための手段】本発明では、固定基板上
に薄膜多層配線を積層形成し、その薄膜多層配線を固定
基板から簡単且つ容易に剥離してフレキシブル多層回路
基板を得る技術を開示するもので、固定基板から薄膜多
層配線を剥離する際、レーザ光、或いは、水蒸気などを
用いることで固定基板と薄膜多層配線との密着力を低下
させることが基本になっている。SUMMARY OF THE INVENTION The present invention discloses a technique for obtaining a flexible multilayer circuit board by laminating thin-film multilayer wiring on a fixed substrate and peeling the thin-film multilayer wiring from the fixed substrate easily and easily. Basically, when peeling off the thin-film multilayer wiring from the fixed substrate, the adhesive force between the fixed substrate and the thin-film multilayer wiring is basically reduced by using laser light or water vapor.
【０００９】即ち、薄膜多層配線の位置合わせ精度を良
好にする為、固定基板上に薄膜多層配線を形成する点で
は従来の技術と類似するところはあるが、その固定基板
に透光性基板、例えばガラス基板を用い、ガラス基板上
に薄膜多層配線を形成してから、ガラス基板裏面からレ
ーザを照射する、いわゆる、レーザ・アブレーションを
利用し、ガラス基板に密着している薄膜多層配線の樹脂
界面を改質、即ち、炭化してガラス基板と薄膜多層配線
とを容易且つ簡単に剥離してフレキシブル多層回路基板
を得る。That is, although the thin film multilayer wiring is formed on a fixed substrate in order to improve the alignment accuracy of the thin film multilayer wiring, there is a point similar to the conventional technique, but the fixed substrate has a light transmitting substrate, For example, using a glass substrate, a thin film multilayer wiring is formed on a glass substrate, and then a laser is irradiated from the back of the glass substrate. Is modified, that is, carbonized to easily and easily peel off the glass substrate and the thin film multilayer wiring to obtain a flexible multilayer circuit board.
【００１０】或いは、基板上に薄膜多層配線を形成して
から、加圧した水蒸気中に放置することで、薄膜多層配
線に於ける樹脂の密着性に寄与している水酸基を水と反
応させて樹脂と基板との密着力を劣化させ、基板と薄膜
多層配線とを容易且つ簡単に剥離してフレキシブル多層
回路基板を得る。尚、この場合に用いる基板は透光性材
料である必要はない。Alternatively, a thin film multilayer wiring is formed on a substrate, and then left in pressurized steam to cause a hydroxyl group contributing to the adhesion of the resin in the thin film multilayer wiring to react with water. The adhesion between the resin and the substrate is degraded, and the substrate and the thin film multilayer wiring are easily and easily peeled off to obtain a flexible multilayer circuit substrate. Note that the substrate used in this case does not need to be a translucent material.
【００１１】前記何れの場合に於いても、基板は薄膜多
層配線を剥離した後、再利用することができるから、従
来の技術に於けるように金属基板をエッチングする方法
と比較するとコストは大幅に低下する。In any of the above cases, the substrate can be reused after the thin-film multilayer wiring is peeled off, so that the cost is significantly higher than the conventional method of etching a metal substrate. To decline.
【００１２】前記したところから、本発明に依るフレキ
シブル多層回路基板の製造方法に於いては、（１）透光
性基板（例えばガラス基板１）上に最下層を樹脂膜（例
えばポリイミドからなる第一層目絶縁膜２）とする薄膜
多層配線を形成する工程と、次いで、透光性基板裏面か
ら光（例えばＫｒＦレーザ光や赤外線レーザ光）を照射
して薄膜多層配線の剥離を容易化する工程とが含まれて
なることを特徴とするか、又は、As described above, in the method for manufacturing a flexible multilayer circuit board according to the present invention, (1) a lowermost layer is formed on a light-transmitting substrate (eg, glass substrate 1) by a resin film (eg, polyimide). A step of forming a thin-film multilayer wiring as a first-layer insulating film 2), and then irradiating light (for example, KrF laser light or infrared laser light) from the back surface of the light-transmitting substrate to facilitate peeling of the thin-film multilayer wiring. Or a process is included, or
【００１３】（２）前記（１）に於いて、透光性基板裏
面からの光の照射がレーザ光の照射に依るアブレーショ
ンであることを特徴とするか、又は、(2) In the above (1), the irradiation of light from the back surface of the light-transmitting substrate is an ablation by irradiation of a laser beam, or
【００１４】（３）基板（例えばガラス基板１）上に最
下層を樹脂膜（例えばポリイミドからなる第一層目絶縁
膜２）とする薄膜多層配線を形成する工程と、次いで、
薄膜多層配線が形成された基板を加圧水蒸気（例えば１
２１〔℃〕、２．１〔気圧〕、１００〔％〕水蒸気）中
に放置（例えば２４〔時間〕）して薄膜多層配線の剥離
を容易化する工程とが含まれてなることを特徴とする
か、又は、(3) A step of forming a thin film multilayer wiring having a lowermost layer as a resin film (for example, a first insulating film 2 made of polyimide) on a substrate (for example, a glass substrate 1);
Pressurized steam (for example, 1
A step of leaving the substrate in 21 [° C.], 2.1 [atm], 100 [%] water vapor (for example, 24 [hours]) to facilitate the peeling of the thin-film multilayer wiring. Do or
【００１５】（４）前記（１）乃至（３）の何れか１に
於いて、基板（例えばガラス基板１）と薄膜多層配線と
を剥離した後、該薄膜多層配線に於ける最下層の樹脂膜
（例えばポリイミドからなる第一層目絶縁膜２）を除去
して配線（例えば第一層目配線３）を表出させることを
特徴とする。(4) In any one of the above (1) to (3), after the substrate (for example, the glass substrate 1) and the thin-film multilayer wiring are peeled off, the lowermost resin in the thin-film multilayer wiring is formed. The film (for example, the first-layer insulating film 2 made of polyimide) is removed to expose the wiring (for example, the first-layer wiring 3).
【００１６】前記手段を採ることに依り、配線ピッチが
例えば１０〔μｍ〕以下であるような微細配線を高精度
で形成できるのは勿論のこと、固定基板上に積層形成さ
れた薄膜多層回路基板は容易に剥離することができ、ま
た、剥離後の固定基板は再利用することが可能であり、
全体として、従来の技術で製造したフレキシブル多層回
路基板に比較すると大幅にコストが削減される。By employing the above-mentioned means, it is possible to form a fine wiring having a wiring pitch of, for example, 10 [μm] or less with high precision, and also to provide a thin-film multilayer circuit board laminated on a fixed substrate. Can be easily peeled off, and the fixed substrate after peeling can be reused,
Overall, the cost is significantly reduced as compared to a flexible multilayer circuit board manufactured by the prior art.
【００１７】[0017]
【発明の実施の形態】図１乃至図３は本発明に於ける実
施の形態１を説明する為の工程要所に於けるフレキシブ
ル多層回路基板を表す要部切断側面図であり、以下、こ
れ等の図を参照しつつ説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 3 are cutaway side views of a main part of a flexible multi-layer circuit board at a key point in a process for explaining a first embodiment of the present invention. The description will be made with reference to the drawings such as FIG.
【００１８】図１（Ａ）参照 １−（１） スピン・コート法を適用することに依り、ガラス基板１
上に厚さが２０〔μｍ〕のポリイミドからなる第一層目
絶縁膜２を形成してからキュアを行う。1 (A) 1- (1) A glass substrate 1 is formed by applying a spin coating method.
After forming a first insulating film 2 of polyimide having a thickness of 20 [μm] thereon, curing is performed.
【００１９】図１（Ｂ）参照 １−（２） 真空蒸着法、リソグラフィ技術に於けるレジスト・プロ
セス、エッチャントを過硫酸アンモニウムとするウエッ
ト・エッチング法を適用することに依り、第一層目絶縁
膜２上に配線ピッチが１０〔μｍ〕（配線幅５〔μｍ〕
及び配線間隔５〔μｍ〕）、厚さが５〔μｍ〕である複
数条の第一層目Ｃｕ配線３及びパッド３Ａを形成する。
尚、本発明に依った場合、配線ピッチを１０〔μｍ〕以
下にすることは容易である。1- (2) First-layer insulating film by applying a vacuum deposition method, a resist process in lithography, and a wet etching method using ammonium persulfate as an etchant. 2 and the wiring pitch is 10 [μm] (wiring width 5 [μm]
A plurality of first-layer Cu wirings 3 and pads 3A having a wiring interval of 5 μm and a thickness of 5 μm are formed.
According to the present invention, it is easy to reduce the wiring pitch to 10 [μm] or less.
【００２０】１−（３） リソグラフィ技術に於けるレジスト・プロセスを適用す
ることに依り、パッド３Ａに対応する開口をもつレジス
ト膜を形成する。1- (3) A resist film having an opening corresponding to the pad 3A is formed by applying a resist process in the lithography technique.
【００２１】１−（４） 鍍金法を適用することに依り、開口内も含めた全面に導
電プラグを形成する為のＣｕ膜を形成する1- (4) A Cu film for forming a conductive plug is formed on the entire surface including the opening by applying the plating method.
【００２２】１−（５） レジスト剥離液中に浸漬してレジスト膜を剥離除去する
リフト・オフ法を適用することに依り、開口内のＣｕ膜
を残し、他を除去することで導電プラグ３Ｂを形成す
る。1- (5) A conductive plug 3B is formed by leaving the Cu film in the opening and removing the others by applying the lift-off method of peeling and removing the resist film by dipping in a resist removing solution. To form
【００２３】１−（６） 工程１−（１）と同様にして、第一層目Ｃｕ配線３、パ
ッド３Ａ、導電プラグ３Ｂを含む全面に厚さが例えば２
０〔μｍ〕のポリイミドからなる第二層目絶縁膜４を形
成してからキュアを行う。1- (6) In the same manner as in the step 1- (1), the entire surface including the first layer Cu wiring 3, the pads 3A and the conductive plugs 3B has a thickness of, for example, 2
After forming a second insulating film 4 made of polyimide having a thickness of 0 [μm], curing is performed.
【００２４】１−（７） 第二層目絶縁膜４を形成すると、導電プラグ３Ｂの箇所
が特に盛り上がるように高くなってしまうので、ＣＭＰ
（ｃｈｅｍｉｃａｌ ｍｅｃｈａｎｉｃａｌ ｐｏｌｉ
ｓｈｉｎｇ）法を適用することに依り、第二層目絶縁膜
４の研磨を行って平坦化し、導電プラグ３Ｂの頂面を表
出させる。1- (7) When the second-layer insulating film 4 is formed, the portion of the conductive plug 3B becomes high so as to be particularly raised.
(Chemical mechanical poli
By applying the shing method, the second insulating film 4 is polished and flattened to expose the top surface of the conductive plug 3B.
【００２５】１−（８） 真空蒸着法、リソグラフィ技術に於けるレジスト・プロ
セス、エッチャントを過硫酸アンモニウムとするウエッ
ト・エッチング法を適用することに依り、第二層目絶縁
膜４上に配線ピッチや厚さが第一層目Ｃｕ配線と同じで
ある第二層目Ｃｕ配線及びパッド５Ａを形成する。尚、
図では、第二層目Ｃｕ配線自体は省略して、関連するパ
ッド５Ａのみを表してある。1- (8) By applying a vacuum deposition method, a resist process in a lithography technique, and a wet etching method in which an etchant is ammonium persulfate, the wiring pitch or the like is formed on the second insulating film 4. A second-layer Cu wiring and a pad 5A having the same thickness as the first-layer Cu wiring are formed. still,
In the drawing, the second layer Cu wiring itself is omitted, and only the related pad 5A is shown.
【００２６】この第二層目Ｃｕ配線に関連するパッド５
Ａは工程１−（５）で形成した導電プラグ３Ｂとコンタ
クトするので、第一層目Ｃｕ配線３に於けるパッド３Ａ
とコンタクトすることになる。Pad 5 related to the second layer Cu wiring
A contacts the conductive plug 3B formed in the step 1- (5), so that the pad 3A in the first-layer Cu wiring 3
Will contact you.
【００２７】１−（９） 工程１−（６）と同様にして、第二層目Ｃｕ配線及びパ
ッド５Ａを含む全面に厚さが例えば２０〔μｍ〕のポリ
イミドからなる第三層目絶縁膜６を形成してからキュア
を行う。1- (9) Third-layer insulating film made of polyimide having a thickness of, for example, 20 [μm] over the entire surface including the second-layer Cu wiring and pad 5A in the same manner as in step 1- (6). After forming 6, curing is performed.
【００２８】１−（１０） ＣＭＰ法を適用することに依り、第二層目Ｃｕ配線及び
パッド５Ａが表出されるまで第三層目絶縁膜６の研磨を
行う。1- (10) The third insulating film 6 is polished by applying the CMP method until the second Cu wiring and the pad 5A are exposed.
【００２９】図２（Ａ）参照 ２−（１） ガラス基板１の裏面からＫｒＦ（エキシマ）レーザ光を
照射して、ガラス基板１に密着しているポリイミドから
なる第一層目絶縁膜２に於ける裏面のアブレーションを
行う。2 (A) 2- (1) A KrF (excimer) laser beam is irradiated from the back surface of the glass substrate 1 to the first insulating film 2 made of polyimide which is in close contact with the glass substrate 1. Ablation of the back surface at
【００３０】図２（Ｂ）及び図３参照 ２−（２） レーザ・アブレーションを行った場合、第一層目絶縁膜
２の裏面は極薄く炭化されたような状態になるので、自
然発生的に第一層目絶縁膜２から第三層目絶縁膜６まで
の薄膜多層配線はガラス基板１から簡単且つ容易に剥離
され、フレキシブル多層回路基板（図３参照）を得るこ
とができた。2 (B) and FIG. 3 2- (2) When laser ablation is performed, the back surface of the first insulating film 2 becomes extremely thin and carbonized. First, the thin-film multilayer wiring from the first insulating film 2 to the third insulating film 6 was easily and easily peeled off from the glass substrate 1 to obtain a flexible multilayer circuit board (see FIG. 3).
【００３１】ガラス基板１から剥離した薄膜多層配線の
最下層である第一層目絶縁膜２を除去して第一層目Ｃｕ
配線３を表出させても良く、その場合、第一層目絶縁膜
２は例えば０．１〔μｍ〕程度と薄くすることが望まし
く、そして、その第一層目絶縁膜２の除去には、レーザ
・アブレーションを利用することができる。The first insulating film 2 which is the lowermost layer of the thin film multilayer wiring peeled off from the glass substrate 1 is removed to remove the first Cu
The wiring 3 may be exposed. In this case, the first insulating film 2 is desirably thin, for example, about 0.1 [μm]. , Laser ablation can be used.
【００３２】尚、薄膜多層配線を剥離したガラス基板１
は、洗浄などの処理をして再び使用できることは云うま
でもない。The glass substrate 1 from which the thin-film multilayer wiring has been peeled off
Needless to say, the can be reused after being subjected to washing and the like.
【００３３】図４は本発明に於ける実施の形態２を説明
する為の工程要所に於けるフレキシブル多層回路基板を
表す要部切断側面図であり、以下、これ等の図を参照し
つつ説明する。尚、図１乃至図３に於いて用いた記号と
同記号は同部分を表すか或いは同じ意味を持つものとす
る。FIG. 4 is a sectional side view showing a main part of a flexible multilayer circuit board in a process step for explaining a second embodiment of the present invention. explain. 1 to 3 represent the same parts or have the same meaning.
【００３４】ガラス基板１上に薄膜多層配線を形成する
までは、図１について説明した実施の形態１に於ける工
程と全く同じであるから省略し、その次のステップから
説明する。The steps up to the formation of the thin-film multilayer wiring on the glass substrate 1 are exactly the same as those in the first embodiment described with reference to FIG. 1, and therefore will be omitted, and the following steps will be described.
【００３５】薄膜多層配線が形成されたガラス基板１を
気密室１１内にセットしてから、温度を１２１〔℃〕、
気圧を２．１〔気圧〕、１００〔％〕の水蒸気中に２４
〔時間〕放置する。After setting the glass substrate 1 on which the thin-film multilayer wiring is formed in the hermetic chamber 11, the temperature is set to 121 ° C.
Atmospheric pressure is 2.1 [atmospheric pressure], 24% in 100% water vapor.
[Time] Leave.
【００３６】この処理に依って、薄膜多層配線とガラス
基板１との密着性に寄与しているポリイミドからなる第
一層目絶縁膜２に於ける水酸基は水と反応して密着力が
劣化する。By this treatment, the hydroxyl groups in the first insulating film 2 made of polyimide, which contribute to the adhesion between the thin-film multilayer wiring and the glass substrate 1, react with water to deteriorate the adhesion. .
【００３７】そこで、第一層目絶縁膜２から第三層目絶
縁膜６までの薄膜多層配線はガラス基板１から自然発生
的に簡単且つ容易に剥離でき、フレキシブル多層回路基
板が得られる。Therefore, the thin-film multilayer wiring from the first insulating film 2 to the third insulating film 6 can be spontaneously and easily peeled off from the glass substrate 1 naturally, and a flexible multilayer circuit board can be obtained.
【００３８】この場合もガラス基板１から剥離した薄膜
多層配線の最下層である第一層目絶縁膜２を除去して第
一層目Ｃｕ配線３を表出させても良く、その第一層目絶
縁膜２の除去には、レーザ・アブレーションを利用する
ことができる。Also in this case, the first-layer insulating film 2 which is the lowermost layer of the thin-film multilayer wiring separated from the glass substrate 1 may be removed to expose the first-layer Cu wiring 3. Laser ablation can be used to remove the eye insulating film 2.
【００３９】尚、ここで用いたガラス基板１は勿論のこ
と、他の材料からなる基板を用いた場合でも洗浄などの
処理をして再び使用できることは云うまでもない。It is needless to say that not only the glass substrate 1 used here but also a substrate made of another material can be used after being subjected to processing such as cleaning.
【００４０】本発明では、前記説明した実施の形態に限
られることなく、他に多くの改変を実現することがで
き、例えば、実施の形態２に於いては、薄膜多層配線と
ガラス基板１との剥離を容易化する為にはエキシマ・レ
ーザ光は用いないから、薄膜多層配線を形成する為の基
板は、ガラス基板である必要はないから、不透光性基板
例えば金属基板など適宜の材料を用いることができる。
また、そのような場合であっても、基板を再利用できる
ことは云うまでもない。In the present invention, many other modifications can be realized without being limited to the above-described embodiment. For example, in the second embodiment, the thin film multilayer wiring and the glass substrate 1 Since excimer laser light is not used to facilitate the peeling of the substrate, the substrate for forming the thin-film multilayer wiring does not need to be a glass substrate. Can be used.
Further, even in such a case, it is needless to say that the substrate can be reused.
【００４１】また、前記実施の形態では、絶縁膜の材料
にポリイミドを用いたが、これはオレフィンに代替する
ことができる。In the above embodiment, polyimide is used as the material of the insulating film, but this can be replaced with olefin.
【００４２】また、前記実施の形態では、レーザ・アブ
レーションを行うレーザとしてエキシマ・レーザを用い
たが、これは赤外線レーザに代替することができる。In the above embodiment, an excimer laser is used as a laser for performing laser ablation, but this can be replaced with an infrared laser.
【００４３】また、薄膜多層配線の最下層の樹脂膜、即
ち、第一層目絶縁膜２として可溶性のポリイミドを用
い、第一層目配線３を表出させる為に第一層目絶縁膜２
を除去するようにしても良く、その場合、ポリイミドの
溶剤としてはＮ−メチル−ピロリジン（ＮＭＰ）を用い
ることができる。Further, a soluble polyimide is used as the lowermost resin film of the thin-film multilayer wiring, that is, the first insulating film 2, and the first insulating film 2 is formed to expose the first wiring 3.
May be removed, and in that case, N-methyl-pyrrolidine (NMP) can be used as a solvent for the polyimide.
【００４４】本発明に依るフレキシブル多層回路基板
は、そのまま、電子機器に用いることは勿論、デバイス
とＭＣＭ基板接続用のインターポーザーとして用いてＭ
ＣＭを構成したり、セラミック回路基板と接合してＭＣ
Ｍを構成したり、ガラス・エポキシ基板などに接合して
プリント回路基板を構成したり、最上層を熱可塑性の樹
脂で構成し、他の回路基板と熱圧着して接合することも
可能である。The flexible multi-layer circuit board according to the present invention can be used as it is for electronic equipment, and can be used as an interposer for connecting a device to an MCM board.
Construct a CM or join a ceramic circuit board
It is also possible to form a printed circuit board by forming M, or to form a printed circuit board by bonding to a glass / epoxy board, or to form a thermoplastic resin for the uppermost layer and bond it to another circuit board by thermocompression bonding. .
【００４５】[0045]
【発明の効果】本発明は、フレキシブル多層回路基板の
製造方法に於いて、基板上に最下層を樹脂膜とする薄膜
多層配線を形成し、基板裏面から光を照射したり、或い
は、加圧水蒸気中に放置するなどして、薄膜多層配線の
剥離を容易化する。According to the present invention, there is provided a method for manufacturing a flexible multi-layer circuit board, comprising forming a thin-film multi-layer wiring having a resin film as a lowermost layer on the board, irradiating light from the back of the board, or applying pressurized steam. It is easy to peel off the thin film multilayer wiring by leaving it inside.
【００４６】前記構成を採ることに依り、配線ピッチが
例えば１０〔μｍ〕以下であるような微細配線を高精度
で形成できるのは勿論のこと、固定基板上に積層形成さ
れた薄膜多層回路基板は容易に剥離することができ、ま
た、剥離後の固定基板は再利用することが可能であり、
全体として、従来の技術で製造したフレキシブル多層回
路基板に比較すると大幅にコストが削減される。By adopting the above configuration, it is possible to form a fine wiring having a wiring pitch of, for example, 10 [μm] or less with high precision, and also a thin film multilayer circuit board laminated on a fixed substrate. Can be easily peeled off, and the fixed substrate after peeling can be reused,
Overall, the cost is significantly reduced as compared to a flexible multilayer circuit board manufactured by the prior art.
【図１】本発明に於ける実施の形態１を説明する為の工
程要所に於けるフレキシブル多層回路基板を表す要部切
断側面図である。FIG. 1 is a fragmentary sectional side view showing a flexible multi-layer circuit board at a key point in a process for explaining a first embodiment of the present invention.
【図２】本発明に於ける実施の形態１を説明する為の工
程要所に於けるフレキシブル多層回路基板を表す要部切
断側面図である。FIG. 2 is a fragmentary sectional side view showing a flexible multilayer circuit board at a key point of a process for describing Embodiment 1 of the present invention.
【図３】本発明に於ける実施の形態１を説明する為の工
程要所に於けるフレキシブル多層回路基板を表す要部切
断側面図である。FIG. 3 is a fragmentary side view showing a flexible multi-layer circuit board at a key point in the process for describing Embodiment 1 of the present invention.
【図４】本発明に於ける実施の形態２を説明する為の工
程要所に於けるフレキシブル多層回路基板を表す要部切
断側面図である。FIG. 4 is a fragmentary side view showing a flexible multi-layer circuit board at an important point in a process for explaining a second embodiment of the present invention.
１ ガラス基板 ２ ポリイミドからなる第一層目絶縁膜 ３ 第一層目Ｃｕ配線 ３Ａ パッド ４ ポリイミドからなる第二層目絶縁膜 ５Ａ 第二層目Ｃｕ配線に於けるパッド ６ 第三層目絶縁膜 Reference Signs List 1 glass substrate 2 first-layer insulating film made of polyimide 3 first-layer Cu wiring 3A pad 4 second-layer insulating film made of polyimide 5A pad in second-layer Cu wiring 6 third-layer insulating film
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP37247998AJP2000196243A (en) | 1998-12-28 | 1998-12-28 | Method for manufacturing flexible multilayer circuit board |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP37247998AJP2000196243A (en) | 1998-12-28 | 1998-12-28 | Method for manufacturing flexible multilayer circuit board |
| Publication Number | Publication Date |
|---|---|
| JP2000196243Atrue JP2000196243A (en) | 2000-07-14 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP37247998APendingJP2000196243A (en) | 1998-12-28 | 1998-12-28 | Method for manufacturing flexible multilayer circuit board |
| Country | Link |
|---|---|
| JP (1) | JP2000196243A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002033464A (en)* | 2000-07-17 | 2002-01-31 | Semiconductor Energy Lab Co Ltd | Method for fabricating semiconductor device |
| JP2002031818A (en)* | 2000-07-17 | 2002-01-31 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| JP2002232021A (en)* | 2001-02-01 | 2002-08-16 | Sony Corp | Method for transferring element and panel |
| WO2003009657A1 (en)* | 2001-07-19 | 2003-01-30 | Toray Industries, Inc. | Circuit board, circuit board-use member and production method therefor and method of laminating fexible film |
| WO2004053967A1 (en)* | 2002-12-10 | 2004-06-24 | Fujitsu Limited | Semiconductor apparatus, wiring board forming method, and substrate treatment apparatus |
| JP2005243999A (en)* | 2004-02-27 | 2005-09-08 | Ngk Spark Plug Co Ltd | Method for manufacturing wiring board |
| JP2006228919A (en)* | 2005-02-17 | 2006-08-31 | Nec Corp | Wiring board, semiconductor device, and their manufacturing method |
| CN100359995C (en)* | 2004-07-15 | 2008-01-02 | 松下电器产业株式会社 | Circuit board connection structure and manufacturing method thereof |
| US7485962B2 (en) | 2002-12-10 | 2009-02-03 | Fujitsu Limited | Semiconductor device, wiring substrate forming method, and substrate processing apparatus |
| US7985663B2 (en) | 2008-05-27 | 2011-07-26 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device |
| US8039756B2 (en) | 2005-10-12 | 2011-10-18 | Nec Corporation | Multilayered wiring board, semiconductor device in which multilayered wiring board is used, and method for manufacturing the same |
| CN105408115A (en)* | 2013-07-24 | 2016-03-16 | 尤尼吉可株式会社 | Laminate, method for processing same, and method for manufacturing flexible device |
| WO2020158082A1 (en)* | 2019-01-31 | 2020-08-06 | 株式会社ジャパンディスプレイ | Deposition mask and method for manufacturing deposition mask |
| US12048207B2 (en) | 2013-12-02 | 2024-07-23 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method for manufacturing the same |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002031818A (en)* | 2000-07-17 | 2002-01-31 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| JP2002033464A (en)* | 2000-07-17 | 2002-01-31 | Semiconductor Energy Lab Co Ltd | Method for fabricating semiconductor device |
| JP2002232021A (en)* | 2001-02-01 | 2002-08-16 | Sony Corp | Method for transferring element and panel |
| US7105221B2 (en) | 2001-07-19 | 2006-09-12 | Toray Industries, Inc. | Circuit board, laminated member for circuit board, and method for making laminated member for circuit board |
| WO2003009657A1 (en)* | 2001-07-19 | 2003-01-30 | Toray Industries, Inc. | Circuit board, circuit board-use member and production method therefor and method of laminating fexible film |
| CN100579332C (en)* | 2001-07-19 | 2010-01-06 | 东丽株式会社 | Circuit board, member for circuit board, manufacturing method thereof, and lamination method of flexible film |
| US7534361B2 (en) | 2001-07-19 | 2009-05-19 | Toray Industries, Inc. | Methods for making laminated member for circuit board, making circuit board and laminating flexible film |
| JPWO2004053967A1 (en)* | 2002-12-10 | 2006-04-13 | 富士通株式会社 | Semiconductor device, method for forming wiring board, and substrate processing apparatus |
| US7485962B2 (en) | 2002-12-10 | 2009-02-03 | Fujitsu Limited | Semiconductor device, wiring substrate forming method, and substrate processing apparatus |
| WO2004053967A1 (en)* | 2002-12-10 | 2004-06-24 | Fujitsu Limited | Semiconductor apparatus, wiring board forming method, and substrate treatment apparatus |
| US7648907B2 (en) | 2002-12-10 | 2010-01-19 | Fujitsu Limited | Semiconductor device, wiring substrate forming method, and substrate processing apparatus |
| US7704856B2 (en) | 2002-12-10 | 2010-04-27 | Fujitsu Limited | Semiconductor device, wiring substrate forming method, and substrate processing apparatus |
| JP2005243999A (en)* | 2004-02-27 | 2005-09-08 | Ngk Spark Plug Co Ltd | Method for manufacturing wiring board |
| CN100359995C (en)* | 2004-07-15 | 2008-01-02 | 松下电器产业株式会社 | Circuit board connection structure and manufacturing method thereof |
| JP2006228919A (en)* | 2005-02-17 | 2006-08-31 | Nec Corp | Wiring board, semiconductor device, and their manufacturing method |
| US8039756B2 (en) | 2005-10-12 | 2011-10-18 | Nec Corporation | Multilayered wiring board, semiconductor device in which multilayered wiring board is used, and method for manufacturing the same |
| US7985663B2 (en) | 2008-05-27 | 2011-07-26 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device |
| CN105408115A (en)* | 2013-07-24 | 2016-03-16 | 尤尼吉可株式会社 | Laminate, method for processing same, and method for manufacturing flexible device |
| CN105408115B (en)* | 2013-07-24 | 2018-08-28 | 尤尼吉可株式会社 | Laminated body, its processing method, and method of manufacturing a flexible device |
| TWI654090B (en) | 2013-07-24 | 2019-03-21 | 尤尼吉可股份有限公司 | Laminated product, treatment method thereof and production method of flexible device |
| US12048207B2 (en) | 2013-12-02 | 2024-07-23 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method for manufacturing the same |
| WO2020158082A1 (en)* | 2019-01-31 | 2020-08-06 | 株式会社ジャパンディスプレイ | Deposition mask and method for manufacturing deposition mask |
| JP2020122208A (en)* | 2019-01-31 | 2020-08-13 | 株式会社ジャパンディスプレイ | Vapor deposition mask and manufacturing method of vapor deposition mask |
| JP7332301B2 (en) | 2019-01-31 | 2023-08-23 | 株式会社ジャパンディスプレイ | Evaporation mask and method for manufacturing the evaporation mask |
| Publication | Publication Date | Title |
|---|---|---|
| US6569712B2 (en) | Structure of a ball-grid array package substrate and processes for producing thereof | |
| KR101215246B1 (en) | Method of Manufacturing Multilayer Wiring Substrate, and Multilayer Wiring Substrate | |
| KR100896810B1 (en) | Printed Circuit Board and Manufacturing Method | |
| TWI492688B (en) | Method of manufacturing multilayer wiring substrate | |
| KR101109230B1 (en) | Printed circuit board and manufacturing method thereof | |
| JP2000196243A (en) | Method for manufacturing flexible multilayer circuit board | |
| JP2003031925A (en) | Structure with flush circuit feature and manufacturing method therefor | |
| JPH0923065A (en) | Thin-film multi-layer wiring board and manufacturing method thereof | |
| KR101109344B1 (en) | Printed circuit board and manufacturing method thereof | |
| JP2004193497A (en) | Chip-size package and manufacturing method thereof | |
| JP2002523789A (en) | Manufacturing method of metal microstructure and application of the method in manufacturing sensor device for detecting fingerprints | |
| US5109601A (en) | Method of marking a thin film package | |
| US6524889B2 (en) | Method of transcribing a wiring pattern from an original substrate to a substrate with closely matched thermal expansion coefficients between both substrates for dimensional control of the transcribed pattern | |
| JP2002033584A (en) | Manufacturing method for multilayer printed-wiring board | |
| JP2004119730A (en) | Method of manufacturing circuit device | |
| EP1801870A1 (en) | Partial adherent temporary substrate and method of using the same | |
| US4965700A (en) | Thin film package for mixed bonding of chips | |
| JP2002009202A (en) | Method of manufacturing low dielectric constant resin insulating layer, method of manufacturing circuit board using the insulating layer, and method of manufacturing thin film multilayer circuit film using the insulating layer | |
| KR100547349B1 (en) | Semiconductor Package Substrate and Manufacturing Method Thereof | |
| KR101039772B1 (en) | Ultra-thin metal printed circuit board manufacturing method | |
| KR100704911B1 (en) | Electronic printed circuit board and its manufacturing method | |
| JP6112857B2 (en) | Wiring board and manufacturing method thereof | |
| JP3941463B2 (en) | Manufacturing method of multilayer printed wiring board | |
| US11764344B2 (en) | Package structure and manufacturing method thereof | |
| KR100934862B1 (en) | Method and apparatus for allowing electrical and mechanical connection of electrical devices with surfaces with contact pads |
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination | Effective date:20050921 Free format text:JAPANESE INTERMEDIATE CODE: A621 | |
| A131 | Notification of reasons for refusal | Free format text:JAPANESE INTERMEDIATE CODE: A131 Effective date:20080610 | |
| A02 | Decision of refusal | Effective date:20081028 Free format text:JAPANESE INTERMEDIATE CODE: A02 |