This patent application claims the benefit of U.S. provisional application No.62/136,224 and U.S. provisional application No.62/196,277, both entitled "method and APPARATUS FOR SPECTRAL EFFICIENT DATA TRANSMISSION IN SATELLITE SYSTEMS", filed on days 3 and 20 of 2015 and 23 of 2015, both of which have been assigned to the assignee of the present application and are hereby expressly incorporated herein in their entirety by reference.
Detailed Description
A communication satellite system provides for spectrally efficient data transmission via a gateway to a plurality of user terminals by way of a satellite. The gateway transmits a plurality of blocks in a single time slot, each block intended for one of the user terminals, wherein each block is coded and modulated according to a scheme that may be different for each intended user terminal. If a block is lost or received in error, the block may be encoded and modulated according to another scheme to provide stronger error control correction when the block is retransmitted, and wherein the modulation has a lower order than in the first transmission of the block.
In the following description and the related drawings, aspects of the present invention are disclosed. Alternative systems may be devised without departing from the scope of the invention. Additionally, some well-known elements have not been described in detail or have been omitted so as not to obscure the relevant details of the description.
The terminology used herein is for the purpose of describing particular aspects of the invention only and is not intended to be limiting of those aspects. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it will be understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Further, some aspects of the invention are described herein in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by some entities such as specific circuits (e.g., Application Specific Integrated Circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, the sequence of acts described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functions described herein. Thus, the various aspects of the invention may be embodied in a number of different forms, all of which are contemplated to be within the scope of the invention. Further, for each aspect of the invention described herein, the corresponding form of any of these aspects may be described herein as: for example, a "logic unit" configured to perform the described actions.
Fig. 1 illustrates an example of a satellite communication system 100, wherein the satellite communication system 100 includes a plurality of satellites (although only one satellite 300 is shown for clarity of illustration) in non-geosynchronous orbits (e.g., Low Earth Orbit (LEO)), a gateway 200 in communication with the satellite 300, a plurality of User Terminals (UTs) 400 and 401 in communication with the satellite 300, and a plurality of User Equipment (UEs) 500 and 501 in communication with the UTs 400 and 401, respectively. Each UE500 or 501 may be a user device such as a mobile device, phone, smartphone, tablet, laptop, computer, wearable device, smart watch, audiovisual device, or any device that includes the capability to communicate with a UT. Additionally, UE500 and/or UE 501 may be devices (e.g., access points, small cells, etc.) for communicating with one or more end user devices. In the example shown in fig. 1, UT400 and UE500 communicate with each other via a bidirectional access link (having a forward access link and a return access link), and similarly UT 401 and UE 501 communicate with each other via another bidirectional access link. In another implementation, one or more additional UEs (not shown) may be configured to receive only and thus communicate with the UT using only the forward access link. In another implementation, one or more additional UEs (not shown) may also communicate with UT400 or UT 401. Alternatively, the UT and corresponding UE may be integrated parts of a single physical device, e.g., a mobile phone with an integrated satellite transceiver and antenna for communicating directly with the satellite.
Gateway 200 may have access to internet 108 or one or more other types of public, semi-private, or private networks. In the example shown in fig. 1, gateway 200 is in communication with infrastructure 106, where infrastructure 106 is able to access internet 108 or one or more other types of public, semi-private, or private networks. In addition, gateway 200 may also be coupled to various types of communication backhauls, including, for example, landline networks such as a fiber optic network or a Public Switched Telephone Network (PSTN) 110. Further, in alternative implementations, gateway 200 may interface with internet 108, PSTN 110, or one or more other types of public, semi-private, or private networks without the use of infrastructure 106. In addition, the gateway 200 may communicate with other gateways (e.g., gateway 201) through the infrastructure 106, or may alternatively be configured to communicate with the gateway 201 without the use of the infrastructure 106. The infrastructure 106 may include, in whole or in part, a Network Control Center (NCC), a Satellite Control Center (SCC), a wired and/or wireless core network, and/or any other component or system for facilitating operation of the satellite communication system 100 and/or communication with the satellite communication system 100.
Communications in both directions between the satellite 300 and the gateway 200 are referred to as feeder links, while communications in both directions between the satellite and each of the UTs 400 and 401 are referred to as service links. The signal path from the satellite 300 to a ground station (which may be the gateway 200 or one of the UT400 and UT 401) may be generally referred to as the downlink. The signal path from the ground station to the satellite 300 may be generally referred to as the uplink. Additionally, as described above, the signals may have a general directionality such as a forward link and a return link (or reverse link). Accordingly, communication links originating at the gateway 200 and terminating in the direction of the UT400 through the satellite 300 are referred to as forward links, while communication links originating at the UT400 and terminating in the direction of the gateway 200 through the satellite 300 are referred to as return links or reverse links. Thus, in fig. 1, the signal path from the gateway 200 to the satellite 300 is labeled as a "forward feeder link", and the signal path from the satellite 300 to the gateway 200 is labeled as a "return feeder link". In a similar manner, in fig. 1, the signal path from each UT400 or 401 to the satellite 300 is labeled as a "return service link," while the signal path from the satellite 300 to each UT400 or UT 401 is labeled as a "forward service link.
Fig. 2 is an exemplary block diagram of a gateway 200 that may also be applied to the gateway 201 of fig. 1. Gateway 200 is shown to include multiple antennas 205, an RF subsystem 210, a digital subsystem 220, a Public Switched Telephone Network (PSTN) interface 230, a Local Area Network (LAN) interface 240, a gateway interface 245, and a gateway controller 250. RF subsystem 210 is coupled to antenna 205 and digital subsystem 220. Digital subsystem 220 is coupled to PSTN interface 230, LAN interface 240, and gateway interface 245. Gateway controller 250 is coupled to RF subsystem 210, digital subsystem 220, PSTN interface 230, LAN interface 240, and gateway interface 245.
RF subsystem 210 (which may include a plurality of RF transceivers 212, RF controller 214, and antenna controller 216) may transmit communication signals to satellite 300 via forward feeder link 301F and may receive communication signals from satellite 300 via return feeder link 301R. Although not shown for simplicity, each of the RF transceivers 212 may include a transmit chain and a receive chain. Each receive chain may include a Low Noise Amplifier (LNA) and a down-converter (e.g., a mixer) to amplify and down-convert, respectively, a received communication signal in a well-known manner. In addition, each receive chain may also include an analog-to-digital converter (ADC) to convert the received communication signal from an analog signal to a digital signal (e.g., for processing by digital subsystem 220). Each transmit chain may include an upconverter (e.g., a mixer) and a Power Amplifier (PA) to upconvert and amplify, respectively, communication signals to be transmitted to the satellite 300 in a well-known manner. In addition, each transmit chain may also include a digital-to-analog converter (DAC) to convert digital signals received from digital subsystem 220 into analog signals to be transmitted to satellite 300.
The RF controller 214 may be used to control various aspects of the plurality of RF transceivers 212 (e.g., selection of carrier frequencies, frequency and phase calibration, gain settings, etc.). Antenna controller 216 may control various aspects of antenna 205 (e.g., beamforming, beam steering, gain setting, frequency tuning, etc.).
The digital subsystem 220 may include a plurality of digital receiver modules 222, a plurality of digital transmitter modules 224, a baseband (BB) processor 226, and a Control (CTRL) processor 228. Digital subsystem 220 may process communication signals received from RF subsystem 210, forward the processed communication signals to PSTN interface 230 and/or LAN interface 240, and process communication signals received from PSTN interface 230 and/or LAN interface 240, forward the processed communication signals to RF subsystem 210.
Each digital receiver module 222 may correspond to a signal processing unit for managing communications between the gateway 200 and the UT 400. One of the receive chains of RF transceiver 212 may provide an input signal to a plurality of digital receiver modules 222. Multiple digital receiver modules 222 may be used to accommodate all satellite beams and possible diversity mode signals being processed at any given time. Although not shown for simplicity, each digital receiver module 222 may include one or more digital data receivers, searcher receivers, and diversity combiner and decoder circuits. The searcher receiver may be used to search for the appropriate diversity mode of the carrier signal and may be used to search for the pilot signal (or other relatively fixed pattern of stronger signals).
The digital transmitter module 224 may process signals to be transmitted to the UT400 via the satellite 300. Although not shown for simplicity, each digital transmitter module 224 may include a transmit modulator for modulating the transmitted data. The transmit power of each transmit modulator may be controlled by a respective digital transmit power controller (not shown for simplicity), which may (1) apply a minimum level of power for interference reduction and resource allocation purposes; and (2) applying an appropriate level of power when compensation for attenuation in the transmission path and other path transfer characteristics is required.
A control processor 228 coupled to the digital receiver module 222, the digital transmitter module 224, and the baseband processor 226 may provide command and control signals to perform functions such as, but not limited to, signal processing, timing signal generation, power control, switching control, diversity combining, and system interfacing.
The control processor 228 may also control the generation and power of the pilot, synchronization and paging channel signals, as well as their coupling to a transmit power controller (not shown for simplicity). The pilot channel is a signal that is not modulated by data, and may use a repetition invariant pattern or an invariant frame structure type (pattern) or tone type input. For example, the orthogonal function of the channel used to form the pilot signal typically has a constant value (e.g., all 1 s or 0 s) or a well-known repeating pattern (e.g., a structured pattern of interspersed 1 s and 0 s).
The baseband processor 226 is well known in the art and is therefore not described in detail herein. For example, the baseband processor 226 may include a variety of known elements such as, but not limited to, an encoder, a data modem, and digital data exchange and storage components.
PSTN interface 230 may provide and receive communication signals to and from an external PSTN, either directly or through additional infrastructure 106, as shown in fig. 1. PSTN interface 230 is well known in the art and is therefore not described in detail herein. For other implementations, PSTN interface 230 may be omitted, or may be replaced with any other suitable interface that connects gateway 200 to a ground-based network (e.g., the internet).
The LAN interface 240 may provide communication signals to and receive communication signals from an external LAN. For example, LAN interface 240 may be coupled to the internet 108, either directly or through additional infrastructure 106, as shown in fig. 1. The LAN interface 240 is well known in the art and is therefore not described in detail herein.
Gateway interface 245 may provide communication signals to and receive communication signals from one or more other gateways associated with satellite communication system 100 of fig. 1 (and/or gateways associated with other satellite communication systems, not shown for simplicity). For some implementations, the gateway interface 245 may communicate with other gateways via one or more dedicated communication lines or channels (not shown for simplicity). For other implementations, gateway interface 245 may communicate with other gateways using PSTN 110 and/or other networks, such as internet 108 (see also fig. 1). For at least one implementation, gateway interface 245 may communicate with other gateways via infrastructure 106.
Overall gateway control may be provided by gateway controller 250. Gateway controller 250 may plan and control the use of resources by gateway 200 for satellite 300. For example, gateway controller 250 may analyze trends, generate service plans, allocate satellite resources, monitor (or track) satellite positions, and monitor the performance of gateway 200 and/or satellites 300. In addition, gateway controller 250 may also be coupled to a ground-based satellite controller (not shown for simplicity) that maintains and monitors the orbit of satellite 300, relays satellite usage information to gateway 200, tracks the position of satellite 300, and/or adjusts various channel settings of satellite 300.
For the exemplary implementation shown in fig. 2, gateway controller 250 includes a local time, frequency, and location reference 251, which reference 251 may provide local time or frequency information to RF subsystem 210, digital subsystem 220, and/or interfaces 230, 240, and 245. The time and frequency information may be used to synchronize the various components of the gateway 200 with each other and/or with the satellite 300. In addition, the local time, frequency, and location references 251 may also provide location information (e.g., ephemeris data) of the satellites 300 to various components of the gateway 200. Further, although depicted in fig. 2 as being included in gateway controller 250, for other implementations, local time, frequency, and location references 251 may be separate subsystems coupled to gateway controller 250 (and/or to one or more of digital subsystem 220 and RF subsystem 210).
Although not shown in fig. 2 for simplicity, gateway controller 250 may also be coupled to a Network Control Center (NCC) and/or a Satellite Control Center (SCC). For example, the gateway controller 250 may allow the SCC to communicate directly with the satellite 300, for example, to acquire ephemeris data from the satellite 300. In addition, the gateway controller 250 may also receive processed information (e.g., from the SCC and/or NCC) that allows the gateway controller 250 to properly aim its antennas 205 (e.g., at the appropriate satellites 300) to schedule beam transmissions, coordinate handovers, and perform various other well-known functions.
For illustrative purposes only, fig. 3 is an exemplary block diagram of a satellite 300. It should be understood that the particular satellite configuration may vary significantly, and may or may not include on-board processing. Further, although shown as a single satellite, two or more satellites using inter-satellite communications may provide functional connectivity between the gateway 200 and the UT 400. It should be understood that the present disclosure is not limited to any particular satellite configuration, and that any satellite or combination of satellites that may provide a functional connection between the gateway 200 and the UT400 may be considered to fall within the scope of the present disclosure. In one example, the satellite 300 is shown to include a forward transponder 310, a return transponder 320, an oscillator 330, a controller 340, forward link antennas 351 and 352, and return link antennas 361 and 362. Forward repeater 310, which may process communication signals within a corresponding channel or frequency band, may include a corresponding one of first bandpass filters 311(1) -311(N), a corresponding one of first LNAs 312(1) -312(N), a corresponding one of frequency converters 313(1) -313(N), a corresponding one of second LNAs 314(1) -314(N), a corresponding one of second bandpass filters 315(1) -315(N), and a corresponding one of PAs 316(1) -316 (N). Each of PAs 316(1) -316(N) is coupled to a respective one of antennas 352(1) -352(N), as shown in fig. 3.
In each of the respective forward paths FP (1) -FP (n), the first band-pass filter 311 passes signal components having frequencies within the channel or band of the respective forward path FP and filters signal components having frequencies outside the channel or band of the respective forward path FP. The pass band of the first band pass filter 311 thus corresponds to the width of the channel associated with the respective forward channel FP. The first LNA 312 amplifies the received communication signal to a level suitable for processing by the frequency converter 313. The frequency converters 313 convert the frequency of the communication signals in the respective forward path FP (e.g., to a frequency suitable for transmission from the satellite 300 to the UT 400). The second LNA 314 amplifies the frequency converted communication signal and the second band pass filter 315 filters signal components having frequencies outside the associated channel width. The PA316 amplifies the filtered signal to a power level suitable for transmission to the UT400 via the respective antenna 352. Return repeater 320, which includes a plurality N of return paths RP (1) -RP (N), receives communication signals from UT400 along return service link 302R via antennas 361(1) -361(N), and transmits communication signals to gateway 200 along return feeder link 301R via one or more antennas 362. Each of return paths RP (1) -RP (N), which may process communication signals in a respective channel or frequency band, may be coupled to a respective one of antennas 361(1) -361(N), and may include a respective one of first bandpass filters 321(1) -321(N), a respective one of first LNAs 322(1) -322(N), a respective one of frequency converters 323(1) -323(N), a respective one of second LNAs 324(1) -324(N), and a respective one of second bandpass filters 325(1) -325 (N).
In each of the respective return paths RP (1) -RP (n), the first band-pass filter 321 passes signal components having frequencies within the channel or band of the respective return path RP and filters signal components having frequencies outside the channel or band of the respective return path RP. Thus, for some implementations, the pass band of the first bandpass filter 321 may correspond to the width of the channel associated with the respective return path RP. The first LNA 322 amplifies all received communication signals to a level suitable for processing by the frequency converter 323. The frequency converter 323 converts the frequency of the communication signal in the corresponding return path RP (e.g., to a frequency suitable for transmission from the satellite 300 to the gateway 200). The second LNA 324 amplifies the frequency converted communication signal and the second band pass filter 325 filters signal components having frequencies outside the associated channel width. The signals from return paths RP (1) -RP (n) are combined and provided to one or more antennas 362 via PA 326. The PA 326 amplifies the combined signal for transmission to the gateway 200.
Oscillator 330 (which may be any suitable circuit or device for generating an oscillating signal) provides forward local oscillator signals lo (f) to frequency converters 313(1) -313(N) of forward repeater 310 and provides return local oscillator signals lo (r) to frequency converters 323(1) -323(N) of return repeater 320. For example, frequency converters 313(1) -313(N) may use lo (f) signals to convert communication signals from frequency bands associated with transmitting signals from gateway 200 to satellite 300 to frequency bands associated with transmitting signals from satellite 300 to UT 400. The frequency converters 323(1) -323(N) may use lo (r) signals to convert communication signals from a frequency band associated with transmitting signals from the UT400 to the satellite 300 to a frequency band associated with transmitting signals from the satellite 300 to the gateway 200.
A controller 340, coupled to the forward transponder 310, the return transponder 320, and the oscillator 330, may control various operations of the satellite 300, including (but not limited to) channel allocation. In one aspect, the controller 340 may include a memory (not shown for simplicity) coupled to the processor. The memory may include a non-transitory computer-readable medium (e.g., one or more non-volatile memory units such as EPROM, EEPROM, flash memory, a hard drive, etc.) that stores instructions that, when executed by the processor, cause the satellite 300 to perform operations including, but not limited to, those described herein.
In fig. 4, an example of a transceiver for use in the UT400 or the UT 401 is shown. In fig. 4, at least one antenna 410 is provided to receive forward link communication signals (e.g., from satellite 300), where the communication signals are passed to an analog receiver 414 where the communication signals are downconverted, amplified, and digitized. A duplexer unit 412 is typically used to allow the same antenna to serve both transmit and receive functions. Alternatively, the UT transceiver may use separate antennas to operate at different transmit and receive frequencies.
The digital communication signals output by the analog receiver 414 are communicated to at least one digital data receiver 416A and at least one searcher receiver 418. Additional digital data receivers up to 416N may be used to achieve the desired level of signal diversity depending on the acceptable level of transceiver complexity, as will be apparent to those of ordinary skill in the relevant arts.
At least one user terminal control processor 420 is coupled to the digital data receivers 416A-416N and the searcher receiver 418. Control processor 420 provides basic signal processing, timing, power and switching control or coordination, and selection of frequencies for signal carriers, among other functions. Another basic control function that may be performed by the control processor 420 is the selection or manipulation of functions for processing various signal waveforms. Signal processing by the control processor 420 may include determining relative signal strengths and calculating various relevant signal parameters. These calculations of signal parameters (e.g., timing and frequency) may include the use of additional or separate dedicated circuitry, providing increased efficiency or speed of measurement or improved allocation of control processing resources.
The outputs of the digital data receivers 416A-416N are coupled to digital baseband circuitry 422 in the user terminals. For example, the digital baseband circuitry 422 includes processing and presentation units for communicating information to and from the UE500 as shown in fig. 1. Referring to fig. 4, if diversity signal processing is used, the digital baseband circuitry 422 may include a diversity combiner and decoder. Some of these units may also operate under the control of the control processor 420 or in communication with the control processor 420.
When preparing voice or other data into an outgoing message or communication signal originating from a user terminal, the digital baseband circuitry 422 is used to receive, store, process, and otherwise prepare the desired data for transmission. The digital baseband circuitry 422 provides the data to a transmit modulator 426, which operates under the control of the control processor 420. The output of the transmit modulator 426 is delivered to a power controller 428, which provides output power control to a transmit power amplifier 430 for eventual transmission of the output signal from the antenna 410 to a satellite (e.g., satellite 300).
In fig. 4, the UT transceiver also includes memory 432 associated with the control processor 420. Memory 432 may include instructions for execution by control processor 420, as well as data for processing by control processor 420. In the example illustrated in fig. 4, memory 432 includes instructions for performing some or all of the processing discussed with reference to fig. 9 and 11.
In the example illustrated in fig. 4, the UT400 also includes an optional local time, frequency, and/or location reference 434 (e.g., a GPS receiver), which reference 434 can provide local time, frequency, and/or location information to the control processor 420 for various applications (e.g., which includes time and frequency synchronization for the UT 400).
Digital data receivers 416A-N and searcher receiver 418 are configured with signal correlation units for demodulating and tracking particular signals. Searcher receiver 418 is used to search for pilot signals or other relatively fixed pattern strong signals, while digital data receivers 416A-N are used to demodulate other signals associated with detected pilot signals. However, the digital data receiver 416 may be assigned to track the pilot signal after acquisition to accurately determine the signal-to-chip energy to signal-to-noise ratio to formulate the pilot signal strength. The outputs of these units can therefore be monitored to determine the energy or frequency of the pilot signal or other signal. These receivers also use frequency tracking units that can be monitored to provide current frequency and timing information to the control processor 420 for use in demodulating the signal.
The control processor 420 may use this information to determine the extent to which the received signal deviates from the oscillator frequency when adjusted to the same frequency band as appropriate. This and other information relating to the frequency error and frequency offset may be stored in a storage device or memory unit 432, as desired.
Further, the control processor 420 may also be coupled to UE interface circuitry 450 to allow communication between the UT400 and one or more UEs. The UE interface circuitry 450 may be configured to communicate with various UE configurations, as desired, and may thus include various transceivers and related components, depending on the various communication techniques used to communicate with the various UEs supported. For example, the UE interface circuitry 450 may include one or more antennas, a Wide Area Network (WAN) transceiver, a Wireless Local Area Network (WLAN) transceiver, a Local Area Network (LAN) interface, a Public Switched Telephone Network (PSTN) interface, and/or other known communication techniques configured to communicate with one or more UEs in communication with the UT 400.
Fig. 5 is a block diagram illustrating an example of a UE500, which may also be applied to the UE 501 of fig. 1. For example, the UE500 as shown in fig. 5 may be a mobile device, a handheld computer, a tablet device, a wearable device, a smart watch, or any type of device capable of interacting with a user. In addition, the UE may be a network side device for providing connectivity to various end user devices and/or various public or private networks. In the example illustrated in fig. 5, UE500 may include a LAN interface 502, one or more antennas 504, a Wide Area Network (WAN) transceiver 506, a Wireless Local Area Network (WLAN) transceiver 508, and a Satellite Positioning System (SPS) receiver 510. SPS receiver 510 may be compatible with the Global Positioning System (GPS), the Global navigation satellite System (GLONASS), and/or any other global or regional satellite based positioning system. In alternative aspects, for example, UE500 may include a WLAN transceiver 508 (with or without LAN interface 502), such as a Wi-Fi transceiver, a WAN transceiver 506, and/or an SPS receiver 510. Further, UE500 may include additional transceivers (with or without LAN interface 502), such as bluetooth, ZigBee, and other known technologies, WAN transceiver 506, WLAN transceiver 508, and/or SPS receiver 510. Thus, in accordance with various aspects disclosed herein, the elements shown for UE500 are provided as one exemplary configuration only, and are not intended to limit the configuration of the UE.
In the example shown in FIG. 5, processor 512 is connected to LAN interface 502, WAN transceiver 506, WLAN transceiver 508, and SPS receiver 510. Optionally, a motion sensor 514 and other sensors may also be coupled to the processor 512.
The memory 516 is connected to the processor 512. In an aspect, the memory 516 can include data 518 that can be transmitted to the UT400 and/or received from the UT400, as shown in fig. 1. Referring to fig. 5, the memory 516 may also include stored instructions 520 that are executed by the processor 512 for performing the process steps of communicating with the UT 400. Further, the UE500 may also include a user interface 522, which may include, for example, hardware and software for interfacing inputs or outputs of the processor 512 with a user through light, sound, or tactile inputs or outputs. In the example shown in fig. 5, the UE500 includes a microphone/speaker 524 connected to the user interface 522, a keypad 526, and a display 528. Alternatively, the user's tactile input or output may be integrated with the display 528, for example, by using a touch screen display. Again, the elements shown in fig. 5 are not intended to limit the configuration of the UE disclosed herein, it being understood that the elements included in UE500 will vary based on the end use of the device and the design choices of the system engineer.
Further, for example, UE500 can be a user equipment (e.g., a mobile device or an external network-side device) that is in communication with UT400 as shown in fig. 1, but separate from UT 400. Alternatively, the UE500 and the UT400 may be integrated parts of a single physical device.
Fig. 6 shows a signal processing system 600 that outlines some of the components of a UT or gateway. Shown in fig. 6 is a processor 602 (the term "processor" is intended to include multiple processor cores on one or more chips), a memory 604, and a modem 606 coupled to an antenna 608. The satellite link 610 may represent: originates from the gateway 200 or UT400 or 401 and terminates at any of the satellite links in fig. 1 of the satellite 300. Antenna 610 may be configured to transmit right-hand polarized electromagnetic radiation or left-hand polarized electromagnetic radiation and may include multiple elements for beam steering. For ease of illustration, a single bus (as labeled as bus 612) allows communication among the components in fig. 6, but in practice a UT or gateway may use one or more buses and one or more point-to-point interconnects or other types of interconnection technology.
Signal processing system 600 may implement one or more protocol stacks (e.g., protocol stack 614). For ease of illustration, the protocol stack 614 does not show all of the layers in a typical protocol stack. Shown in protocol stack 614 are physical layer (PHY)616, medium access control layer (MAC)618, and link layer 620. PHY 616 provides RF (radio frequency) modulation and demodulation for signals transmitted and received via antenna 608, PHY 616 and MAC 618 provide framing, encoding, and decoding (e.g., block coding, convolutional coding, turbo coding), and link layer 620 provides functionality that enables multiplexing and demultiplexing of data. The above functional descriptions of PHY 616, MAC 618, and link layer 620 are not meant to be exhaustive or exclusive, but are merely provided to indicate that their functionality is similar to some of the protocol layers in the open systems interconnection model (OSI) model.
Above the link layer 620 is an additional layer for accessing the internet or using voice over internet protocol (VoIP), such as an Internet Protocol (IP) layer 622 and an additional layer referred to in fig. 6 as an application and higher layer 624. The application and higher layers 624, along with the IP layer 622, along with the layers below them, define a communications plane for providing VoIP, web surfing, and other communications functions.
Other layers above link layer 620 may specify other planes. For example, the layer referred to as the signal and control layer 626 in fig. 6 provides additional functionality in the form of a signal plane and a control plane so that a voice call can be established and various parameters can be set (controlled).
Some functions of the layers in the protocol stack 614 may be performed by software running on the processor 602 and some functions may be performed by hardware under the control of firmware. In some instances, some of the functions of the layers in the protocol stack 614 may be performed by special purpose hardware, such as an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA). For example, modem 606 may perform some or all of the functions of PHY 616. Software for performing some of the functions of the protocol stack 614, as well as other functions to be described, may be stored in the memory 604. Memory 604 may represent a hierarchy of memory, which may be referred to as non-transitory computer-readable media.
The signal processing system 600 may implement multiple instances of the protocol stack 614, as well as other protocol stacks for communicating with other devices (e.g., UE500 or 501). The protocol stack provides functionality for implementing multiple physical and logical channels for the forward or return link.
Fig. 7A shows a communication structure 710 for the forward link. A plurality of time slots are transmitted from gateway 200 to the plurality of UTs, wherein three time slots are depicted: an (n-1) th slot 704, an nth slot 706, and an (n +1) th slot 708. A slot represents the smallest unit of transmission time, the duration of which may be referred to as a transmission time interval. A slot includes three components: pilot 712, control 714, and data 716. The time slot may include other components. Pilot 712 comprises a pilot signal that may be used by the UT for synchronization, equalization, channel quality estimation, and so on. The data 716 comprises a data payload intended for one or more user terminals, and the control 714 comprises information elements describing the data 716 as discussed below.
The MAC 618 and PHY 616 can insert multiple blocks in the data 716, where each block is intended for one UT. More than one block in data 716 may be intended for the same UT. Different blocks may have different lengths. In particular, to achieve flexibility, it is contemplated that individual blocks at one time or other will likely occupy different lengths in the data 716.
The information element in control 714 indicates: how many blocks are contained in the data 716, which block belongs to which UT, and the relative position and length of each block in the data 716. For example, three blocks in data 716 are depicted as: block (i-1)718, block (i)720, and block (i +1) 722. The information element 724 includes information related to one or more blocks in the data portion of the slot. For example, for block (i), the information element 724 may provide its relative position and length in the data 716, which UT it is for, the type of coding scheme, and the type of modulation scheme. The information element 724 may include information related to other blocks, and whether it is irrelevant whether the information element 724 is regarded as single data (information data on a single block) having information on a single block, or information data on a plurality of blocks.
The information element 724 may represent any of a large number of possible block mappings for the user terminal. For example, data 724 in FIG. 7B includes five blocks: for some arbitrary index i, block (i-2) through block (i + 2). Data 724 may include additional blocks. Similar labels apply to the data 726 shown in FIG. 7C. In FIG. 7B, for data 724, three blocks (block (i-2), block (i-1), and block (i)) are mapped to UT 728, and two blocks (block (i +1) and block (i +2)) are mapped to UT 730. In FIG. 7C, for data 726, five blocks (block (i-2), block (i-1), block (i +1), and block (i +2)) are mapped to UT 732. Obviously, a large number of mappings are possible.
The PHY 616 of fig. 6 may use various types of coding (encoding and decoding) schemes, such as block coding, convolutional or turbo coding, and combinations thereof (e.g., concatenated coding using outer codes in conjunction with inner codes). Also, interleaving may be used, which may be considered as part of the coding scheme. Therefore, a CRC (cyclic redundancy check) may be generated from the information bits and appended to the information bits for error control.
PHY 616 converts the data symbols (e.g., bits) of the block into channel symbols. For example, every B bits in a block may be combined together and each such group mapped to a signal in a signal constellation space comprising at least 2BA signal point. The combination of modulation and coding may be represented by an index value, which is referred to as MCI (modulation and coding index) for the convenience of description herein. By way of the information element, control 714 in fig. 7A provides the value of the MCI for the block. However, in some implementations, the UT may use blind detection and error control, where in this case the MCI for the block for which it is decoding is not sent along with the block. Regardless of whether MCI is transmitted or not, different modulation and coding schemes may be used for different blocks, so there are moreMultiple modulation and coding schemes may be used for multiple blocks in a slot to one or more UTs.
The various satellite communication links may use various access schemes (e.g., single carrier TDMA). The signal constellation space may represent any of a number of well-known modulation techniques, such as PSK (phase shift keying), QPSK (quadrature phase shift keying), or different levels of QAM (quadrature amplitude modulation) (e.g., 16-QAM, 64-QAM, etc.).
Fig. 8 shows a signal processing chain for PHY 616 to perform coding and modulation. Based on the value of MCI802, encoder 804 encodes the information data, which may implement, for example, a block encoder, a convolutional or turbo encoder, or a concatenated coding scheme. The encoder 804 may include interleaving. Modulation symbol mapper 806 maps the bit space to a signal constellation space, whereby one or more bits are grouped together and mapped to a modulation symbol, as previously discussed. The baseband signal is converted to RF by RF (radio frequency) modulation, symbolized by an RF modulator 808, where the RF output signal is fed to an antenna 810.
Fig. 8 shows a portion of a signal processing chain of a UT or gateway. Further, the modulation and coding scheme used by the UT for transmission may be different from the modulation and coding scheme used by the gateway to transmit data to the UT.
A user terminal may determine the channel quality of its satellite communication link based on various measured parameters, for example, by measuring the signal-to-noise ratio or by calculating the accumulated frame error rate (or bit error rate) over a certain time period. The channel quality may be encoded into a value of an information element, which may be referred to as Channel State Information (CSI). The value of the CSI for the UT (e.g., UT400 or 401) may be sent to gateway 200. Based on the value of the CSI, in one implementation of signal processing system 600, gateway 200 assigns to UT400 or 401 a value for its MCI, where the value is placed in control 714 and used in the signal processing chain of fig. 8, as previously discussed.
Since the coverage and channel propagation characteristics of the satellite 300 change over time and depend on the relative location of the user terminals to the satellite 300, different user terminals may experience different channel qualities for their respective communication links. As a result, the modulation and coding scheme appropriate for one UT may not be appropriate for the other UTs. That is, to achieve the same BLER (block error rate), data for those user terminals with relatively lower quality satellite links may require a modulation and coding scheme with lower spectral efficiency than data intended for those user terminals with higher quality links. As a result, it is expected that different modulation and coding schemes are assigned to the respective blocks in one time slot to obtain the overall efficiency of spectrum usage.
In some system implementations, the UTs 400 or 401 may determine their respective modulation and coding schemes, while in other implementations, the gateway 200 may determine the modulation and coding schemes. For example, the signal processing system 600 may store a look-up table by which values of CSI are mapped to values of MCI so that appropriate modulation and coding schemes may be determined.
Furthermore, the modulation and coding scheme may be changed for retransmission of the block. For example, a relatively high spectral efficiency may be selected for the initial transmission of a block, and when the sender of the block (e.g., gateway 200 or UT400 or 401) determines that the block has been lost or received in error, a new modulation and coding scheme is selected for the retransmission of the block to improve BLER at the expense of spectral efficiency. For example, the PHY 616 may receive a NAK (negative acknowledgement) and determine that the block has been lost or received in error, in which case the processor 602 running the protocol stack 614 resets the MCI802 so that less spectrally efficient modulation and coding is used. (the convention may be chosen so that as the MCI value increases, so does the spectral efficiency, or at least it does not fall off.
Fig. 9 illustrates various processes and procedures performed by a gateway and a user terminal in a satellite communication system. While the actions indicated in fig. 9 are shown using a sequential flow chart, they need not be performed in the order indicated in fig. 9, nor is it necessary for the gateway or user terminal to perform all of the indicated actions. That is, some of the actions indicated in fig. 9 are optional and need not be performed in a satellite communication system.
As previously described and depicted in fig. 9, as indicated in act 902, a plurality of user terminals determine their respective CSI based on parameters such as signal-to-noise ratio, accumulated bit or frame error rate, or perhaps other parameters measured or obtained by the satellite 300. As indicated in act 904, the user terminals send the values of their respective CSI to gateway 200 using the return link of the satellite communication system. In act 906, gateway 200 encodes and modulates each block based on the CSI of its intended (corresponding) UT. As discussed above, the gateway may assign a particular modulation and coding scheme (indicated by the value of the MCI) to each user terminal based on the CSI for that user terminal. In other implementations, gateway 200 may determine the modulation and coding scheme without CSI.
In act 908, the gateway 200 transmits the blocks coded and modulated in act 906 intended for the respective user terminals in a single time slot, wherein the modulation and coding scheme for the respective blocks is based on the scheme to which the gateway 200 is assigned. In explaining the actions of fig. 9, the use of the plural term "block" also encompasses the singular term "block" such that in action 908, there may be only one block in the transmitted time slot. In act 910, the user terminals demodulate and decode their respective blocks using their assigned modulation and coding schemes (as indicated by their respective MCIs).
As indicated in act 912, if the block for a particular user terminal has been determined to be lost or received in error, the gateway may change the modulation and coding scheme (as indicated by the value of the assigned MCI) when retransmitting the block in another time slot. A new modulation and coding scheme (as indicated by the lower value of MCI) is selected to reduce BLER at the expense of a reduction in spectral efficiency.
Communication systems provide flexibility in the spectral efficiency of modulation and coding used for transmission and retransmission. In one exemplary implementation of the communication system, a first modulation and coding scheme is selected for a first transmission of a block, whether by a gateway to a user terminal via a satellite (forward link) or by a user terminal to a gateway via a satellite (return link); if a block is lost or received in error, a second modulation and coding scheme is selected for retransmission of the block (second transmission). The first transmission has a relatively higher spectral efficiency than the second transmission.
For example, the second modulation and coding scheme may use a lower order modulation and a lower rate turbo coding relative to the first modulation and coding scheme. Further, the first modulation and coding scheme does not use concatenated coding, but the second modulation and coding scheme may use concatenated coding in which a BCH code is used as an outer code and a turbo code is used as an inner code.
It should be appreciated that the retransmitted block may occupy a larger portion of the time slot than when it was first transmitted. That is, the retransmission may use more resources in time. For example, in the case of a more robust coding scheme using more error control bits, the extra bits used for error correction cause the block to occupy more symbol positions (for the same modulation scheme) in the transmitted slot than when the block was transmitted for the first time. When implemented, a first transmitted block may occupy a relatively small portion of a time slot, such that when the block is retransmitted it may be scheduled with fewer other blocks, such that it may occupy a larger portion of its time slot than when it was first transmitted, but in any event, the retransmitted block may fit within a single time slot. In this way, re-segmentation of the block can be avoided. (it should also be noted that a communication system designed to avoid re-segmentation may ensure that blocks that are retransmitted occupy a larger portion of the time slot for retransmission changes to lower order modulations may also contribute to re-transmission.): the blocks in the first transmission occupy only a relatively small portion of the time slot. How small the portion should be can be determined based on how much more coding gain is expected in the retransmission.
In some implementations, a communication system can be designed such that a first transmission of a block and each subsequent retransmission of the block (e.g., a second transmission, a third transmission, etc.) have different target BLERs. For example, consider a communication system having 10 that uses turbo codes without outer codes-4An error floor (error floor) of the order of (d). Compared with the error floor of turbo code, has 10-3Has a larger target BLER, so turbo codes are used without the use of outer codes. Has 10 compared to the error floor of turbo codes (when used without outer codes)-6The retransmission of target BLER of (b) has a smaller target BLER, in which case concatenated coding should be used, e.g., turbo code as inner code and Bose-Chaudhuri-hocquenghem (bch) code as outer code. The concatenated code should have a size of less than 10-6Error floor of (2).
In the above example, the first transmission of the block occupies a relatively small portion of the time slot. Upon retransmission, the block may occupy a larger portion of the slot than its first transmission without re-segmenting the block, thereby avoiding overflowing the slot. The communication structure shown in fig. 7A achieves the advantage of avoiding fragmentation.
Fig. 10 shows a concatenated coding scheme that may be used by a user terminal or gateway. In the example of FIG. 10, the outer encoder 1002 encodes the information bits according to a BCH code, where the inner encoder 1004 encodes the output of the outer encoder 1002 according to a turbo code (which may be referred to as an inner turbo code). The inner decoder 1006 decodes the received bits according to the turbo code implemented by the inner encoder 1004, and the outer decoder 1008 decodes the output of the inner decoder 1006 according to the BCH code implemented by the outer encoder 1002. The outer encoder 1002 and the inner encoder 1004 may be considered as a super encoder 1010, and the inner decoder 1006 and the outer decoder 1008 may be considered as a super decoder 1012. Inner encoder 1004 and inner decoder 1006 (when combined with the original channel 1014 observed by inner encoder 1004 and inner decoder 1006) may be considered a super channel 1016.
Table 1018 provides t (error correction capability) of the outer BCH code depending on the code block length (CB) in bits and the code rate of the inner turbo code. For example, for a magnitude of 10-6For a target BLER of (d), the outer BCH is not used for code block lengths less than or equal to 512 bits. For larger code block lengths (e.g., 1024, 2048, and 6144 bits), t-6 outer BCH codes are used in conjunction with the turbo code rates of 1/2 and 1/3, and t-10 outer BCH codes are used in conjunction with the turbo code rate of 2/3. However, using the outer code to reduce the error floor comes at the cost of degrading the performance of the waterfall region of the BLER curve.
Fig. 11 shows an ARQ (automatic repeat request or automatic repeat query) method. The gateway as well as the UT may implement the method shown in fig. 11, but for the case of a UT, there is no mix of multiple blocks from multiple UTs in one slot. For the gateway, the flexible communication structure shown in fig. 7A allows: ARQ retransmissions occur with lower spectral efficiency and without re-segmentation. Fig. 11 illustrates several acts whereby a communication system may implement an adaptive ARQ method in which a first transmission of a block is spectrally efficient as compared to a retransmission of the block. The actions listed in fig. 11 are associated with a particular block, where the index n (not the same index shown in fig. 7A) refers to the number of retransmissions for that block. Index n is initialized to 0 as indicated in act 1100.
In act 1102, a modulation and coding scheme is selected. The selection may be based on the index n. For example, the modulation selected when n is 1 may be a lower order modulation than that selected when n is 0. However, the selection in act 1102 does not include concatenated coding, so there is no outer code.
In act 1104, a determination is made as to whether the target BLER is less than the error floor. The target BLER in act 1104 is shown to be indexed by n to indicate that the particular value selected for the target BLER may depend on the value of index n. For example, when n is 0, 10 may be selected-3When n is equal to>When 0 (which represents retransmission), the value of the target BLER may be selected to be 10-6. However, it should be understood that these are only examples. The value of the error floor used in act 1104 is specific to the particular modulation and coding scheme selected in act 1102.
If the value of the target BLER is equal to or greater than the error floor, control is taken to act 1106 such that the modulation and coding scheme selected in act 1102 is the scheme to be used. Otherwise, control is taken to act 1108, where concatenated coding is enabled, thereby using the outer code. The particular outer code selected may depend on the encoding selected in act 1102, as indicated by the parenthetical description in act 1108. For example, the code rate of the outer code may depend on the encoding selected in act 1102. The encoding selected in act 1102 may now be referred to as an inner code since concatenated encoding is enabled.
As indicated in act 1110, the block is transmitted using the modulation and coding scheme as determined by the previous act. As indicated in act 1112, if an ACK (acknowledgement) is received, then in act 1114, no retransmission is required. If a NAK (negative acknowledgement) is received, the index n is incremented by 1 in act 1116 and control is brought back to act 1102 and the process is repeated again for that particular block for retransmission in another time slot.
Fig. 12 shows an example of concatenated coding with inner turbo codes and outer systematic block coding. Each block of data (e.g., blocks 718, 720, and 722 as shown in fig. 7 and 12) is segmented into sub-blocks, which are encoded using a systematic block encoder for outer encoding and a turbo encoder for inner encoding.
Referring to fig. 12, block 720 is provided for a concatenated coding scheme. In act 1202, a CRC (cyclic redundancy check) is computed for block 720 and appended to the block. The appended bits need not necessarily be a CRC, so other types of check bits can be computed, but since the algebraic structure of the CRC facilitates efficient computation, it is typically used for error correction. As will be described in fig. 13, the CRC calculated in act 1202 is used to assert whether block 720 has been correctly decoded (when it is received by the UT).
In act 1204, the block 720 with its appended CRC is partitioned into sub-blocks, indicated as: b (1), B (2), …, B (n). The segmentation is performed to match the computational requirements of turbo decoding to the available hardware such that turbo encoding and turbo decoding are performed on a sub-block by sub-block basis.
In act 1206, each sub-block is encoded using a systematic block encoder to implement an outer encoding scheme (e.g., the outer encoder shown in fig. 10). The BCH encoding scheme is one particular example of a block encoder for act 1206, but other encodings (e.g., Reed Solomon encoding) may be used. The systematic block encoder in act 1206 does not need to be cyclic in its algebraic structure.
Since the encoding scheme in act 1206 is systematic, the original sub-blocks are available for act 1208. For each sub-block, act 1208 computes a CRC and attaches it to the sub-block. The UT receiving a particular sub-block uses the received CRC for that sub-block to determine when to stop the iteration of the turbo decoder. Act 1208 is not required.
In act 1210, turbo encoding is performed for each sub-block with its appended CRC. The turbo encoder in act 1210 provides a stream of systematic bits and parity bits to a circular buffer 1214. The rate of the turbo encoder in act 1210 may be 1/3 such that two parity bits are provided for each systematic bit, although other turbo encoders may also be used. In the particular example of fig. 12, act 1212 applies row and column interleaving to the output of the turbo encoder.
The circular buffer 1214 is sampled to provide the appropriate code rate required by the modulation symbol mapper 806 of fig. 8. The sampling may include puncturing such that not all of the parity bits provided by the turbo encoder are transmitted, or the circular buffer 1214 may be oversampled in the case where some of the systematic bits and parity bits are repeated in the transmission. The functional units indicated by acts 1210, 1212 and 1214 may be combined together, at which time the combination may also be referred to as a turbo encoder, as indicated by the dashed box 1215. The output of the circular buffer 1214 (or turbo encoder 1215) in response to a block of data (e.g., block 720 in slot 706 of fig. 7) may be referred to as an encoded sub-block. Each such encoded sub-block is obtained by applying turbo coding to the sub-block with its appended CRC, where the sub-block is a subset of the block (e.g., block 720).
For example, for any index k, the encoded sub-blocks for sub-block B (k) may be represented using data structure 1226 of CB (k) such that for sub-blocks B (1), B (2), …, B (n) provided by the segmentation in act 1204, turbo encoder 1215 provides encoded sub-blocks CB (1), CB (2), …, CB (n).
Act 1216 concatenates the parity bits provided from the systematic block encoder of act 1206, where parity block PB represents a concatenation (or combination) of these parity bits. The parity block PB may then be treated in the same manner as the systematic bits provided by the systematic block encoder of act 1206. However, some implementations may partition the parity block PB according to the computational power of the turbo decoder of the destination UT, but for ease of illustration the implementation represented by fig. 12 does not partition the parity block PB into smaller parity blocks.
Act 1218 calculates a CRC for the parity block PB and appends it to the parity block PB, although in some implementations act 1218 is optional. The circular buffers in acts 1220, 1222 and act 1224 are essentially identical to their corresponding components 1210, 1212 and 1214, so the overall functionality represented in acts 1220, 1222 and 1224 can be combined and viewed as a turbo encoder 1225, although the particular turbo code used for turbo encoder 1225 can be different from the turbo code used for turbo encoder 1215. The output of the circular buffer 1224 (the output of the turbo encoder 1225) may be referred to as an encoded parity block CPB.
The encoded sub-blocks from the turbo encoder 1215 and the encoded parity block CPB from the turbo encoder 1225 are concatenated and sent into a data structure 1226. The concatenation of the encoded sub-blocks CB (1), CB (2), …, CB (n) into data structure 1226 will be the same as the outer encoder in the miss action 1206. Therefore, a signal processing structure for encoding and decoding a turbo code without an outer code may be used in the concatenated coding scheme of fig. 12.
Fig. 13 illustrates decoding for the concatenated coding scheme of fig. 12. In act 1302, each received encoded sub-block cb (k)' received in response to transmission of an arbitrary block (referred to as block (i) in fig. 13) according to data structure 1226 in fig. 12, where k is 1,2, …, n, is decoded using a turbo decoder. The prime sign in cb (k)' distinguishes the received coded sub-block from the transmitted coded sub-block cb (k). The turbo decoder in the UT uses the received CRC in each received encoded sub-block cb (k)' to determine when to stop the iterative process inherent in turbo decoding. In fig. 13, the output of the turbo decoder in act 1302 is all sub-blocks b (k) 'associated with block (i), where the index k runs from 1 to n, and the prime notation indicates that b (k)' is an estimate of the sub-block b (k) transmitted. If all errors, if any, have been corrected, b (k)' ═ b (k).
At act 1304, sub-blocks b (k)' are concatenated together to provide the transmitted block and an estimate of the block CRC. That is, sub-blocks b (k)' are concatenated providing an estimate of the block transmitted (e.g., block 720, block (i) of fig. 12) and an estimate of the block CRC appended to the block transmitted in act 1202 of fig. 12. If the estimated block CRC passes in act 1304, then it is declared that the estimate of the transmitted block is the transmitted block, and the signal processing flow diagram of FIG. 13 may exit, as indicated by act 1306.
It should be noted that up to and including act 1304, outer decoding has not been employed, such that if the estimated block CRC passes in act 1304, the received encoded parity block CPB' is not needed.
If the estimated block CRC fails in act 1304, act 1308 turbo decodes the received coded parity block CPB ', where the received coded parity block is distinguished from the transmitted coded parity block CPB using the upper apostrophe in CPB'. The output of the turbo decoder in act 1308 is marked as PB', the estimate of the parity block PB obtained in acts 1206 and 1216. While acts 1308 and 1302 are indicated as separate acts in the signal processing diagram of fig. 13, the same signal processing structure may be used for both acts when implemented. As in act 1302, the turbo decoder in act 1308 uses the received CRC in the received encoded parity block CPB' to determine when to stop its iterative process. If all errors (if any) are corrected, then PB' ═ PB.
In act 1310, the outer decoder decodes b (k) 'using PB', where k is 1,2, …, n, the output of the turbo decoder in act 1302. For example, the outer decoder looks for a codeword with the smallest hamming distance from the word [ B (1) ' | B (2) ' | … | B (n) | PB ' ] to provide the outer decoded sub-block B (k) ', where k ═ 1,2, …, n, where double prime refers to the received encoded sub-block cb (k) ', to which both inner turbo decoding and outer decoding have been applied.
In action 1312, b (k)' is concatenated (where k is 1,2, …, n) to form a second estimate of the transmitted block with block CRC, and the (second) estimated block CRC is checked. The signal processing structure used for act 1304 may be used for act 1312. If the (second) estimated block CRC passes, as in act 1304, then it is assumed that the received block has been correctly decoded and is available to higher layers in the protocol stack, as indicated by act 1314.
If the (second) estimated block CRC fails in act 1312, other actions may be taken as indicated in block 1316. For example, the UT may send a NAK message so that the gateway can send the data structure 1226 again, or may discard the received data.
If the parity bits obtained by the systematic encoder of act 1206 for a group of sub-blocks of a block are combined into multiple parity blocks, act 1218 is repeated such that a CRC is calculated and appended to each parity block, followed by turbo encoding each parity block with the appended CRC. Subsequently, the data structure 1226 will include a plurality of encoded parity blocks. Where multiple encoded parity blocks are received at the UT, act 1308 is repeated for each received encoded parity block associated with the received block (i.e., received data structure 1226). The decoded parity block is then used for outer decoding in act 1310.
The PHY 616 and MAC 618 layers of the signal processing system 600 of fig. 6 may perform the signal processing actions indicated in fig. 12 and 13, where for the actions of fig. 12, the signal processing system 600 is in a gateway (e.g., gateway 200 in fig. 1), and for the actions of fig. 13, the signal processing system 600 is in a UT (e.g., UT400 in fig. 1 (or any other user terminal)).
Fig. 14 illustrates an exemplary gateway apparatus 1400 represented as a series of interrelated functional modules (as discussed with reference to the examples of fig. 6-11). A module 1402 for receiving channel state information may correspond at least in some aspects to, for example, a signal processing system or a component thereof (e.g., signal processing system 600 of fig. 6, etc.) as discussed herein. A module 1404 for encoding the plurality of blocks may correspond at least in some aspects to, for example, a signal processing system or component thereof as discussed herein (e.g., signal processing system 600 of fig. 6, etc.). The module 1406 for modulating the coded blocks into modulated and coded blocks may correspond at least in some aspects to, for example, a signal processing system or component thereof (e.g., the signal processing system 600 of fig. 6, etc.) discussed herein. A module 1408 for transmitting time slots comprising modulated and coded blocks may correspond at least in some aspects to, for example, a signal processing system or a component thereof as discussed herein (e.g., signal processing system 600 of fig. 6, etc.).
Fig. 15 illustrates another exemplary gateway apparatus 1500 that is represented as a series of interrelated functional modules (as discussed with reference to the examples of fig. 12-13). A module 1502 for providing and appending block checks to a block may correspond at least in some aspects to, for example, a signal processing system or component thereof (e.g., signal processing system 600 of fig. 6, etc.) as discussed herein. The module 1504 for partitioning a block with additional block checks into one or more sub-blocks may correspond at least in some aspects to, for example, a signal processing system or component thereof (e.g., signal processing system 600 of fig. 6, etc.) discussed herein. A module 1506 for encoding the sub-blocks using the systematic encoder to provide parity bits may correspond at least in some aspects to, for example, a signal processing system or component thereof (e.g., signal processing system 600 of fig. 6, etc.) as discussed herein. A module 1508 for providing sub-block checks for each sub-block and appending the respective sub-block checks may correspond at least in some aspects to, for example, a signal processing system or component thereof as discussed herein (e.g., signal processing system 600 of fig. 6, etc.). The module 1510 for turbo encoding the sub-blocks with additional sub-block checks to provide encoded sub-blocks may correspond at least in some aspects to, for example, a signal processing system or component thereof (e.g., signal processing system 600 of fig. 6, etc.) discussed herein. The module 1512 for grouping parity bits into parity blocks may correspond at least in some aspects to, for example, a signal processing system or component thereof as discussed herein (e.g., signal processing system 600 of fig. 6, etc.). A module 1514 for providing parity block checks for the parity blocks and appending corresponding parity block checks may correspond at least in some aspects to, for example, a signal processing system or component thereof (e.g., signal processing system 600 of fig. 6, etc.) as discussed herein. The module 1516 for turbo encoding the parity block with the appended parity block checks to provide an encoded parity block may correspond at least in some aspects to, for example, a signal processing system as discussed herein or a component thereof (e.g., the signal processing system 600 of fig. 6, etc.). The module 1518 for transmitting the concatenation of the encoded sub-blocks and the encoded parity block may correspond at least in some aspects to, for example, a signal processing system or a component thereof (e.g., the signal processing system 600 of fig. 6, etc.) discussed herein.
Fig. 16 shows an exemplary user terminal device 1600 represented as a series of interrelated functional modules (as discussed with reference to the examples of fig. 12 and 13). A module 1602 for turbo decoding the encoded sub-blocks to provide a first estimate of the sub-blocks may correspond at least in some aspects to, for example, a signal processing system or component thereof (e.g., signal processing system 600 of fig. 6, etc.) discussed herein. The module 1604 for concatenating the first estimates of the sub-blocks to provide a first estimate of a block with a first estimate of a block check may correspond at least in some aspects to, for example, a signal processing system as discussed herein or a component thereof (e.g., the signal processing system 600 of fig. 6, etc.). The module 1606 for determining whether the first estimate of block checks passed or failed may correspond at least in some aspects to, for example, a signal processing system or component thereof discussed herein (e.g., the signal processing system 600 of fig. 6, etc.). The module 1608 for turbo decoding the received encoded parity block to provide an estimate of the parity block when the first estimate of block checking fails may correspond at least in some aspects, for example, to the signal processing system discussed herein or a component thereof (e.g., the signal processing system 600 of fig. 6, etc.). The module 1610 for outer-decoding the first estimate of the sub-block using the estimate of the parity block to provide a second estimate of the sub-block when the first estimate of the block check fails may correspond at least in some aspects to, for example, a signal processing system or a component thereof (e.g., the signal processing system 600 of fig. 6, etc.) as discussed herein. The module 1612 for concatenating the second estimates of the sub-blocks to provide the second estimate of the block with the second estimate of the block check may correspond at least in some aspects, for example, to a signal processing system or components thereof discussed herein (e.g., the signal processing system 600 of fig. 6, etc.) when the first estimate of the block check fails. The means 1614 for determining whether the second estimate of the block check passed or failed when the first estimate of the block check failed may correspond at least in some aspects, for example, to the signal processing system discussed herein or a component thereof (e.g., the signal processing system 600 of fig. 6, etc.).
The functionality of the modules of fig. 14, 15, and 16 may be implemented in a variety of ways consistent with the teachings herein. In some designs, the functionality of these modules may be implemented as one or more electrical components. In some designs, the functions of these blocks may be implemented as a processing system including one or more processor components. In some designs, the functionality of these modules may be implemented using, for example, at least a portion of one or more integrated circuits (e.g., ASICs). As discussed herein, an integrated circuit may include a processor, software, other related components, or some combination thereof. Thus, the functionality of the different modules may be implemented as different subsets of an integrated circuit, as different subsets of a set of software modules, or as a combination thereof, for example. Further, it should be understood that a given subset (e.g., of an integrated circuit and/or a set of software modules) may provide at least a portion of the functionality for more than one module.
Further, the components and functions represented by fig. 14, 15, and 16, as well as other components and functions described herein, may also be implemented using any suitable means. Furthermore, these units may also be implemented, at least in part, using corresponding structures as taught herein. For example, the components described above in connection with the "module for … …" component of fig. 14, 15, and 16 may also correspond to the similarly designated "unit for … …" functionality. Thus, in some aspects, one or more of these units may be implemented using one or more of a processor component, an integrated circuit, or other suitable structure as taught herein.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Furthermore, those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The methods, sequences and/or algorithms disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium may be coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
Accordingly, aspects of the claimed subject matter can include a non-transitory computer-readable medium embodying a method for spectrally efficient data transmission in a satellite system. Accordingly, the claimed subject matter is not limited to the illustrated examples.
While the foregoing disclosure shows illustrative aspects of the claimed subject matter, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims described herein need not be performed in any particular order. Furthermore, although aspects of the claimed subject matter may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.