Method of assembling printable semiconductor elements and manufacturing electronic devicesThis application is a divisional application of the invention patent application No. 201010519400.5 entitled "method and apparatus for manufacturing and assembling printable semiconductor elements" filed on 2005, 6/2, which was originally filed on 200580018159.5.
Cross Reference to Related Applications
Priority is claimed in this application to U.S. provisional patent application nos. 60/577,077, 60/601,061, 60/650,305, 60/663,391 and 60/677,617, filed on 4/2004, 11/2004, 2/2005, 4/2005, 3/2005, 18/2005 and 5/4/2005, respectively, the entire contents of which are hereby incorporated by reference in their entirety into this specification to the extent not inconsistent with the disclosure of this application.
Background
Since the first appearance of printed all-polymer transistors in 1994, a potential new class of electronic systems containing flexible integrated electronics on plastic substrates has attracted considerable attention [ Garnier, f., Hajlaoui, r., Yassar, a. and Srivastava, p., Science, vol.265, pages 1684-1686 ]. Recently, much research has been conducted on developing new solution processable materials for conductors, insulators, and semiconductors of flexible plastic electronic devices. However, advances in the field of flexible electronic devices have been driven not only by the development of new solution processable materials, but also by new geometries for device components, efficient devices, and device component processing methods and high resolution patterning techniques suitable for plastic substrates. Such materials, device configurations, and fabrication methods are expected to play an important role in the rapid emergence of new types of flexible integrated electronic devices, systems, and circuits.
The focus in the field of flexible electronics is primarily due to several important advantages of this technology. First, the mechanical strength of the plastic substrate material makes the electronic device less susceptible to damage and/or degradation of electronic performance due to mechanical stress. Second, the inherent flexibility of these substrate materials allows them to be integrated into a variety of shapes that are required for a large number of useful device configurations, which are not achievable with fragile conventional silicon-based electronic devices. For example, flexible electronic devices that are bendable are expected to enable the fabrication of new devices that are not easily implemented by existing silicon-based technologies, including, for example, electronic paper, wearable computers (weberable computers), and large-screen high-resolution displays. Finally, the combination of solution processable component materials with plastic substrates enables fabrication by continuous, high speed printing techniques that can produce electronic devices over large substrate areas at low cost.
However, the design and manufacture of flexible electronic devices that exhibit good electronic performance faces a number of significant challenges. First, well-developed methods of manufacturing conventional silicon-based electronic devices are incompatible with most plastic substrates. For example, conventional high quality inorganic semiconductor components, such as single crystal silicon or germanium semiconductors, are typically processed by growing thin films at temperatures well above the melting or decomposition temperatures (> 1000 ℃) of most plastic substrates. In addition, most inorganic semiconductors are themselves insoluble in convenient solvents that facilitate solution-based processing and transport. Second, while many amorphous silicon, organic or hybrid organic-inorganic semiconductors (amorphous silicon-inorganic semiconductors) are compatible for incorporation into plastic substrates and can be processed at relatively low temperatures, these materials do not have the electronic properties that enable integrated electronic devices to exhibit good electronic performance. For example, thin film transistors having semiconductor elements made of these materials exhibit field effect mobilities that are about three orders of magnitude smaller than single crystal silicon based complementary devices. These limitations have led to the fact that flexible electronic devices are currently limited to specific applications that do not require high performance, such as in switching elements of active-matrix flat-panel displays with non-emissive pixels (non-emissive pixels) and in light-emitting diodes.
Recent advances have been made in expanding the electronic performance capabilities of integrated electronic devices on plastic substrates to broaden their applicability to electronic device applications. For example, several new Thin Film Transistors (TFTs) have emerged which are compatible with processing methods carried out on plastic substrate materials and which exhibit device performance characteristics which are significantly higher than those of thin film transistors having amorphous silicon, organic or hybrid organic-inorganic semiconductor elements. One class of flexible electronic devices that operate well is based on polycrystalline silicon thin film semiconductor elements made by annealing amorphous silicon thin films with pulsed laser. While such flexible electronic devices provide improved device electronic performance characteristics, the use of pulsed laser annealing processes limits the ease and flexibility of manufacturing such devices, thereby significantly increasing cost. Another promising, well-performing, new class of flexible electronic devices is those that employ solution processable nanoscale materials, such as nanowires (nanowires), nanoribbons (nanobubons), nanoparticles, and carbon nanotubes as the active functional components in many large electronic (macroelectronic) and microelectronic devices.
The use of discrete single crystal nanowires or nanoribbons has been evaluated as a possible approach to providing printable electronic devices on plastic substrates that exhibit improved device performance characteristics. Duan et al describe thin film transistor designs having multiple selectively oriented single crystal silicon nanowires or CdS nanoribbons as the semiconductor channels [ Duan, X.; Niu, C., Sahl, V., Chen, J., Parce, J., Empedocles, S. and Goldman, J., Nature, Vol.425, pp.274-278]. These authors report a fabrication method that is said to be compatible with solution processing methods on plastic substrates, which disperses monocrystalline silicon nanowires or CdS nanoribbons with a thickness of less than or equal to 150nm into a solution and assembles them onto the substrate surface using flow-directed alignment methods to produce thin film transistor semiconductor elements. The optical micrographs provided by the authors demonstrate that the disclosed fabrication method produces monolayers of nanowires or nanoribbons spaced from about 500 nanometers to about 1000 nanometers in a substantially parallel orientation. Although the authors report that individual nanowires or nanoribbons haveHigh intrinsic field effect mobility (about 119 cm)2V-1s-1) However, recently it has been determined that the field effect mobility of the entire device is "about two orders of magnitude lower" than the value of intrinsic field effect mobility reported by Duan et al [ Mitzi, D.B, Kosbar, L.L., Murray, C.E., Copel, M.Afzali, A., Nature, Vol.428, pp.299-303]. The field effect mobility of the device is orders of magnitude lower than that of conventional single crystal inorganic thin film transistors, and is likely due to the practical challenges in the alignment, close packing and electrical contact of discrete nanowires or nanotubes with the method and device configuration disclosed by Duan et al.
The use of nanocrystal solutions as precursors for polycrystalline inorganic semiconductor thin films has been explored as a possible approach to providing printable electronic devices on plastic substrates that exhibit superior device performance characteristics. Ridley et al disclose a solution processing fabrication process that processes a solution of cadmium selenide nanocrystals having a size of about 2 nanometers at a temperature compatible with plastics to provide a semiconductor component for a field effect transistor. The authors report a method in which the growth of low temperature grains in a cadmium selenide nanocrystal solution provides a single crystal region containing hundreds of nanocrystals. Although Ridley et al reported improved electrical characteristics over similar devices with organic semiconductor elements, the device mobility (≈ 1 cm) achieved by these techniques2V-1s-1) The field effect mobility of the device is several orders of magnitude lower than that of the conventional single crystal inorganic thin film transistor. The limitations on field effect mobility achieved by the device configuration and fabrication methods of Ridley et al are likely due to the electrical contact established between the individual nanoparticles. The use of organic end groups to stabilize the nanocrystal solution and prevent aggregation (aggregation) may prevent the establishment of good electrical contact between adjacent nanoparticles, which is necessary to provide high field effect mobility of the device.
Although Duan et al and Ridley et al provide methods for fabricating thin film transistors on plastic substrates, the device configurations described employ transistors that contain mechanically rigid device components, such as electrodes, semiconductors, and/or insulators. The selection of plastic substrates with good mechanical properties allows the electronic device to operate in a flexed or deformed orientation. However, such action is expected to produce mechanical strain on the individual rigid transistor device components. Such mechanical strain may cause damage to the individual components by, for example, causing them to crack, and may also reduce or destroy electrical contact between the device components.
From the foregoing it will be appreciated that there is a need in the art for methods and device configurations for fabricating devices containing integrated electronic semiconductors on plastic substrates. There is a need for printable semiconductor elements with good electrical characteristics to enable efficient device fabrication at temperatures compatible with components on plastic polymer substrates. In addition, there is a need for a method of printing semiconductor material onto large area plastic substrates to enable continuous, high speed printing of complex integrated circuits over large substrate areas. Finally, there is a need for fully flexible electronic devices with good electronic performance in flexed or deformed device orientations to achieve a variety of new flexible electronic devices.
Disclosure of Invention
The present invention provides methods, apparatus and apparatus components for fabricating structures and/or devices, such as electronic devices containing semiconductors, on a substrate surface, such as a plastic substrate. In particular, the present invention provides printable semiconductor elements for the manufacture of electronic devices, optoelectronic devices and other functional electronic components by flexible, low-cost printing methods. It is an object of the present invention to provide a method and apparatus for manufacturing a semiconductor component, such as a bulk (unity) single crystal inorganic semiconductor having selected physical dimensions in the range of about 10 nanometers to about 10 centimeters, capable of high precision assembly on a substrate surface through a series of printing techniques. It is another object of the present invention to provide a method of assembling and/or patterning printable semiconductor elements using dry transfer contact printing and/or solution printing techniques that provides good placement accuracy and pattern fidelity over a large substrate area. It is a further object of the present invention to provide integrated electronic and/or optoelectronic devices of good electronic performance, particularly fully flexible thin film transistors with printable semiconductor elements, exhibiting good electronic performance characteristics, such as field effect mobility, threshold voltage and on-off ratio, comprising one or more printable semiconductor elements supported by a plastic substrate.
In one aspect, the present invention provides a method of manufacturing a high performance electronic and/or optoelectronic device or device component having one or more printable components, such as printable semiconductor elements. Electronic and optoelectronic devices that can be fabricated by the methods of the present invention include, but are not limited to, transistors, diodes, Light Emitting Diodes (LEDs), lasers, Organic Light Emitting Diodes (OLEDs), micro-electromechanical systems (MEMS), and nano-electromechanical systems (NEMS). In particular, the present invention provides methods for assembling semiconductor elements and/or other device components into electronic and/or optoelectronic devices or device components by printing techniques that exhibit performance characteristics comparable to single crystal semiconductor-based devices fabricated by conventional high temperature processing methods.
In one embodiment of the present invention that may be used for device fabrication on substrates having low melting or decomposition temperatures, such as plastic and semiconductor substrates, the method of the present invention comprises the following independently executable fabrication steps: (1) forming one or more discrete high quality semiconductor elements; and (2) assembling and/or patterning these semiconductor elements and other device components on the surface of the substrate. For example, the present invention includes methods for producing free-standing, high quality printable inorganic semiconductors by masking and etching bulk single crystalline inorganic semiconductor materials produced by conventional high temperature processing methods such as high temperature (> 1000 ℃) thin film growth, doping, and other processing techniques. Such printable inorganic semiconductors are assembled, after fabrication, onto one or more substrate surfaces by printing techniques that can be performed at lower temperatures (< about 400 ℃). One advantage of having independently executable preparation and patterning/assembly steps is that each step can be performed at ambient conditions, such as room temperature, and at an environmental contamination level (i.e., if clean room conditions are required), which optimizes the efficiency, flexibility, and utility of each independently executable manufacturing step. For example, the method of the present invention enables the manufacture of semiconductor materials at the high temperatures required to produce high quality single crystal semiconductors. However, patterning and/or assembly of the semiconductor elements may then be carried out at significantly reduced temperatures which is advantageous for manufacturing devices on substrates having low melting or decomposition temperatures, such as plastic substrates. High performance devices can be fabricated on a wide range of substrate surfaces in the manner described above without significantly melting, decomposing or damaging the substrate surface. Another advantage of separating semiconductor fabrication from semiconductor/device assembly is that semiconductor components can be integrated into high performance devices and device assemblies through various flexible, low cost assembly methods, such as dry transfer and solution printing techniques, that do not require clean room conditions and are compatible with continuous, high speed device fabrication methods on large area substrates. In this respect, the method of the invention is compatible with printing on substrates comprising virtually any material, including plastic and non-plastic substrates, such as semiconductor wafers, e.g., silicon wafers or GaAs wafers.
In another aspect, the present invention provides printable semiconductor elements for integration into high performance electronic and optoelectronic devices and device components. For the purposes of the present invention, the term "printable" refers to materials, structures, device components and/or integrated functional devices that can be transferred, assembled, patterned, organized (organized) and/or integrated onto or into a substrate without exposing the substrate to high temperatures (i.e., at less than or equal to about 400 ℃). Printable semiconductors of the present invention may include semiconductor structures that can be assembled and/or integrated onto a substrate surface by dry contact transfer and/or solution printing methods. Exemplary semiconductor elements of the invention may be made by "top down" processing a series of inorganic semiconductor materials, including but not limited to single crystal silicon wafers, silicon on insulator wafers, polycrystalline silicon wafers, and GaAs wafers. Printable semiconductor elements made from high quality semiconductor wafers, such as those produced using conventional high temperature vapor deposition processing techniques, are beneficial for applications requiring good electronic performance because these materials have better purity and degree of crystallinity than materials made using "bottom up" processing techniques, such as conventional techniques for producing nanocrystals and nanowires. Another advantage provided by the "top-down" processing method of the present invention is that printable semiconductor elements and arrays of printable semiconductor elements can be fabricated in well-defined orientations and patterns, unlike the "bottom-up" processing methods commonly used to fabricate nanowires and nanoparticles. For example, semiconductor elements may be fabricated into arrays, such as transistor arrays or diode arrays, having locations and spatial orientations that directly correspond to the final locations and spatial orientations of the elements in a functional device or an array of functional devices.
Printable semiconductor elements may include single crystal inorganic semiconductor monolithic structures having various shapes, such as ribbon (or strip), disk, platelet, block, pillar, cylinder, or any combination of these shapes. Printable semiconductor elements of the present invention may have a variety of physical dimensions, for example, a thickness in the range of about 10 nanometers to about 100 micrometers, a width in the range of about 50 nanometers to about 1 millimeter, and a length in the range of about 1 micrometer to about 1 millimeter. For some applications, it is preferred to use semiconductor elements having a thickness greater than about 10 nanometers and a width greater than about 500 nanometers, since these dimensions can enable electronic devices to exhibit good electronic performance, such as device field effect mobility of greater than or equal to about 100cm for thin film transistors2V-1s-1Preferably greater than or equal to about 300cm2V-1s-1More preferably greater than or equal to about 800cm2V-1s-1. In addition to this, the present invention is,semiconductor components having widths greater than about 10 nanometers can be assembled onto a substrate with good placement accuracy and pattern fidelity by a range of printing techniques.
The printable semiconductor element of the present invention may also have an alignment-retaining element that connects the printable semiconductor element with a master (e.g., a semiconductor wafer). The alignment-retaining elements may be used to maintain a selected orientation and/or position of the printable semiconductor elements during transfer, assembly, and/or integration operation steps. The alignment-retaining elements may also be used to maintain the relative positions and orientations of the plurality of semiconductor elements forming the selected pattern of semiconductor elements during the transfer, assembly and/or integration operation steps. In the method of the present invention, the alignment-retaining elements maintain a selected position and orientation during contact (and attachment) of the printable semiconductor element to the contact surface of the adaptable transfer device. The alignment-retaining element used in this aspect of the invention can be removed (disengageable) from the printable semiconductor element after moving the adaptable transfer device without significantly changing the selected position and orientation of the printable semiconductor element. The discharging is generally achieved by breaking or disengaging the arrangement holding member during the movement of the transfer apparatus.
In one embodiment of the present invention, the printable semiconductor element has a peanut-like shape characterized by wider ends and narrower central regions. In this embodiment, the alignment-retaining member is obtained by performing an incomplete isotropic etching (isotropic etching) below the wider end portion and performing a complete isotropic etching below the central region. The processing method forms semiconductor elements connected to the master at two points corresponding to respective ends of the semiconductor elements. In another embodiment, the printable semiconductor element has a ribbon shape extending along a central longitudinal axis. In this embodiment, the arrangement holding member connects both ends of the ribbon in the axial direction to the master. In various embodiments, the bonding of the tape-like or peanut-like semiconductor elements to the transfer device contact surface and the movement of the transfer device causes both alignment-maintaining elements to break and release the printable semiconductor elements from the master.
The printable semiconductor elements of the present invention have independently selectable physical dimensions such as width, height, thickness, surface roughness and flatness, which can be selected with high accuracy. In an exemplary embodiment, the physical dimensions of the printable semiconductor elements may be selected with an error of less than about 5%. A large number of printable semiconductor elements having highly uniform selected physical dimensions can be fabricated using the method of the present invention. In one exemplary embodiment, a large number of printable semiconductor elements can be fabricated with physical dimension variations of less than about 1%. Thus, unlike conventional methods of producing nanowires, the present invention provides printable semiconductor elements without significant size and shape distributions. An important advantage of this method is that the structures and devices incorporating the printable semiconductor elements of the present invention need not be made to tolerate a dispersion in the size and shape of the semiconductor elements. In certain embodiments, the printable semiconductor elements of the present invention have very low surface roughness, e.g., the root mean square value of the surface roughness is less than about 0.5 nanometers. Printable semiconductor elements of the present invention may have one or more planar surfaces. Such a configuration may be beneficial in certain device manufacturing applications because the planar surface may be used to establish an interface with other device components, such as conductor, semiconductor and/or dielectric device components.
In addition, the present methods and compositions of matter (compositions) provide printable semiconductor elements containing high quality semiconductor materials. In certain embodiments for the manufacture of high performance electronic devices, the printable semiconductor elements are about 1000 times or less pure than conventional semiconductor wafer materials made by high temperature processing techniques. For example, the present invention provides high purity semiconductor components in which the oxygen impurities are less than about 5 to 25ppm atomic, the carbon impurities are less than about 1 to 5ppm atomic, and the heavy metal impurities are less than or equal to about 1ppm atomic (ppma), preferably less than or equal to about 100ppba (parts perbllion atoms) for some applications, and more preferably less than or equal to about 1ppba for some applications. Printable semiconductor elements having low levels of heavy metal impurities (e.g., less than about 1 ppma) are beneficial for applications and devices requiring good electronic performance, because the presence of heavy metals in the semiconductor material can severely degrade its electrical performance.
In addition, the printable semiconductor elements of certain aspects of the present invention have very low resistivity gradients, e.g., less than about 5% to 10% variation in their area. This aspect of the invention provides for improved doping uniformity relative to conventional semiconductor materials, such as nanowires and nanocrystalline materials, made by "bottom-up" processing techniques. Furthermore, the printable semiconductor elements of the present invention may contain semiconductor materials that exhibit few dislocations, for example less than 500 dislocations per square centimeter. For device manufacturing applications requiring good electronic performance, it is beneficial to use semiconductor components containing high quality semiconductor materials.
In addition, the methods and compositions of matter of the present invention provide printable semiconductor elements that are highly uniform in composition. In this specification, compositional uniformity refers to the uniformity between devices (piece-to-piece) in terms of purity, doping concentration, spatial distribution of dopants, and degree of crystallinity. The high purity and good consistency of composition of the printable semiconductor elements of the present invention provide functional devices with improved reliability relative to devices made from conventional semiconductor materials made by "bottom-up" processing techniques, such as nanowires and nanocrystalline materials.
The printable semiconductor elements of the present invention preferably have at least one smooth surface, such as the top or bottom surface of a micro tape, preferably exhibiting a deviation from the average surface position of less than 10 nanometers, and more preferably exhibiting a deviation from the average surface position of less than 1 angstrom for some applications. The smooth surface of the printable semiconductor elements of the present invention allow for the establishment of effective electrical contact and/or physical integration with other device components in an integrated electronic or optoelectronic device.
Alternatively, printable semiconductor elements of the present invention may comprise composite semiconductor elements having semiconductor structures operatively connected to one or more additional structures, including, for example, dielectric structures, conductive structures (e.g., electrodes), additional semiconductor structures, or any combination of these structures. Printable composite semiconductor elements provide materials and device components that can be easily and efficiently integrated into complex electronic or optoelectronic devices. In addition, the assembly methods of the present invention can cause printable semiconductor elements to form an array geometry in which adjacent elements are in close proximity to each other, e.g., within 100 nanometers to 1 micron of each other. For example, the printable semiconductor element of the present invention comprises a monolithic structure having a high quality semiconductor structure, such as a single crystalline inorganic semiconductor, operatively connected to an inorganic dielectric structure, such as a silicon dioxide layer. This embodiment of the invention is particularly useful for fabricating high performance thin film transistors because the semiconductor and dielectric components can be assembled in a single printing step and because the resulting insulator configuration using the overall structure containing the semiconductor and dielectric components exhibits very low leakage current from the gate electrode to the semiconductor element or source and drain electrodes. In another embodiment, the printable semiconductor elements of the present invention may contain integrated functional devices such as diodes, LEDs, transistors, and OLEDs that are readily incorporated onto the surface of the substrate.
The present methods and compositions provide a processing platform that enables the fabrication of functional devices that exhibit improved reliability compared to devices based on semiconductor materials, such as nanowires and nanocrystals, produced by "bottom-up" processing techniques. In this specification, reliability refers to the ability of a functional device to exhibit good electrical performance over a long period of operation, and to the consistency from device to device in terms of the electrical performance of the device as a whole made using the method and composition of the invention. For example, the devices of the present invention exhibit very consistent threshold voltages (e.g., standard deviation less than 0.08V) and very consistent device mobilities (e.g., standard deviation less than about 13%). This represents about a 40-fold and about an 8-fold improvement in the uniformity of threshold voltage and device mobility, respectively, over nanowire-based devices. The excellent reliability of the functional devices of the present invention results, at least in part, from the high degree of uniformity in composition and physical dimensions obtainable using the printable semiconductor elements of the present invention.
In another aspect, the present invention provides an electronic device comprising a first electrode, a second electrode, and a printable semiconductor element in electrical contact with the first and second electrodes. In one embodiment that may be used in applications requiring good electronic device performance, the printable semiconductor element comprises an inorganic semiconductor bulk structure having a physical size and shape that provides a fill factor between the first and second electrodes of greater than or equal to about 20%, preferably greater than or equal to about 50% for certain applications, and more preferably greater than or equal to about 80% for certain applications. Optionally, the electronic device of this embodiment may further comprise additional printable semiconductor elements, such as printable elements that are substantially longitudinally oriented, and may optionally be in no physical contact with each other. Importantly, the plurality of printable semiconductor elements of the present invention can be configured in a device or array of devices in a manner that has a large fill factor (e.g., greater than or equal to 20%, 50%, or 80%) and good electronic performance, unlike systems that include tightly packed nanowire arrays. In one embodiment, the printable semiconductor element has at least one cross-sectional dimension greater than or equal to about 500 nanometers. In one embodiment, the aspect ratio of the printable semiconductor element is equal to or less than about 10, preferably equal to or less than about 1.5 for certain applications. In one embodiment, the printable semiconductor element has a thickness to width ratio of equal to or less than about 0.1, preferably equal to or less than about 0.01 for certain applications.
This aspect of the invention also includes an array of electronic devices, such as transistors, diodes, photovoltaic devices, light emitting devices, comprising a first electrode, a second electrode, and a plurality of printable semiconductor elements in electrical contact with the first and second electrodes. In one embodiment, the array of electronic devices comprises more than 20 printable semiconductor elements, preferably more than 50 printable semiconductor elements for certain applications, and more preferably more than 100 printable semiconductor elements for certain applications. In one embodiment, which may be useful in applications requiring good electronic device performance, the printable semiconductor element provides a fill factor between the first and second electrodes of greater than or equal to about 20%, preferably greater than or equal to about 50% for some applications, and more preferably greater than or equal to about 80% for some applications. The printable semiconductor elements may be substantially longitudinally oriented with respect to a selected alignment axis, for example a selected alignment axis extending along an axis connecting the most adjacent points of said first and second electrical contacts. In one embodiment, the relative position and orientation of the printable semiconductor elements is selected to be within less than or equal to about 5 microns. In one embodiment for providing good end-to-end positioning of semiconductor elements, each of said printable semiconductor elements extends a length and terminates in a first end and a second end. In this embodiment, the first end of the printable semiconductor element is located within 5 microns of the first electrode and the second end of the printable semiconductor element is located within 5 microns of the second electrode. In one embodiment, the electronic device array of the present invention comprises a plurality of printable semiconductors in a configuration such that the plurality of printable semiconductors are in a substantially vertical orientation and are not in physical contact with each other (i.e., do not overlap) and are in electrical contact with the first and second electrodes. In one embodiment, the printable semiconductor elements in the array of electronic devices have at least one physical dimension, such as an average length, an average width, and/or an average thickness, that varies by less than about 10%, preferably less than about 5% for certain applications. In this embodiment, the printable semiconductor elements in the array have selected physical dimensions, such as average length, average width, and/or average thickness, that do not vary significantly (i.e., less than about 10%) from one another.
In another aspect, the present invention provides a transistor having a printable semiconductor element. In one embodiment, a transistor of the present invention includes a source electrode, a printable semiconductor element, a gain electrode, and a gate electrode. In this configuration, the source electrode and the gain electrode are both in electrical contact with and separated by the printable semiconductor element, while the gate electrode is separated from the printable semiconductor by the dielectric. The printable semiconductor element may comprise a crystalline inorganic semiconductor bulk structure having a thickness greater than or equal to about 50 nanometers, preferably greater than or equal to 100 nanometers for certain applications, and more preferably greater than or equal to 200 nanometers for certain applications. The invention also includes a transistor having a plurality of printable semiconductor elements in contact with source and drain electrodes. In certain applications, the use of multiple printable semiconductor elements in a single transistor may be beneficial because it may reduce the overall positional accuracy tolerance (tolerance) of various device components in a field effect transistor, such as the source, drain and gate electrodes and the dielectric. The present invention also includes embodiments wherein the printable semiconductor element is a stretchable semiconductor element. The use of one or more stretchable semiconductor elements in the transistor of the present invention is advantageous because it allows good device performance and mechanical strength in devices that are in flexion, extension or deformation.
In another embodiment, the invention provides a high performance transistor supported by and/or in contact with a plastic substrate, such as a polyimide, polycarbonate, or Mylar (Mylar) substrate. The transistor of this embodiment of the invention may have a printable semiconductor element comprising a single crystal inorganic semiconductor structure, such as silicon or germanium. The device configuration exhibits good device performance characteristics such as field effect mobility, threshold voltage, switching frequency (switching frequency) and on-off ratio. In one exemplary embodiment, a thin film transistor on a plastic substrate has a device field effect mobility comparable to that of a transistor having a semiconductor including a crystalline semiconductor made by a conventional high temperature processBulk elements, e.g. devices having field effect mobility greater than or equal to 300cm2V-1s-1More preferably 800cm or more2V-1s-1. In another embodiment, the present invention provides Si-MOS transistors with single-crystal silicon printable semiconductor elements capable of high-frequency operation, for example, operating at frequencies up to about 280 MHz.
In another embodiment, the present invention provides a complementary metal oxide semiconductor circuit comprising a printable semiconductor element. For example, a CMOS circuit is formed using a printable semiconductor element having a lightly doped region of N (or P) type between two highly doped regions of P (or N) type. This capability is particularly significant for applications requiring low power consumption, since CMOS technology has much less power consumption than NMOS technology. Also, CMOS technology has no static power consumption, and thus the technology is particularly suitable for battery-driven electronic systems. Finally, circuit designs using CMOS technology are generally more compact than circuit designs using any other semiconductor technology, and therefore more devices can be integrated per unit surface area.
In one embodiment, the dielectric and semiconductor components of the transistor of this aspect of the invention may comprise an integral composite printable semiconductor element. Alternatively, the dielectric, gate electrode and semiconductor element of the transistor of this aspect of the invention may comprise an integrally combined printable semiconductor element. For some applications it is preferred to use a combined printable semiconductor element with an integrated structure of semiconductor and insulator, since this gives very high quality dielectric-semiconductor interfaces in thin film transistors with low drain electrodes. In addition, the use of a combined printable semiconductor element having semiconductor and insulator integrated structures may also enable efficient assembly of device components without the need for a spin-on step to integrate the dielectric layer into the thin film transistor.
In another embodiment, the present invention provides a stretchable semiconductor element that can withstand significant strain without breaking. The stretchable semiconductor conductor elements of the present invention may exhibit good electronic performance even when subjected to significant strain, for example, greater than or equal to about 0.5%, preferably 1%, and more preferably 2%. For some applications, the stretchable semiconductor elements of the present invention are also preferably flexible and thus capable of significant elongation, flexing, bending or deformation along one or more axes. Flexible, stretchable semiconductors may also exhibit good electronic performance in flexed, stretched, contracted, flexed, and/or deformed states. The flexible, stretchable semiconductor elements of the present invention may be printable and may include composite semiconductor elements having semiconductor structures operatively connected to other device components, such as dielectrics, electrodes, and other semiconductors. The present invention includes a variety of electronic and/or optoelectronic devices having stretchable and/or flexible semiconductor elements, such as transistors, diodes, LEDs, OLEDs, lasers, micro-electromechanical devices, and nano-electromechanical devices.
The stretchable semiconductor elements of the present invention comprise a flexible substrate having a support surface and a printable semiconductor structure having a curved interior surface. In this embodiment, at least a portion of the curved inner surface of the semiconductor structure is bonded (bond) to the support surface of the flexible substrate. Exemplary semiconductor structures having curved inner surfaces that may be used with the present invention include buckling semiconductor structures. For purposes of this specification, "buckled semiconductor structure" refers to a semiconductor structure having a curved morphology resulting from an applied force. The buckled semiconductor structure may have one or more crumple zones. The buckled semiconductor structure may exist in a coiled or corrugated configuration. Semiconductor structures having curved inner surfaces, such as buckling semiconductor structures, may be bonded to a flexible substrate in a strained configuration, such as less than about 30%, less than about 10%, or less than 1%.
The curved inner surface of the stretchable semiconductor of the present invention may have any profile that provides stretchability or flexibility including, but not limited to, a profile characterized by at least one convex region, at least one concave region, or a combination of at least one convex region and at least one concave region. In one embodiment, the curved inner surface of the stretchable and/or flexible semiconductor element has a profile characterized as a substantially periodic wave or a substantially non-periodic wave. For purposes of this specification, periodic and non-periodic waves can be any two-dimensional or three-dimensional waveform, including, but not limited to, sine waves, square waves, Aries functions, gaussian waves, lorentz waves, or any combination thereof. For example, the stretchable semiconductor elements and flexible elements of the present invention comprise buckled semiconductor ribbons having curved inner surfaces with a substantially periodic wave profile characterized by extending along the length of the ribbon. The stretchable semiconductor element and the flexible element of this embodiment may expand or contract along a lengthwise axis of the tape and may bend or deform along one or more other axes.
The profile of the semiconductor structure in this embodiment of the invention may change when subjected to mechanical stress or when a force is applied to the semiconductor element. Thus, the ability of an exemplary semiconductor structure to change profile provides the ability to expand, contract, flex, deform, and/or bend without significant mechanical damage, breakage, or substantial degradation of electrical performance. The curved inner surface of the semiconductor structure may be joined to the support surface in a continuous manner (i.e., joined at substantially all points along the curved inner surface). Alternatively, the curved inner surface of the semiconductor structure may be joined to the support surface in a discontinuous manner, wherein the curved inner surface is joined to the support surface at selected points along the curved inner surface.
The invention also includes stretchable electronic devices and/or device components comprising printable semiconductor structures in combination with additional integrated device components such as electrical contacts, electrodes, conductive layers, dielectric layers, and additional semiconductor layers (e.g., doped layers, P-N junctions, etc.) each having curved interior surfaces supported by the support surface of the flexible substrate. The curved inner surface configuration of the additional integrated device component is such that it may exhibit good electronic performance even when subjected to significant strain, for example to maintain electrical conductivity or to maintain insulation from the semiconductor element in a stretched or flexed configuration. The additional integrated device components of this aspect of the invention may have a buckled configuration, such as the coiled or corrugated configuration described above, and may be manufactured using similar techniques as used to manufacture the stretchable semiconductor element. In one embodiment, for example, a plurality of stretchable device components including stretchable semiconductor elements are fabricated independently and subsequently interconnected. Alternatively, the semiconductor-containing device may be fabricated in a planar configuration and the resulting planar device subsequently processed to provide all or a portion of the device components with curved interior surfaces.
Printable semiconductor elements of the present invention may contain hetero semiconductor (heterosemiconductor) elements that exhibit improved properties, such as improved mechanical, electrical, magnetic and/or optical properties, that may be used in a variety of device environments and configurations. Hetero-semiconductors are multi-component structures containing a semiconductor in combination with one or more additives. For purposes of this specification, additives include elements, molecules and complexes, aggregates and particles thereof that are different from the semiconductor to which they are bound, such as additives having different chemical compositions and/or physical states (e.g., crystalline, semi-crystalline or amorphous). Additives useful in this aspect of the invention include other semiconducting materials, N-type and P-type dopants (e.g., arsenic, boron, and antimony), structural enhancers, dielectric materials, and conductive materials. The hetero semiconductor element of the present invention includes a structure having a spatially uniform composition, such as a uniformly doped semiconductor structure; also included are structures having spatially non-uniform composition, such as semiconductor structures containing dopants that vary in concentration with spatial location in one, two, or three dimensions (i.e., having a spatially non-uniform dopant distribution in the semiconductor element).
On the other hand, a hetero-semiconductor element includes a semiconductor structure with additional integrated functional device components, such as dielectric layers, electrodes, electrical contacts, doped contact layers, P-N junctions, additional semiconductor layers, and an integrated multi-layer stack for charge confinement (charge confinement). Additional integrated functional device components of this aspect of the invention include semiconductor-containing structures as well as non-semiconductor-containing structures. In one embodiment, the hetero-semiconductor element comprises a functional device such as a transistor, diode, or solar cell, or a multi-element functional device assembly that can be efficiently patterned, assembled, and/or interconnected onto a substrate material.
The use of printable heterogeneous semiconductor elements provides certain advantages to the fabrication method of the present invention. First, the "top-down" processing of the present invention enables virtually any type of semiconductor processing, such as spatially controlled doping, to be performed in a step separate from the subsequent fabrication steps of (i) determining the spatial dimensions of the semiconductor elements and (ii) assembling the semiconductor elements onto a substrate or into a functional device. The separation of semiconductor processing steps from the assembly and interconnection steps of devices and device components in the methods of the present invention allows the processing of semiconductor materials under a variety of conditions beneficial for the production of very high quality semiconductor-containing materials, including single crystal semiconductors having well-defined concentrations and spatial distributions of dopants in their doped regions, and integrated semiconductor multilayer stacks having high purity. For example, the separation of semiconductor processing from the assembly of device components enables semiconductor processing to be performed at high temperatures and with highly controlled impurity levels. Second, the use of heterogeneous semiconductor elements containing multiple integrated device components and/or functional devices facilitates efficient high-throughput printing of functional devices and arrays thereof in a manner that facilitates commercialization. For example, the device manufacturing method of the present invention using a hetero semiconductor element having a plurality of interconnected device components reduces the number of net manufacturing steps and/or reduces the cost involved in producing certain devices.
In another aspect, the present invention provides methods for assembling, placing, organizing, transferring, patterning and/or integrating printable semiconductor elements onto or into a substrate by a variety of printing methods, including dry contact transfer or solution printing techniques. The printing method of the present invention enables one or more semiconductor components to be integrated onto or into a substrate in a manner that does not substantially affect its electrical and/or mechanical properties. Also, the printing method of the present invention enables semiconductor components to be assembled onto or into selected regions of a substrate in a selected spatial orientation. Furthermore, the printing method of the present invention enables the integration of semiconductor elements and other device components onto and/or into a substrate in such a way that high performance electronic and optoelectronic devices are obtained by establishing good electrical conductivity between selected device components, good insulation between selected device components, and/or good spatial arrangement and relative positional relationship between device components.
In one embodiment of the invention, the semiconductor element is assembled to the substrate surface by a dry contact transfer process, such as soft lithographic micro-or nano-transfer. In one approach, one or more printable semiconductor elements are contacted with an adaptable transfer device having one or more contact surfaces. Contact established between the contact surface and the printable semiconductor element causes the semiconductor element to bond or connect to the contact surface. Optionally, a conformal contact is established between the contact surface and the printable semiconductor elements to facilitate bonding or connection of these elements. At least a portion of the semiconductor component disposed on the contact surface is then contacted with the receiving surface of the substrate. Optionally, the conformable transfer device also establishes conformal contact between the contact surface on which the semiconductor element is disposed and at least a portion of the receiving surface. The semiconductor element can be transferred to the receiving surface in response to separation of the contact surface of the transfer device from the semiconductor element, thereby assembling the semiconductor element to the receiving surface of the substrate. In one embodiment, preferably for device manufacturing applications, printable semiconductor elements are placed and/or integrated into selected regions of a substrate in a selected spatial orientation. Optionally, the transfer process is repeated multiple times to pattern a large area of the substrate receiving surface. In this embodiment, for each successive patterning step, a transfer stamp having printable semiconductor elements is brought into contact with different areas of a receiving substrate. In this way, a semiconductor element which can be produced from a single mother wafer (the heat wafer) is made available for patterning a very large area of the receiving surface.
One advantage of using dry contact transfer methods in the present invention is that the pattern of printable semiconductor elements can be transferred and assembled onto the substrate surface while maintaining the selected spatial orientation of the semiconductor elements — the spatial orientation defining the pattern. This aspect of the invention is particularly advantageous for applications in which a plurality of printable semiconductor elements are fabricated in well-defined locations and relative spatial orientations that directly correspond to a selected device configuration or device array configuration. The transfer method of the present invention is capable of transferring, placing and assembling printable semiconductor elements and/or functional devices containing printable semiconductor elements, including, but not limited to, transistors, optical waveguides, micro-electromechanical systems, nano-electromechanical systems, laser diodes, or fully formed circuits (fully formed circuits).
In another embodiment, the present invention provides a selective transfer and assembly method in which a portion, but not all, of the provided printable semiconductor is transferred and assembled onto or into a substrate. In this embodiment, the adaptable transfer device is capable of selectively bonding with the particular printable semiconductor element provided. For example, the conformable transfer device may have a selected three-dimensional raised pattern on its outer surface having recessed regions and raised features. In this embodiment, the recessed regions and raised features may be positioned such that only selected printable semiconductor elements are brought into contact with one or more contact surfaces of the raised pattern and subsequently transferred and assembled onto the substrate surface. Alternatively, the conformable transfer device may have a contact surface with one or more bonding regions having a selected pattern, e.g., chemically modified regions having hydroxyl groups extending from the contact surface and/or regions having one or more adhesive surface coatings. In this embodiment, only those semiconductor elements that are in contact with the bonding areas on the contact face are bonded to the transfer device and subsequently transferred and assembled onto the substrate surface. An advantage of the present selective transfer and assembly method is that a first pattern of printable semiconductor elements having a first set of location and spatial orientation features may be used to produce a second pattern of printable semiconductor elements different from the first pattern and having a second set of location and spatial orientation features corresponding to a selected device configuration or device array configuration.
Exemplary adaptable transfer devices of the present invention include dry transfer plates, such as elastomeric transfer plates or combinatorial multi-layer patterning devices. Adaptable transfer Devices useful in the present invention include Patterning Devices comprising multiple polymer layers, as described in U.S. patent application serial No.11/115,954, entitled Composite Patterning device for Soft Lithography, filed on 27.4.2005, U.S. patent and trademark office, which is incorporated herein by reference in its entirety. An exemplary patterning device useful in the methods of the present invention comprises a polymer layer having a low young's modulus, such as a poly (dimethylsiloxane) (PDMS) layer, preferably having a thickness selected from the range of about 1 micron to about 100 microns for certain applications. The use of a low modulus polymer layer is beneficial because it provides a transfer device that is capable of establishing good conformal contact with one or more printable semiconductor elements, particularly printable semiconductor elements having curved, rough, flat and/or contoured exposed (exposed) surfaces, and is capable of establishing good conformal contact with substrate surfaces having a variety of surface morphologies, such as curved, rough, flat, smooth and/or contoured substrate surfaces.
Optionally, the transfer device of the present invention may further comprise a second layer having an outer surface opposite the inner surface and having a high young's modulus, such as a high modulus polymer layer, a ceramic layer, a glass layer, or a metal layer. In this embodiment, the inner surface of the first polymer layer and the inner surface of the high modulus second layer are arranged such that a force applied to the outer surface of the high modulus second layer is transferred to the first polymer layer. The use of a high modulus second polymer layer (or backing layer) in the transfer apparatus of the present invention is beneficial because it provides the transfer apparatus with a net flexural rigidity that is sufficiently large to provide good bonding, transfer and assembly characteristics. For example, using a net flexural rigidity selected fromAbout 1X 10-7Nm to about 1X 10-5Nm range transfer devices minimize positional deviations of semiconductor components and/or other structures bonded to the contact surface after they establish conformal contact with the substrate surface. The use of a high modulus rigid backing layer is also advantageous for preventing degradation of the printable semiconductor element during transfer, for example by preventing cracking of the printable semiconductor layer. This feature results in a method and apparatus for assembling printable semiconductor elements with high placement accuracy and good pattern fidelity. The transfer device of the present invention may contain additional layers, including polymer layers, to facilitate handling and maintenance and to obtain good thermal performance, and to distribute the force applied to the transfer device evenly across the contact surface, as taught in U.S. patent application entitled Composite Patterning device for Soft Lithography, filed on 27.4.2005, application serial No.11/115,954, to the U.S. patent and trademark office, which is incorporated herein by reference in its entirety.
Another approach is to use the principle of "soft adhesion" (soft adhesion) to govern the transfer process. In this case, the viscoelasticity of the material of the upper surface of the transfer member causes a peeling force (i.e., a force that can lift the object from the surface) that depends on the peeling speed. At high peel speeds, even if the static surface energy of the transfer member is lower than the static surface energy of the substrate, the peel force can be large enough to remove objects from the substrate and transfer them to the transfer member. At low peel speeds, the peel force is lower. In certain embodiments, the objects are transferred from the transfer member to the substrate by contacting the transfer member supporting the array of objects against the final substrate and then slowly peeling the member. This method of the present invention using controlled stripping rates can be used in conjunction with other transfer methods described herein.
The transfer apparatus of the present invention may have a single continuous contact surface or a plurality of discontinuous contact surfaces. The contact surface of the transfer apparatus of the present invention may be defined by a selected three-dimensional raised pattern having recessed areas and raised features of selected physical dimensions. The contact surfaces useful in the present invention can be associated with the printable semiconductor element by van der waals forces, covalent bonds, adhesive layers, chemically modified regions (e.g., regions having hydroxyl groups on their surface), dipole-dipole forces, or combinations thereof.
Various methods may be used to facilitate transfer of the printable semiconductor element from the contact surface into or onto the substrate surface. In one exemplary embodiment, the difference in surface energy between the substrate surface and the contact surface facilitates transfer to the substrate surface. For example, transfer from a contact surface comprising a PDMS layer having a lower surface energy to a substrate surface having a higher surface energy, such as a polyimide, polycarbonate, or polyester film layer, may be effectively achieved. In addition, the plastic substrate surface can be softened or partially melted by heating before and/or during contact with the printable semiconductor element to be transferred, thereby forming a semiconductor element embedded in the substrate. The substrate is cooled and hardened before the contact surface is separated from the semiconductor element, which contributes to efficient transfer. Alternatively, the substrate surface may have one or more chemically modified regions that cause the substrate to exhibit a greater affinity for the semiconductor component. For example, the modified region may be covered or modified by one or more adhesion layers such that it is effectively covalently bonded, van der waals attractive, dipole-dipole forces, or a combination thereof, with the semiconductor element to facilitate efficient transfer and assembly. Alternatively, the partially polymerized polymer precursor may be contacted with a semiconductor element or other device component and subsequently polymerized to form a substrate having the semiconductor element embedded therein.
In one exemplary embodiment, printable semiconductor elements are fabricated with a thin release layer (release layer) coated on top, including, for example, a photoresist layer used as a photomask patterned on a substrate during the process of defining and fabricating the printable semiconductor elements. The contact surface of the conformable transfer device is brought into conformal contact with the coated surface of the printable semiconductor element. The release layer facilitates the coupling of the printable semiconductor element to the contact surface of the transfer device. The surface of the printable semiconductor element not coated with the release layer is then brought into contact with the receiving surface of the substrate. Next, the release layer is removed, for example by exposure to a suitable solvent, such as acetone, to separate the printable semiconductor element from the conformable transfer device. Optionally, the receiving surface may be coated with one or more adhesive layers to facilitate transfer of the printable semiconductor element.
In another embodiment of the present invention, the printable semiconductor element is assembled onto the substrate by solution printing. For purposes of this specification, the term "solution printing" is intended to refer to a process of dispersing one or more structures, such as printable semiconductor elements, into a carrier medium, such as a carrier fluid or solvent, and delivering it to selected regions of a substrate surface in a predetermined manner. In an exemplary solution printing process, the transfer of structures to selected areas of the substrate surface is achieved by a process that is independent of the morphology and/or physical characteristics of the substrate surface being patterned. In another embodiment, the printable semiconductor elements remain suspended in the solvent until the solvent evaporates, or until an applied force, such as an electrostatic force, a magnetic force, or a force provided by an acoustic wave, detaches the printable semiconductor elements from the solution and transfers them to selected regions of the substrate. This function can be achieved by selecting the appropriate physical dimensions and quality of the printable semiconductor element required to avoid premature deposition. It can thus be seen that the solution printing process of the present invention differs substantially from certain fluidic self-assembly processes in which elements suspended in a carrier medium fall out of solution due to gravity and into recessed areas of the substrate in a statistical manner.
The method of assembling the printable semiconductor element onto the receiving side of the substrate of the present invention comprises the step of dispersing the printable semiconductor element in a carrier medium to form a suspension containing the semiconductor element in the carrier medium. The semiconductor components are assembled onto the receiving surface by printing a suspension solution onto the receiving surface to transfer the semiconductor components onto the substrate. In this embodiment, solution printing may be accomplished by a variety of techniques known in the art, including, but not limited to, ink jet printing, thermal transfer printing, and screen printing. The solution printing process of the present invention may also employ self assembly adjustment techniques (self assembly alignment techniques). For example, in one embodiment, the arrangement, placement and positioning of printable semiconductor elements having patterned hydrophobic and hydrophilic groups is adjusted on a receiving surface having complementary patterned hydrophobic regions (e.g., methyl terminal surface groups) and hydrophilic regions (e.g., carboxylic acid terminal surface groups). The solution printing process of the present invention can also utilize capillary action of droplets containing dispersed printable semiconductor elements to achieve alignment, placement and positioning.
Optionally, a variety of methods may be used in the present invention to control the orientation, alignment, and selective deposition of semiconductor elements and/or other device components on the substrate surface. These methods enable the fabrication of complex integrated electronic and optoelectronic devices containing a plurality of interconnected device components having precisely specified relative positions and spatial orientations. For example, electrostatic, acoustic, and/or static magnetic forces may be utilized to help place semiconductor elements and other device components at particular locations on the substrate surface in a selected spatial orientation. Alternatively, the characteristics and/or composition of the substrate surface itself may be modified in selected areas to achieve precise placement of semiconductor elements and other device components. For example, selected regions of the substrate surface may be chemically modified to exhibit selective affinity for semiconductor elements. In addition, the electrical properties of the substrate surface can be modified, for example, by forming potential wells in specific surface regions to facilitate selective integration, orientation, and arrangement of printable semiconductor elements and other device components.
The printing process of the present invention has many advantages that are important for the fabrication of high performance electronic and/or optoelectronic devices. First, the printing method of the present invention is capable of transferring and assembling inorganic single crystal semiconductor structures without subjecting these structures to mechanical strains large enough to cause significant damage or degradation, such as damage due to cracking. Second, the printing method of the present invention enables one or more semiconductor components to be placed on selected areas of the substrate surface with a selected orientation and with good placement accuracy (i.e., with good spatial positioning with respect to selected areas of the receiving surface), preferably with a spatial deviation of less than or equal to 5 microns from the absolutely correct orientation and position on the substrate. Third, the printing method of the present invention can form a pattern with good fidelity to a selected spatial configuration, e.g., a spatial configuration corresponding to a functional device or an array of devices, that contains multiple semiconductor elements, other device elements, integrated functional devices, or any combination thereof. Fourth, the printing process of the present invention can be carried out at relatively low temperatures (i.e., temperatures below about 400℃.) and is therefore compatible with a wide variety of substrates, particularly plastic substrates. Finally, the printing process of the present invention provides a low cost approach to the fabrication of high performance electronic and/or optoelectronic devices, and does not require clean room conditions.
The compositions and associated methods of the present invention for assembling, placing, organizing, transferring, patterning and/or integrating printable semiconductor elements onto or into a substrate can be used to fabricate virtually any structure containing one or more semiconductor elements. These methods can be used in particular for the manufacture of complex integrated electronic or optoelectronic devices or device arrays, such as arrays of diodes, light emitting diodes, solar cells, transistors (FETs and bipolar transistors) and thin film transistors. The compositions and associated methods of the present invention may also be used to fabricate system-level integrated circuits, such as complementary logic circuits, in which a plurality of printable semiconductor elements are printed onto a substrate in a well-defined spatial orientation and interconnected to form a desired circuit design. In one embodiment of this aspect of the invention, printable N-type and P-type hetero-semiconductor elements having selected dopant concentrations and spatial distributions of dopants are assembled and interconnected to fabricate complex integrated circuits. In another embodiment, a plurality of printable semiconductor elements containing different semiconductor materials are printed onto the same substrate and interconnected to produce complex integrated circuits.
However, the assembly of the present inventionThe method is not limited to semiconductors. Rather, these methods are widely compatible with a variety of non-semiconductor materials. Materials that can be transferred and/or assembled by the methods of the present invention include, but are not limited to, insulating materials, such as SiO2(ii) a Connecting materials, such as conductors; optical elements such as active optical materials, passive optical materials, and fiber optic elements; materials for sensing and magnetic materials. Thus, the methods, devices, and device components of the present invention can be used to fabricate a variety of micro-and/or nano-scale structures and structural assemblies, such as microfluidic devices and structures, NEMS devices and arrays of NEMS devices, and MEMS devices and arrays of MEMS devices. In particular, the transfer and assembly method of the present invention can be used to produce complex three-dimensional structures, such as integrated circuits, by sequentially superimposing multiple printed layers.
The compositions of the present invention and associated methods of fabrication, assembly and interconnection are useful for fabricating devices, particularly semiconductor-based devices, on a wide variety of substrates over large areas. The benefits of the methods of the present invention are that they are compatible with device assembly at temperatures compatible with most flexible substrates, including polymeric materials such as thermoplastics, thermosets, reinforced polymeric materials, and composite polymeric materials. However, the method of the present invention is equally applicable to device fabrication on rigid and/or brittle substrates including ceramic materials, glass, dielectric materials, conductors, metals, and semiconductor materials. These methods have applicability to device fabrication on brittle materials because very little force is applied to the substrate using the printing method of the present invention. The compositions and methods of manufacture of the present invention are also compatible with performing device manufacturing on a variety of less common substrate materials, such as paper, wood and rubber, as well as contoured substrates, including curved substrates, curved rigid substrates, concave substrates, and convex substrates. For example, the inventive method enables assembly and integration of printable semiconductor elements and other device components (e.g., electrodes, dielectric layers, P-N junctions, etc.) onto substrates having radii of curvature in the range of about 10 microns to about 10 meters, including rigid and flexible substrates.
On the other hand, the manufacturing method of the present invention enables heterogeneous integration (heterointegration) of printable semiconductor components into functional substrates. For example, the printing methods of the present invention enable printable semiconductor elements to be deposited and integrated into substrates having well-defined semiconductor regions, conductor regions, and/or insulating regions. One advantage of the inventive fabrication method is that printable semiconductor elements can be printed onto functional substrates, such as integrated circuits or components of integrated circuits, in selected orientations and positions with high placement accuracy, particularly for the inventive dry contact transfer method.
The printable semiconductor elements of the present invention may be made from a variety of materials. Useful precursor materials for the fabrication of semiconductor devices include semiconductor wafer sources, which in turn include bulk semiconductor wafers, such as single crystal silicon wafers, polycrystalline silicon wafers, germanium wafers; ultra-thin semiconductor wafers, such as ultra-thin silicon wafers; doped semiconductor wafers, e.g. P-type or N-type doped wafers, and wafers with a selected spatial distribution of dopants (semiconductor on insulator wafer, e.g. silicon on insulator (e.g. Si-SiO)2SiGe)); and semiconductors on substrate wafers, such as silicon on substrate wafers and silicon on insulators. Furthermore, the printable semiconductor elements of the present invention may be made from waste material left over from semiconductor device processing using conventional methods or unused high quality semiconductor material or reprocessed semiconductor material. In addition, the printable semiconductor elements of the present invention can be made from a variety of amorphous sheet sources including, for example, those deposited on sacrificial layers or substrates (e.g., SiN or SiO)2) Thin films of amorphous, polycrystalline and single crystal semiconductor materials (e.g., polysilicon, amorphous silicon, poly GaAs and amorphous GaAs) on and subsequently annealed.
The invention also includes methods of making printable semiconductor elements and flexible semiconductor elements. These methods enable the fabrication of printable semiconductor elements as well as flexible semiconductor elements from a variety of precursor materials such as silicon on insulator wafers, single crystal silicon wafers, polycrystalline silicon thin films, ultra-thin silicon wafers, and germanium wafers. In addition, these methods enable the production of printable semiconductor elements having a variety of shapes and physical dimensions. Furthermore, the inventive method enables low cost manufacturing of large arrays/patterns of printable semiconductor elements in a well-defined relative spatial orientation.
In another aspect, the present invention provides a method of assembling a printable semiconductor element onto a receiving side of a substrate, comprising the steps of: (1) providing a printable semiconductor element comprising an inorganic semiconductor bulk structure; (2) contacting a printable semiconductor element with an adaptable transfer device having a contact surface, wherein contact between the contact surface and the printable semiconductor element bonds or connects the printable semiconductor element to the contact surface, thereby forming a contact surface on which the printable semiconductor element is disposed; (3) contacting the printable semiconductor element disposed on the contact surface with the receiving surface of the substrate; and (4) separating the contact surface of the adaptable transfer device from the printable semiconductor element, wherein the printable semiconductor element is transferred to the receiving surface, thereby assembling the printable semiconductor element to the receiving surface of the substrate. In one embodiment, the method of the present invention further comprises the steps of: (1) providing additional printable semiconductor elements each comprising an inorganic semiconductor bulk structure; (2) contacting a printable semiconductor element with an adaptable transfer device having a contact surface, wherein contact between the contact surface and the printable semiconductor element bonds or connects the printable semiconductor element to the contact surface and forms the contact surface on which the printable semiconductor element is disposed, the relative orientation of the printable semiconductor elements forming a selected pattern; (3) contacting the printable semiconductor element disposed on the contact surface with the receiving surface of the substrate; and (4) separating the contact surface of the adaptable transfer device from the printable semiconductor element, wherein the printable semiconductor element is transferred to the receiving surface in a relative orientation that forms the selected pattern.
In another aspect, the present invention provides a method of assembling a printable semiconductor element onto a receiving surface of a substrate, comprising the steps of: (1) providing a printable semiconductor element comprising an inorganic semiconductor bulk structure, wherein the printable semiconductor element has at least one cross-sectional dimension greater than or equal to about 500 nanometers; (2) dispersing the semiconductor element in a solvent to form a suspension containing the semiconductor element in the solvent; and (3) assembling the semiconductor component onto the receiving surface by printing the suspension solution onto the receiving surface to transfer the semiconductor component onto the substrate. In one embodiment, the method of the present invention further comprises the steps of: (1) providing additional printable semiconductor elements, wherein each additional printable semiconductor element has at least one cross-sectional dimension greater than or equal to about 500 nanometers; (2) dispersing the semiconductor element in a solvent to form a suspension containing the semiconductor element in the solvent; and (3) assembling the semiconductor component onto the receiving surface by printing the suspension solution onto the receiving surface to transfer the semiconductor component onto the substrate.
In another aspect, the present invention provides a method of manufacturing a printable semiconductor element comprising the steps of: (1) providing a wafer having an outer surface, the wafer containing an inorganic semiconductor; (2) masking selected areas of the outer surface by applying a mask; (3) etching (optionally anisotropic etching) the outer surface of the wafer to form raised structures and at least one exposed wafer surface on the wafer, wherein the raised structures have masked sides and one or more unmasked sides; (4) applying a mask to at least a portion of the unmasked side of the raised structure; and (5) at least partially etching the exposed surface of the wafer, thereby releasing a portion of the raised structures from the wafer and fabricating the printable semiconductor element. In this embodiment, the mask may be applied to the unmasked sides of the raised structures by an oblique deposition process, such as sputtering or vapor deposition, or by flowing a portion of the mask on the outer surface onto the unmasked sides.
In another aspect, the present invention provides a method of making a printable semiconductor element: the method comprises the following steps: (1) providing a wafer having an outer surface, the wafer containing a semiconductor; (2) masking selected areas of the outer surface by applying a first mask; (3) etching (optionally anisotropically) the outer surface of the wafer to form a plurality of raised structures; (4) annealing the wafer to form an annealed external surface; (5) masking selected areas of the annealed outer surface by applying a second mask; and (6) etching (optionally anisotropically) the annealed outer surface to form the semiconductor element.
In another aspect, the present invention provides a method of manufacturing a printable semiconductor element comprising the steps of: (1) providing an ultra-thin wafer having an outer surface, the wafer containing a semiconductor and having a selected thickness along an axis perpendicular to the outer surface; (2) masking selected areas of the outer surface by applying a mask; (3) the outer surface of the wafer is etched (optionally anisotropically), wherein the wafer is etched through its thickness along an axis perpendicular to the outer surface, thereby forming printable semiconductor elements.
In another aspect, the present invention provides a method of manufacturing a flexible semiconductor element, including the steps of: (1) providing a printable semiconductor structure having an inner surface; (2) providing a pre-strained elastomeric substrate in an expanded state, wherein the elastomeric substrate has an outer surface; and (3) bonding an inner surface of the printable semiconductor structure to an outer surface of the pre-strained elastic substrate in the expanded state; and relaxing the flexible substrate at least partially to a relaxed state, wherein the relaxation of the flexible substrate causes the inner surface of the printable semiconductor structure to bend, thereby forming a semiconductor element having a curved inner surface. In one exemplary embodiment, the pre-strained elastomeric substrate expands along a first axis, a second axis perpendicular to the first axis, or both. The pre-strained elastic substrate in the expanded state may be formed by bending the elastic substrate or rolling the elastic substrate. Optionally, the method of this aspect of the invention may further comprise the step of transferring the semiconductor having a curved inner surface to a flexible receiving substrate.
In another aspect, the present invention provides a method of manufacturing a printable semiconductor element attached to a mother wafer by one or more alignment-retaining elements, the method comprising the steps of: (1) providing a mother wafer having an outer surface, the wafer containing an inorganic semiconductor material; (2) masking selected areas of the outer surface by applying a mask; (3) etching the outer surface of the wafer to form raised structures and at least one exposed surface on the wafer, wherein the raised structures have a masked side and one or more unmasked sides; (4) etching the exposed surface of the wafer; and (5) stopping the etching of the exposed structures to prevent complete detachment of the raised structures, thereby producing printable semiconductor elements connected to the mother wafer by one or more alignment-maintaining elements. In one embodiment of the method, the printable semiconductor element is peanut-shaped having a first end and a second end, wherein the alignment-retaining element connects the first and second ends of the printable semiconductor element to the mother wafer. In another embodiment of the method, the printable semiconductor element is in the form of a ribbon having a first end and a second end, wherein the alignment-retaining element connects the first and second ends of the printable semiconductor element to the mother wafer.
Drawings
FIG. 1 schematically illustrates one exemplary method of the present invention for producing and assembling printable semiconductor elements comprising single crystal silicon ribbons.
FIG. 2 provides a schematic illustration of a selective dry contact transfer method for assembling printable semiconductor elements onto a receiving side of a substrate.
Fig. 3A-C are schematic diagrams showing equipment, equipment configurations, and equipment components that may be used in the selective dry contact transfer method of the present invention. Figure 3D provides a photograph of a photodiode array printed onto the spherical surface of a polycarbonate lens (FL 100 mm). Figure 3E provides a scanning electron micrograph of a photodiode array printed onto the curved face of a spherical glass lens (FL 1000 mm). The contrast in the image provided in fig. 3E is slightly enhanced to show the p-doped region. Fig. 3F provides a current (μ a) versus bias (volts) curve illustrating the photo response of the photodiode shown in fig. 3E.
FIGS. 4A1 and 4A2 illustrate preferred shapes of printable semiconductor elements for use in the assembly method of the present invention using dry contact transfer. Fig. 4a1 provides a perspective view and fig. 4a2 provides a top view. FIGS. 4B1 and 4B2 show preferred shapes of printable semiconductor elements for use in the assembly method of the present invention using dry contact transfer. Fig. 4B1 provides a perspective view and fig. 4B2 provides a top view.
Fig. 5A-C provide optical and scanning electron micrographs of various printable semiconductor elements containing monocrystalline silicon micro-bars (microsstrips) having selected physical dimensions.
FIG. 6 provides an image of a transferred printable semiconductor element containing single crystal silicon micro-stripes on a PDMS coated polyimide sheet.
Figure 7 provides an optical microscope image of a thin film transistor having printable semiconductor elements.
Fig. 8 provides a graph showing the current-voltage (V) characteristics of devices fabricated on pre-oxidized Si wafers.
FIG. 9 provides at VDSCurves measured at 0.1V show the transmission characteristics of devices made on a mylar sheet grid (gate) coated with ITO and polymer dielectric.
FIGS. 10A-H provide schematic illustrations of a method of the present invention for fabricating a thin film transistor array having combined printable semiconductor elements.
Fig. 11A-D provide schematic illustrations of a method of the present invention for fabricating a printable device containing an integrated gate electrode, gate insulator, semiconductor, source and drain electrodes.
Fig. 12A-12C provide atomic force micrographs illustrating the tensile printable semiconductor element of the present invention.
Fig. 13A-13E show atomic force micrographs providing enlarged views of semiconductor structures having curved inner surfaces.
Fig. 14A-14C show atomic force micrographs of an array of tensile printable semiconductor elements of the present invention.
Figure 15 shows an optical micrograph of a tensile printable semiconductor element of the present invention.
Fig. 16A-16B show atomic force micrographs of a stretch printable semiconductor element of the present invention having a semiconductor structure bonded to a flexible substrate having a three-dimensional raised pattern on a supporting surface.
Figure 17 shows a flow chart illustrating an exemplary method of the present invention for fabricating a stretchable semiconductor element.
FIG. 18A illustrates an exemplary method of fabricating printable semiconductor elements from Si-Ge epi substrates.
FIG. 18B illustrates an exemplary method of fabricating printable semiconductor elements from bulk silicon substrates, preferably single crystal silicon substrates.
FIG. 18C illustrates another exemplary method for fabricating printable semiconductor elements from bulk silicon substrates, preferably single crystal silicon substrates.
FIG. 18D illustrates yet another exemplary method of fabricating printable semiconductor elements from bulk silicon substrates, preferably single crystal silicon substrates.
FIG. 18E illustrates an exemplary method of fabricating printable semiconductor elements from ultra-thin silicon substrates.
FIG. 18F illustrates an exemplary method of fabricating printable semiconductor elements from a polysilicon film on a supporting substrate.
FIG. 18G showsFrom SiO2Exemplary methods of fabricating printable semiconductor elements from polysilicon thin films on substrates.
FIGS. 18H (1) and 18H (2) illustrate a method of fabricating a single crystal semiconductor film using the printable semiconductor element of the present invention.
FIG. 18I illustrates an exemplary method of fabricating printable semiconductor elements containing microwires from GaAs substrates.
FIG. 18J illustrates an alternative method of fabricating printable semiconductor elements containing single crystal silicon ribbons.
FIG. 18K illustrates an alternative method of fabricating printable semiconductor elements containing single crystal silicon ribbons.
Fig. 19A-19B provide schematic diagrams illustrating steps of an exemplary method of forming and transferring GaAs nanowire arrays onto a substrate, including, for example, a plastic substrate comprising a poly (diethyl terephthalate) (PET) sheet coated with a thin layer of cured Polyurethane (PU).
FIG. 20A provides a scanning electron micrograph of unsupported GaAs lines made from GaAs wafers with isolated SiO2The lines are patterned.
FIGS. 20B-E show scanning electron micrographs of single lines obtained by etching a GaAs wafer with 2 μm wide SiO2The lines are patterned. FIG. 20F provides a graph showing the average width of the top surface of a wire made by the method of the present inventionGraph of etch time.
FIGS. 21A-G show images of arrays of various GaAs lines printed on PDMS and PU/PET substrates.
FIGS. 22A-C show scanning electron micrographs of arrays of InP wires on PDMS and PU/PET substrates.
Fig. 23A provides a schematic and image of an exemplary two-terminal diode device containing an array of GaAs wires. Fig. 23B shows the current-voltage (I-V) curves for the two-terminal diode device recorded at different bend radii, which indicates that the two-terminal diode device containing the GaAs wire array exhibited the expected diode characteristics. Fig. 23C shows the current-voltage (I-V) curves measured after the two-terminal diode device relaxes again after bending at different bend radii.
FIG. 24 provides a schematic diagram illustrating an exemplary method of solution printing printable semiconductor elements having manipulation elements that include magnetic tags (magnetic tags) in accordance with the present invention.
FIG. 25 provides several optical images showing the formation of an ordered array of microstructures containing printable semiconductor elements having manipulating elements comprising thin layers of nickel using the solution printing process of the present invention.
Fig. 26A illustrates steps for fabricating an exemplary bendable thin film transistor device of the present invention. Fig. 26B provides a schematic illustration of the bottom gate device configuration of the thin film transistor, and high magnification and low magnification optical images of a portion of the device array.
FIG. 27A provides the current-voltage characteristics of the bendable thin film transistor of the present invention evaluated using a standard field effect transistor model that ignores the contact effect, and the results indicate that the effective device mobility in the saturation region (saturation region) is 140cm2Per Vs, effective device mobility in Linear region (Linear region) of 260cm2Vs. Fig. 27B provides the transmission characteristics of several devices plotted on a linear scale (left axis) and a logarithmic scale (right axis). Fig. 27C shows the linear effective mobility distribution of several bendable thin film transistors fabricated by the method of the present invention.
Fig. 28A provides a high resolution scanning electron micrograph (left inset) of a solution cast tape illustrating the significant flexibility of printable single crystal silicon semiconductor elements. The right inset in fig. 28 shows a picture of an experimental setup used to bend the bendable thin film transistors evaluated in this study. Fig. 28B shows a small (< 1%) linear change in the capacitance of the epoxy insulator when subjected to tensile and compressive strains (see top inset). The bottom inset in fig. 28B provides the change in device saturation current measured at both gate and drain bias voltages of 4V.
FIG. 29A provides a schematic depiction of a fabrication method for producing transistors containing printable heterogeneous semiconductor elements on a PET substrate. FIG. 29B shows optical images of several devices having heterogeneous printable semiconductor elements fabricated using the techniques of the present invention.
FIG. 30A shows an arrangement of printable heterogeneous semiconductor elements and contact pads (see inset), R, for characterizing contact resistanceGeneral assemblyNormalized impedance curve of W as a function of L. Fig. 30B shows the results of time-of-flight secondary ion mass spectrometry (TOF-SIMS) measurements, which indicate that the use of patterned SOG as a diffusion barrier (see schematic in fig. 29A) confines dopants to a desired region in silicon. In the image shown in fig. 30B, bright red indicates a high phosphorus concentration.
Fig. 31A-D show measurements corresponding to transistors containing printable contact doped silicon semiconductor elements on an epoxy/ITO/PET substrate. Fig. 31A provides typical current-voltage characteristics of a single crystal silicon transistor with doped contacts on a PET substrate when L is7 μm and W is 200 μm. FIG. 31B provides the transfer curves (V) for devices with channel lengths from high to low of 97 μm, 72 μm, 47 μm, 22 μm, 7 μm and 2 μmd0.1V). The channel width was 200 microns in each case. FIG. 31C shows the width-normalized ON-state device impedance (R) at different gate voltagesonW) as a function of channel length L. The solid line represents a linear fit. The scaling results are consistent with contacts within this channel length range having a negligible effect on device performance. The inset in FIG. 31C shows the substrate conductance [ Δ (R) as determined by the inverse of the slope of the linear fit in FIG. 31ConW)/ΔL]-1Follow gridA change in voltage. Fig. 31D shows the effective mobility measured in linear segments as a function of channel length for devices with undoped (triangular) and doped (square) contacts.
FIG. 32A shows the value μ from the unbuckled state0effThe normalized effective device mobility varies with strain (or bend radius). FIG. 32B provides normalized effective mobility μ after hundreds of bend cycles (to a radius of 9.2 mm) to induce a compressive strain in the device of 0 to 0.98%eff/μ0eff。
FIG. 33 provides an example of a composite semiconductor structure containing gallium nitride microstructures directly bonded to a silicon wafer (100) fabricated using the hetero-integration method of the present invention.
Fig. 34A provides a process flow diagram schematically illustrating processing steps in a manufacturing route to produce solar cells containing printable P-N segments. Fig. 34B shows a schematic diagram of a solar cell device configuration produced by the fabrication approach shown in fig. 34A. Fig. 34C shows the response of the photodiode observed after irradiation of the solar cell device having the configuration shown in fig. 34B.
Figure 35A provides a process flow diagram schematically illustrating processing steps in an alternative fabrication approach to produce a semiconductor layer containing printable P-doped and N-doped. Fig. 35B shows a schematic diagram of a solar cell device produced using the fabrication approach shown in fig. 35A. Fig. 35C shows a top-view SEM image of the solar cell schematically depicted in fig. 35B. Fig. 35D provides a current-bias curve illustrating the photodiode response of the solar cell shown in fig. 35C. Fig. 35E shows current-bias curves for several different illumination intensities illustrating the photodiode response of the solar cell shown in fig. 35C.
Figure 36A shows a process flow diagram illustrating an exemplary method of producing a stretchable thin film transistor array. Figure 36B provides an optical micrograph of the stretchable thin film transistor array in a relaxed and stretched state.
FIG. 37A provides a schematic diagram showing the process of the present invention (method I) for patterning a μ s-Si element onto a plastic substrate. FIG. 37B provides a schematic diagram illustrating an alternative inventive process (process II) for patterning a μ s-Si element onto a plastic substrate.
FIG. 38A shows a design of a so-called peanut-like μ s-Si object for use in the method of the invention. The optical image inset in FIG. 38A shows optimized HF etch conditions where the buried oxide under the via is removed and the SiO of the sacrificial layer is removed2And part remains. Fig. 38B illustrates an example of losing this order when the Si object is over-etched in an HF solution. 38C, 38D, 38E, and 38F show a series of photomicrographs depicting the performance of each μ s-Si transfer step performed using method I.
FIGS. 39A and 39B provide optical images of the selective transfer of μ s-Si onto PU/PET sheets through a 3600PDMS stamp. Fig. 39C is an optical micrograph of a fragment of a Sylgard184 coated PET substrate to which μ s-Si has been chemically bonded and which will subsequently be transferred. The higher magnification image of μ s-Si transferred in this manner is shown in FIG. 39D.
Fig. 40A illustrates an exemplary device geometry for a device fabricated using peanut-like μ s-Si according to the transfer method using method I. FIG. 40B provides μ s-Si TFTs at multiple gate voltages (V)g-2.5V to 20V). FIG. 40C shows the voltage at constant source-drain voltage (V)sd1V), which indicates an effective mobility of 173cm2Vs. The inset in fig. 40C shows an optical micrograph of an actual device of the present invention.
Figure 41 provides a schematic flow chart of the steps involved in a method of fabricating a mus-gaasmsfet on a poly (diethyl terephthalate) (PET) substrate. The wires are made from standard (100) GaAs wafers by anisotropic chemical etching. Printing techniques using elastomeric stamps transfer these lines from the wafer to the plastic device substrate in a manner that preserves the spatial organization (i.e., ordered array). PR stands for photoresist.
Fig. 42A provides a schematic diagram showing a cross-section of a GaAs wire based MESFET geometry on a plastic substrate (PU/PET). The source/drain electrodes form ohmic contacts with the n-GaAs layer. FIG. 42B shows a representative image of two MESFETs based on GaAs lines on a plastic substrate fabricated according to the process flow diagram of FIG. 41, each using an array of 10 GaAs lines. FIG. 42C shows an image of a 2cm by 2cm PET sheet with hundreds of transistors, which clearly shows its flexibility.
FIGS. 43A, 43B and 43C provide results for a GaAs MESFET similar to the MESFET shown in FIG. 42B with a channel length of 50 μm and a gate length of 15 μm. Fig. 43A shows the current-voltage (between drain and source electrodes) curve for gate voltages between 0.5V and-2.0V (step size of 0.5V). FIG. 43B shows the effect at different VDSThe following measured transfer characteristics (i.e., I) of the GaAsMESFET of the present inventionDS-VGS). FIG. 43C shows a cross-sectional view at VDS4V hour pair (I)DS)1/2-VGSThe resulting transmission curve is plotted and clearly shows the linear relationship expected for MESFETs.
Fig. 44A and 44B show the current-voltage characteristics of the gate modulation of a GaAs wire-based MESFET on a flexible PET substrate in two cases: (A) before bending; (B) after bending to a bend radius of 8.4 mm. Fig. 44C shows the current-voltage characteristics of the gate modulation of a GaAs wire-based MESFET after relaxation of the flexed substrate to its flat, unflexed state. FIG. 44D shows the strain at V during three bending (with different surface strains)/relaxation cyclesDS4V and VGSWhen equal to 0V, IDSShows that these MESFETs remain intact after many flexion cycles that change the tensile strain of the device between 0% and 1.2%, without significant change in their performance: (<20％）。
Fig. 45 provides a schematic diagram illustrating an exemplary device configuration of the present invention for a P-type bottom gate thin film transistor on a plastic substrate.
Fig. 46 provides a schematic diagram illustrating an exemplary device configuration of the present invention for complementary logic gates on a plastic substrate.
Figure 47 provides a schematic diagram illustrating one exemplary device configuration of the present invention for a top-gate thin film transistor on a plastic substrate.
Detailed Description
Referring to the drawings, like numbers indicate like elements, and like numbers appearing in multiple figures refer to like elements. In addition, the following definitions apply hereinafter.
"printable" refers to materials, structures, device components, and/or integrated functional devices that can be transferred, assembled, patterned, organized, and/or integrated onto or into a substrate without exposing the substrate to high temperatures (i.e., at less than or equal to about 400 ℃). In one embodiment of the present invention, printable materials, structures, device components and devices can be transferred, assembled, patterned, organized and/or integrated onto or into substrates by solution printing or dry contact transfer.
"printable semiconductor elements" of the present invention include semiconductor structures that can be assembled and/or integrated onto a substrate surface by using, for example, dry contact transfer and/or solution printing methods. In one embodiment, the printable semiconductor element of the present invention is a single crystal, polycrystalline or microcrystalline inorganic semiconductor monolithic structure. For purposes of this specification, a unitary structure is a monolithic element having mechanically connected components. The semiconductor components of the present invention may be doped or undoped, may have a selected spatial distribution of dopants, and may be doped with a variety of different dopant materials, such as P-type and N-type dopants. The present invention includes a micro-structured printable semiconductor element having at least one cross-sectional dimension greater than or equal to about 1 micron, and a nano-structured printable semiconductor element having at least one cross-sectional dimension less than or equal to about 1 micron. Printable semiconductor elements useful in a variety of applications include those obtained by "top-down" processing of high purity bulk materials, such as high purity crystalline semiconductor wafers produced using conventional high temperature processing techniques. In one embodiment, the printable semiconductor elements of the present invention comprise composite structures having a semiconductor operably connected to at least one additional device component or structure, such as a conductive layer, a dielectric layer, an electrode, an additional semiconductor structure, or any combination thereof. In one embodiment, the printable semiconductor elements of the present invention comprise stretchable semiconductor elements and/or hetero-semiconductor elements.
"cross-sectional dimension" refers to a cross-sectional dimension of a device, device component, or material. The cross-sectional dimensions include width, thickness, radius, and diameter. For example, the strip-shaped printable semiconductor element is characterized by a length and two cross-sectional dimensions: namely thickness and width. For example, a cylindrical printable semiconductor element is characterized by length and cross-sectional dimension diameters (or radii).
"fill factor" refers to the percentage of area between two elements, such as first and second electrodes, that is occupied by material, elements, and/or device components. In one embodiment of the invention, the first and second electrodes are disposed in electrical contact with one or more printable semiconductor elements that provide a fill factor between the first and second electrodes of greater than or equal to 20%, preferably greater than or equal to 50% for certain applications, and more preferably greater than or equal to 80% for certain applications.
"supported by the substrate" refers to a structure that is at least partially present on the surface of the substrate, or at least partially present on one or more intermediate structures located between itself and the surface of the substrate. The term "supported by a substrate" may also refer to structures that are partially or fully embedded in the substrate.
"solution printing" is intended to refer to a process whereby one or more structures, such as printable semiconductor elements, are dispersed into a carrier medium and delivered to selected areas of a substrate surface in a predetermined (confined) manner. In an exemplary solution printing process, the transfer of structures to selected areas of the substrate surface is achieved by a method that is independent of the morphology and/or physical characteristics of the substrate surface being patterned. Solution printing processes useful in the present invention include, but are not limited to, ink jet printing processes, thermal transfer processes, and capillary action printing processes.
"substantially machine direction orientation" refers to an orientation in which: a set of elements, such as printable semiconductor elements, have their longitudinal axes oriented substantially parallel to a selected axis of alignment. For purposes of this definition, substantially parallel to the selected axis refers to an orientation that is within 10 degrees of an absolutely parallel orientation, more preferably within 5 degrees of an absolutely parallel orientation.
"stretchable" refers to the ability of a material, structure, device, or device component to be pulled taut without breaking. In an exemplary embodiment, a stretchable material, structure, device or device component can withstand a strain of greater than about 0.5% without breaking, with a strain of greater than about 1% without breaking being preferred for some applications, and a strain of greater than about 3% without breaking being more preferred for some applications.
The terms "flexible" and "bendable" are used synonymously in this specification and both refer to the ability of a material, structure, device or device component to deform to a bent shape without undergoing a deformation that causes significant strain, e.g., defines the point of failure of the material, structure, device or device component. In an exemplary embodiment, a flexible material, structure, device or device component can be deformed into a curved shape without inducing a strain of greater than or equal to about 5%, with greater than or equal to about 1% preferred for certain applications, and greater than or equal to about 0.5% more preferred for certain applications.
"semiconductor" refers to any material that is an insulator at very low temperatures, yet has significant electrical conductivity at temperatures of about 300K. In this specification, the term semiconductor is intended to be usedIs used in accordance with the use of this term in the field of microelectronics and electronics. Semiconductors that can be used in the present invention can include elemental semiconductors and compound semiconductors. Such as silicon, germanium, and diamond. The latter such as group iv compound semiconductors, e.g., SiC and SiGe; group III-V semiconductors such as AlSb, AlAs, Aln, AlP, BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN, and InP; III-V ternary semiconductor alloys, e.g. AlxGa1-xAs; II-VI semiconductors such as CsSe, CdS, CdTe, ZnO, ZnSe, ZnS, and ZnTe; I-VII semiconductor CuCl; group IV-VI semiconductors such as PbS, PbTe and SnS; layer semiconductors, e.g. PbI2、MoS2And GaSe; oxide semiconductors, e.g. CuO and Cu2And O. The term semiconductor includes both intrinsic semiconductors and extrinsic semiconductors that are doped with one or more selected materials, including semiconductors having p-type and n-type doped materials, to provide electrical properties that are beneficial for a given application or device. The term semiconductor includes composite materials containing mixtures of semiconductors and/or dopants. Specific semiconductor materials that may be used for certain applications of the present invention include, but are not limited to, Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InInInP, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP. Porous silicon semiconductor materials may be used for the application of the present invention in the field of sensors and luminescent materials, such as Light Emitting Diodes (LEDs) and solid state lasers. Impurities of a semiconductor material are atoms, elements, ions, and/or molecules other than the semiconductor material itself or any dopants introduced into the semiconductor material. Impurities are undesirable materials present in semiconductor materials that may adversely affect the electrical properties of the semiconductor material, including, but not limited to, oxygen, carbon, and metals (including heavy metals). Heavy metal impurities include, but are not limited to, elements between copper and lead on the periodic table, calcium, sodium, and all ions, compounds, and/or complexes thereof. Gold is a specific heavy metal impurity that significantly degrades the electrical performance of semiconductors.
"Plastic" refers to any synthetic or natural material or combination of materials that can be molded or formed, typically upon heating, and can harden into a desired shape. Exemplary plastics that may be used in the present apparatus and method include, but are not limited to, polymers, resins, and cellulose derivatives. In this specification, the term plastic is intended to include composite plastics comprising one or more plastics and one or more additives including, for example, structural reinforcing agents, fillers, fibers, plasticizers, stabilizers or additives which provide the desired chemical or physical properties.
"dielectric" and "dielectric material" are used synonymously in this specification and both refer to a substance that has a high resistance to the flow of electrical current. Useful dielectric materials include, but are not limited to, SiO2、Ta2O5、TiO2、ZrO2、Y2O3、SiN4STO, BST, PLZT, PMN, and PZT.
"polymer" refers to a molecule comprising a plurality of repeating chemical groups, commonly referred to as monomers. Polymers are generally characterized by high molecular weight. The polymers useful in the present invention may be organic or inorganic and may be in an amorphous, semi-amorphous (semi-amorphous), crystalline or partially crystalline state. The polymer may comprise monomers having the same chemical composition, or may comprise a plurality of monomers having different chemical compositions, such as copolymers. Crosslinked polymers having linked monomer chains are particularly useful for some applications of the present invention. Polymers that may be used in the methods, apparatus and apparatus components of the present invention include, but are not limited to, plastics, elastomers, thermoplastic elastomers, elastoplastics, thermosets, thermoplastics, and acrylates. Exemplary polymers include, but are not limited to, acetal polymers, biodegradable polymers, cellulosic polymers (cellulose polymers), fluoropolymers, nylons, polyacrylonitrile polymers, polyamide-imide polymers, polyimides, polyarylates, polybenzimidazoles, polybutylenes, polycarbonates, polyesters, polyetherimides, polyethylenes, ethylene copolymers and modified polyethylenes, polyketones, polymethylmethacrylate, polymethylpentene, polyphenylene oxide and polyphenylene sulfide, polyphthalamide, polypropylene, polyurethanes, styrene resins, sulfone-based resins, vinyl resins, or any combination thereof.
"elastomer" refers to a polymeric material that is capable of being stretched or deformed and capable of recovering its original shape without substantial permanent deformation. The elastomer is typically deformed substantially elastically. Exemplary elastomers useful in the present invention may include polymers, copolymers, composite materials, or mixtures of polymers and copolymers. An elastomeric layer refers to a layer comprising at least one elastomer. The elastomeric layer may also include a dopant or other non-elastomeric material. Elastomers useful in the present invention may include, but are not limited to, thermoplastic elastomers, styrenic materials, olefinic materials, polyolefins, polyurethane thermoplastic elastomers, polyamides, synthetic rubbers, PDMS, polybutadiene, polyisobutylene, poly (styrene-butadiene-styrene), polyurethanes, polychloroprene, and silicones.
The term "electromagnetic radiation" refers to both electric and magnetic field waves. Electromagnetic radiation that may be used in the methods of the present invention includes, but is not limited to, gamma rays, X-rays, ultraviolet light, visible light, infrared light, microwaves, radio waves, or any combination of these electromagnetic radiations.
"good electronic performance" and "high performance" are used synonymously in this specification and both refer to devices and device components having electronic properties, such as field effect mobility, threshold voltage and on-off ratio, that provide a desired function, such as electrical signal conversion and/or amplification. Exemplary printable semiconductor elements of the present invention having good electronic properties may have a thickness of greater than or equal to 100cm2V-1s-1Preferably greater than or equal to about 300cm for certain applications2V-1s-1. Exemplary transistors of the invention having good electronic performance can have greater than or equal to about 100cm2V-1s-1Preferably greater than or equal to about 300cm for some applications2V-1s-1And more preferably greater than or equal to about 800cm for some applications2V-1s-1. Exemplary transistors of the invention having good electronic performance may have a threshold voltage of less than about 5 volts and/or greater than about 1 x 104The on-off ratio of (c).
"Large area" refers to an area of greater than or equal to about 36 square inches, for example, the area of a substrate receiving surface used in device fabrication.
"device field effect mobility" refers to the field effect mobility of an electronic device, such as a transistor, calculated using data corresponding to the output current of the electronic device.
"conformal contact" refers to contact established between a surface, a coated surface, and/or a surface having a material deposited thereon, which can be used to transfer, assemble, organize, and integrate structures (e.g., printable semiconductor elements) onto a substrate surface. In one aspect, conformal contact involves macroscopic adaptation to the overall shape of one or more contact-facing substrate surfaces of a transfer device. Conformal contact, on the other hand, involves microscopic adaptation of one or more contact-facing substrate surfaces of an adaptable transfer device that results in intimate contact without voids. The term conformal contact is intended to be consistent with its use in the field of soft lithography. Conformal contact can be established between one or more exposed contact surfaces of the conformable transfer device and the substrate surface. Alternatively, conformal contact may be established between one or more coated contact surfaces of the conformable transfer device, including, for example, contact surfaces having transfer material, printable semiconductor elements, device components, and/or devices deposited thereon, and the substrate surface. Alternatively, conformal contact may be established between one or more exposed or coated contact surfaces of an adaptable transfer device and a substrate surface coated with a material, such as a transfer material, a solid photoresist, a pre-polymer layer, a liquid, a film, or a fluid.
"placement accuracy" refers to the ability of a transfer method or apparatus to transfer printable elements, such as printable semiconductor elements, to selected locations, either relative to the location of other device components, such as electrodes, or to selected areas of a receiving surface. By "good placement" accuracy is meant that the method and apparatus is capable of transferring the printable element to a selected position relative to another device or device component or to a selected region of the receiving surface that has a spatial deviation from an absolutely exact position of less than or equal to 50 microns, more preferably less than or equal to 20 microns for some applications, and even more preferably less than or equal to 5 microns for some applications. The present invention provides devices containing at least one printable element that is transferred with good placement accuracy.
"fidelity" refers to a measure of how good or bad a selected pattern of elements, such as a pattern of printable semiconductor elements, is transferred to a receiving surface of a substrate. Good fidelity refers to the transfer of a selected pattern of elements in which the relative position and orientation of the individual elements remains unchanged, e.g., the spatial deviation of an individual element from its position in the selected pattern in the transfer is less than or equal to 500 nanometers, more preferably less than or equal to 100 nanometers.
"Young's modulus" is a mechanical property of a material, device or layer, and refers to the ratio of stress to strain for a given substance. Young's modulus can be expressed as:
wherein E is Young's modulus, L0Is the equilibrium length,. DELTA.L is the change in length after application of the stress, F is the applied force, and A is the area of application of the force. Young's modulus can also be expressed by the Laume (Lame) constant by the following formula:
where λ and μ are Lame constants. High young's modulus (or "high modulus") and low young's modulus (or "low modulus") are relative descriptors of the magnitude of young's modulus for a given material, layer or device. In the present invention, the high Young's modulus is greater than the low Young's modulus, preferably greater than about 10 times in some applications, more preferably greater than about 100 times in other applications, and even more preferably greater than about 1000 times in still other applications.
In the following description, numerous specific details of the apparatus, apparatus components and methods of the present invention are set forth in order to provide a thorough explanation of the exact nature of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details.
The present invention provides methods and apparatus for fabricating printable semiconductor elements and assembling printable semiconductor elements onto a substrate surface. The present invention provides a variety of printable semiconductor elements, including single crystal inorganic semiconductors, composite semiconductor elements comprising semiconductor structures operatively connected to one or more other device components, and stretchable semiconductor elements. The method, apparatus and apparatus assembly of the present invention enable the production of high performance electronic and optoelectronic devices and device arrays, such as thin film transistors on flexible plastic substrates.
FIG. 1 diagrammatically illustrates an exemplary method of the present invention for producing and assembling printable semiconductor elements comprising single crystal silicon ribbons. The method first provides a thin layer of monocrystalline silicon 105, SiO2A buried layer 107 and a silicon-on-insulator (SOI) substrate 100 of a Si handle layer 108. Optionally, if there is a surface native oxide layer on the thin layer of monocrystalline silicon 105, the surface native oxide layer may be removed, for example, by exposing the surface of the SOI substrate 100 to dilute (1%) HF. After sufficient stripping of the native oxide layer, selected regions of the outer surface 110 of the SOI substrate 100 are masked, thereby forming a pattern 120 of mask elements on the outer surface 110, maskingA shaded region 125 and an exposed surface region 127. In the embodiment shown in fig. 1, the outer surface 110 is patterned with a rectangular Al/Au surface layer that provides mask elements 120 that prevent the masked regions 125 of the outer surface 110 from being etched. The mask elements 120 may have any size and shape including, but not limited to, square, rectangular, circular, oval, triangular, or any combination of these shapes. In an exemplary embodiment, the Al/Au layer providing the mask elements of the desired geometry is made using micro-contact printing, nano-contact printing techniques or photolithography and etching (TFA for Au; Cyantec etchant premixed with AL-11 for Al). The deposition of the mask elements containing the metal films can be carried out by means of an electron beam evaporator, for example Temescale BJD1800, for example by first depositing Al (20 nm; 0.1 nm/s) and then Au (100 nm; 1 nm/s).
The outer surface 110 of the SOI substrate 100 is anisotropically etched downward. Although material is selectively removed from the exposed surface region 127, the mask elements 120 prevent etching of the masked regions 125, forming a plurality of raised features 140 comprising single crystal silicon structures having slightly sloped sidewalls 141, as shown in fig. 1. In an exemplary embodiment where the raised features have sidewalls 141 with a thickness 147 of about 100 nanometers, the exposed surface regions 127 are exposed to tetramethylammonium hydroxide (TMAH) for about 3.5 minutes. In this embodiment, the etching step forms smooth sidewalls on the single crystal silicon raised features 140 with the Al/Au mask elements 120, preferably with less than 10 nanometers deviation from the average surface position. When, for example, concentrated (49%) HF is used to make the underlying SiO2When layer 107 is partially or fully isotropically etched away, raised features 140 may be peeled away from substrate 100. The peeling of the raised features 140 forms printable semiconductor elements 150 comprising discrete single crystal silicon structures having one surface covered by a masking element. The mask elements 120, i.e., the Al/Au layers in this example, may be removed or integrated directly into the final device structure, e.g., as source and drain electrodes in a thin film transistor. As shown in fig. 1, it can be transferred by dry contact transfer techniques (e.g., dry contact transferAs indicated by arrow 166) or by solution casting (as indicated by arrow 165) the printable semiconductor element 150 is assembled to the receiving surface 160 of the surface of a substrate, such as a plastic substrate. Both assembly methods can be performed at room temperature in the ambient environment, and therefore they are compatible with a variety of substrates, including low cost flexible plastic substrates.
Assembling the printable semiconductor element using dry contact transfer has the advantage that the known orientation and position of the printable semiconductor element can be used before it is peeled from the SOI substrate. In this case, the printable semiconductor element is moved from the SOI to (after etching away the SiO) using a process similar to the soft lithography transfer technique2Thereafter, but before stripping the silicon) at the desired location on the device substrate. In particular, an elastomeric transfer element can be adapted to lift an object from the SOI surface and transfer it to a desired substrate. Similarly, printable semiconductor elements can be directly transferred to thin plastic substrates by cold welding of gold using receiving pads defined on the target substrate surface.
In one exemplary method, at least a portion of the printable semiconductor element 150 is brought into conformal contact with the contact surface 170 of a conformable transfer device 175, such as an elastomeric transfer stamp, a polymer transfer device, or a composite polymer transfer device, thereby coupling at least a portion of the printable semiconductor element 150 to the contact surface 170. The printable semiconductor element 150 disposed on the contact surface 170 of the conformable transfer device 175 is preferably in contact with the receiving surface 160 of the substrate in a manner that establishes conformal contact between the contact surface 170 and the receiving surface 160 of the substrate. The contact surface is separated from the printable semiconductor element 150 in contact with the substrate receiving surface 160, thereby assembling the printable semiconductor element 150 to the receiving surface. This embodiment of the present invention enables the pattern of printable semiconductor elements to be formed on the receiving surface in a well-defined position and in a well-defined spatial orientation. In the embodiment shown in FIG. 1, the printable semiconductor element 150 may be operatively connected to a gold pad 162 on the substrate receiving surface 160.
FIG. 2 provides a schematic diagram illustrating a selective dry contact transfer method for assembling printable semiconductor elements onto a receiving side of a substrate. A plurality of printable semiconductor elements 300 are fabricated on a master 305 into a first pattern 310 of printable semiconductor elements 300, the first pattern 310 being characterized by a well-defined position and spatial orientation. A conformable transfer device 315 having a contact surface 320 is brought into conformal contact with at least a portion of the printable semiconductor element 300 on the master 305, the contact surface 320 having a plurality of discrete bonding regions 325. The binding regions 325 on the contact surface 320 may be characterized as having an affinity for the printable semiconductor element 310, and the binding regions 325 may be chemically modified regions, such as regions having hydroxyl groups protruding from the surface of the PDMS layer, or regions coated with one or more adhesive layers. The conformal contact transfers at least a portion of printable semiconductor element 310 in contact with bonding region 325 to contact surface 320. The printable semiconductor element 310 transferred to the contact surface 320 is brought into contact with the receiving surface 330 of a substrate 335, which substrate 335 may be a flexible substrate, such as a plastic substrate. Subsequent separation of the semiconductor element 310 from the contact surface 320 results in assembly of the semiconductor element 310 onto the receiving surface 330 of the substrate 335, thereby forming a second pattern of printable semiconductor elements 340 characterized by a well-defined position and spatial orientation that is different from the first pattern of printable semiconductor elements 340. As shown in FIG. 2, the printable semiconductor elements 340 remaining on the master 305 are characterized by a third pattern 345 of printable semiconductor elements, the third pattern 345 being different from the first and second patterns of printable semiconductor elements. Printable semiconductor element 340 forming third pattern 345 may then be transferred and/or assembled to substrate 335 or another substrate using the printing methods of the present invention, including selective dry transfer methods.
Fig. 3A-C are schematic diagrams showing equipment, equipment configurations, and equipment components that may be used in the selective dry contact transfer method of the present invention. FIG. 3A illustrates a plurality of printable semiconductor elements 300 on a master 305, wherein selected printable semiconductor elements 300 have one or more adhesive layers 350. As shown in fig. 3A, the adhesive layer 350 has a well-defined pattern. Fig. 3B illustrates a conformable transfer device 315 having a contact surface 320, the contact surface 320 having a plurality of discrete bonding regions 325 forming a well-defined pattern. Fig. 3C illustrates a conformable transfer device 315 having a three-dimensional raised pattern 355, the three-dimensional raised pattern 355 containing raised features 360 of a well-defined pattern. In the embodiment shown in fig. 3C, the raised pattern 355 provides a plurality of contact surfaces 320 that may optionally be coated with one or more adhesive layers. The pattern of the adhesive layer 350, bonding regions 325, and raised features 360 preferably corresponds to the relative position and spatial orientation of the printable semiconductor elements 300 in a device configuration or device array configuration, such as a thin film transistor array configuration.
The use of dry transfer methods can be used in the present invention for assembly, organization, and integration of printable semiconductor elements onto substrates having a variety of compositions and surface morphologies, including curved surfaces. To demonstrate the above-described functional capabilities of the methods and compositions of the present invention, silicon photodiodes containing semiconductor elements were printed directly (i.e., without adhesive) onto the curved surfaces of a variety of optical lenses by dry transfer printing using an elastomeric stamp. Figure 3D provides a photograph of a photodiode array printed onto the spherical surface of a polycarbonate lens (FL 100 mm). Figure 3E provides a scanning electron micrograph of a photodiode array printed onto the curved face of a spherical glass lens (FL 1000 mm). The contrast in the image provided in fig. 3E is slightly enhanced to show the p-doped region. Fig. 3F provides a current (μ a) versus bias (volts) curve illustrating the photo response of the photodiode shown in fig. 3E.
FIGS. 4A1 and 4A2 illustrate preferred shapes of printable semiconductor elements for use in the assembly method of the present invention using dry contact transfer. Fig. 4a1 provides a perspective view and fig. 4a2 provides a top view. The printable semiconductor element includes a ribbon 500 extending along a central longitudinal axis 502, the ribbon 500 having a first end 505, a central region 510, and a second end 515. As illustrated in fig. 4A, the width of the ribbon 500 is selectively varied along its length. Specifically, the first end 505 and the second end 515 are wider than the central region 510. In one exemplary method, the ribbon 500 is formed by etching the master 520. In this embodiment, the master is isotropically exposed to the etchant until the ribbon 500 is connected to the master 520 by only two alignment-retaining members, which include a sacrificial layer 525 adjacent to the first end 505 and the second end 515. During the manufacturing process, the etching process is stopped at this point and the ribbon 500 is brought into contact and/or coupled with an adaptable transfer device. When the transfer device is removed from the master 520, the sacrificial layer 525 fractures and the ribbon 500 detaches. The method is also applicable to dry contact transfer of a plurality of printable semiconductor elements having the shape shown in FIG. 4. One advantage of the method of the present invention is that the orientation and relative position of the plurality of ribbons 500 on the master 520 can be precisely maintained during the transfer, assembly and integration steps. An exemplary range of sacrificial layer thicknesses is 1um to 100nm for a ribbon width of 2um to 100 um. Interestingly, the breakage of the ribbon usually occurs at the end of the object (very near the point/edge where the ribbon is attached to the mother wafer). The wide ribbon is generally not deformed during detachment and attachment to the stamp.
FIGS. 4B1 and 4B2 show preferred shapes of printable semiconductor elements for use in the assembly method of the present invention using dry contact transfer. Fig. 4B1 provides a perspective view and fig. 4B2 provides a top view. The printable semiconductor element comprises ribbons 527 extending along parallel central longitudinal axes 528. The ribbons 527 are secured in a selected position and orientation by an array of retaining elements 530, the array of retaining elements 530 connecting at least one end of the ribbons along the central longitudinal axis 528 to the master 529. The alignment retaining element 530 is fabricated by not determining one or both ends of the ribbon along its central longitudinal axis during the patterning of the ribbon 527. After the ribbon comes into contact with the contact surface of the transfer apparatus and is then removed from the master 520, the arrangement holding member 530 is broken and the ribbon 527 is detached.
To achieve assembly by solution printing, at least a portion of the printable semiconductor element 150 is dispersed in a carrier medium, thereby forming a suspension 190 containing the semiconductor element 150 in the carrier medium. The printable semiconductor element 150 is transferred to the substrate and assembled by printing the suspension solution onto the receiving surface 160 of the substrate. Solution printing can be accomplished by a variety of techniques known in the art, including but not limited to ink jet printing, thermal transfer printing, and screen printing. In the embodiment shown in FIG. 1, the printable semiconductor element 150 is operatively connected to a gold pad 162 located on the receiving surface 160 of the substrate.
Fig. 5A-C provide optical and scanning electron micrographs of a variety of printable semiconductor elements 150, the printable semiconductor elements 150 containing monocrystalline silicon micro-bars having selected physical dimensions. Printable semiconductor elements are shown in the form of an ethanol suspension and cast on various types of substrates. FIG. 5A shows an optical micrograph of a solution cast wound web of a silicon rod (2 microns wide; 2 microns thick; 15 mm long). The inset image shows printable silicon stripes (about ten million) dispersed in an ethanol solution. The low resolution SEM image in FIG. 5B illustrates the range of mechanical flexibility for some flat micro-bars (340 nm thick; 5 microns wide; 15 mm long) solution cast onto bare silicon wafers. Fig. 5C shows a high resolution SEM image of one of these objects. Note the extremely smooth sidewalls produced by the isotropic wet etch process.
Printable semiconductor elements in the form of wires, platelets and disks can also be formed using the method of the invention. By using large area soft lithography techniques, large quantities (i.e., billions) of printable semiconductor elements having lateral dimensions as low as 50nm and having nearly arbitrary geometries can be produced in a single low cost process sequence. Printable semiconductor elements with lateral dimensions as small as 20nm can also be produced by the method of the present invention. For application in thin film transistors in flexible electronic systems, printable semiconductor elements containing long (10 microns) and narrow (1 micron) strips of single crystal silicon are very useful.
Figure 6 provides an image of a printable semiconductor element containing single crystal silicon micro-bars transferred onto a PDMS coated polyimide sheet with a thickness of about 25 microns. The top inset picture illustrates the flexibility of the system itself. The bottom inset shows a top view micrograph of printable dense silicon micro-bars (25 microns wide, 2 microns apart) cold welded to a thin Ti/Au coated mylar sheet. As shown in fig. 6, printable semiconductor elements containing silicon micro-strips are aligned and transferred in a controlled orientation. No cracking of the printable semiconductor element by assembly was observed after careful examination with a scanning electron microscope, which was not observed even when the substrate was significantly flexed. Similar results were obtained (without the elastomer layer) using Au coated mylar sheets as shown in the bottom inset micrograph. In this way a coverage density of nearly 100% can be obtained.
The present invention also provides a combined printable semiconductor element comprising a semiconductor structure operatively connected to one or more other device components, such as a dielectric element, a conductive element (i.e., an electrode), or an additional semiconductor element. Exemplary printable semiconductor elements that may be particularly useful in the fabrication of thin film transistors of the present invention include integrated semiconductors and dielectric elements. Such a combined printable semiconductor element provides a transistor with a high quality, leak-free dielectric and does not require the use of a separate spin-coating step in order to fabricate the dielectric element in a thin film transistor. Furthermore, the use of composite printable semiconductor elements enables efficient device fabrication over large substrate areas by low cost printing techniques.
The following references relate to self-assembly techniques that may be used in the method of the present invention to transfer, assemble and interconnect printable semiconductor elements by contact printing and/or solution printing techniques, among which are: (1) "Guided molecular self-assembly: a review of recovery effects ", Jiyun C HuieSmart Mater. Structure. (2003)12, 264-; (2) "Large-Scale Hierarchical organic Nanosystems for Integrated Nanosystems", Huang, D.; Jin, S.; Wu, Y.; Lieber, C.M. Nano lett. (2003)3(9), 1255-; (3) "direct Assembly of One-dimensional nanostructures in Functional Networks", Yu Huang, Xiangfeng Duan, Qingqi Wei and Charles M.Lieber, Science (2001)291,630-633, and (4) "Electric-field assisted Assembly and alignment of metallic nanoweres", Peter A.Smith et al, appl.Phys.Lett. (2000)77(9), 1399-1401.
All references cited in this application are hereby incorporated by reference in their entirety into this specification to the extent they do not contradict the disclosure of this application. Certain references provided herein are incorporated by reference to provide details as to the sources of starting materials, additional reagents, additional synthetic methods, additional analytical methods, and other uses of the invention. It will be apparent to one skilled in the art that other methods, devices, device elements, materials, processes and techniques besides those specifically disclosed herein can be used to practice the invention as broadly disclosed herein without undue experimentation. This disclosure is intended to cover all art-known functional equivalents of the methods, devices, device elements, materials, processes, and techniques specifically disclosed herein.
U.S. patent application nos. 60/577,077, 60/601,061, 60/650,305, 60/663,391 and 60/677,617, filed on 6/4/2004, 8/11/2004, 2/4/2005, 3/18/2005 and 5/4/2005, respectively, are hereby incorporated by reference in their entirety into this specification to the extent that they do not contradict the disclosure of the present application.
When a group of materials, compositions, components or compounds is disclosed herein, it is to be understood that all individual members of such group, as well as all subgroups of such group, are also disclosed herein separately. When the present specification uses markush groups or other groupings, all individual members of the group and all possible combinations and subcombinations (subcombinations) of the group are intended to be included in the disclosure. Unless otherwise indicated, various combinations of components described or illustrated herein may be used to practice the invention. Where a range is given in this specification, for example, a temperature range, a time range, or a composition range, all intermediate ranges and subranges encompassed within that range, as well as individual values, are intended to be encompassed by the disclosure.
As used herein, "comprising" is synonymous with "including," "comprising," or "having … … characteristics" ("characterized by"), and is non-exhaustive or extensible, and does not exclude other, unrecited elements or method steps. As used herein, "consisting of … …" excludes any element, step, or ingredient not specified in the claims. As used herein, "consisting essentially of … …" does not exclude materials or steps that do not materially affect the basic nature and novelty of the claims. In each instance of this specification, the terms "comprising," "consisting essentially of … …," and "consisting of … …" can be substituted for either of the other two terms.
Example 1: thin film transistor with printable semiconductor elements
The ability of the printable semiconductor element of the present invention to provide a semiconductor channel in a thin film transistor was demonstrated by experimental studies. In particular, it is an object of the present invention to provide a thin film transistor that can be manufactured on a flexible plastic substrate by a printing method. In addition, it is an object of the present invention to provide a high-performance thin film transistor on a plastic substrate, which has similar or superior field effect mobility, switching ratio, and threshold voltage compared to thin film transistors manufactured by conventional high temperature processing.
Figure 7 provides an optical microscope image of a thin film transistor having printable semiconductor elements. The illustrated transistor 531 includes a source electrode 532, a drain electrode 533, a printable semiconductor element 534, a dielectric (not shown in the photomicrograph of fig. 7), and a gate electrode (also not shown in the photomicrograph of fig. 7). The thin film transistor is supported by a substrate comprising a polyester film sheet coated with a gate electrodeIndium tin oxide (ITO, 100nm thick) and a light-cured epoxy as the gate dielectric (SU 8-5; Microchem Corp.). The capacitance of the dielectric was evaluated using a capacitor test structure formed near the device (2.85 nF/cm)2). The device uses a solution cast printable semiconductor element comprising micro-bars about 5 mm long, 20 microns wide, 340 nm thick, fabricated on a p-doped SOI wafer (Soitec) with a device layer thickness of 340 nm and a resistivity of 14-22 Ω · cm. Growing 25 nm thick SiO on top of silicon by dry oxidation in a horizontal quartz tube furnace2And (3) a layer. The source and drain electrodes of Al (20 nm)/Au (180 nm) were formed by lift off technique. The semiconductor channel has a length of 50 microns and a width of 20 microns.
Fig. 8 and 9 show electrical measurement data collected from a thin film transistor of the present invention having printable semiconductor elements. The device operates in a similar manner to a back gated (SOI) device having a top contact configuration. The semiconductor is of a width equal to a 20 micron monocrystalline silicon micro-strip in a channel of 50 microns in length. In this case, the printable semiconductor element is patterned by solution casting. The source/drain contacts are defined by photolithography and lift-off techniques.
Fig. 8 provides a current-voltage (IV) characteristic curve for devices fabricated on pre-oxidized Si wafers. FIG. 9 provides at VDSTransmission curves measured at 0.1V for devices made on a mylar sheet coated with an ITO gate and a polymer dielectric. The slope of this curve determines the effective device mobility (using the physical width of the source and drain electrodes, which in this case is equal to the width of the semiconductor element micro-strip) to be 180cm2Vs. Coating Al/Au on the contacts of the printable semiconductor element provides a reasonably low resistance Schottky barrier (Schottky barrier) contact to silicon, as would be expected for coating Al (work function 4.2 eV) on p-doped silicon. Al is known to diffuse rapidly into silicon, but special care is not required to avoid localization(localized) aluminum-silicon interaction because no high temperature annealing treatment step is taken after the metal is applied. The switching ratio of the device is slightly lower than 103. Analysis of the transmission characteristics of FIG. 9 using a parallel plate model of dielectric capacitance showed a linear field effect mobility of 180cm2V-1S-1. The analysis ignores the effect of contact and process induced threshold voltage variations.
It is theorized that a transistor containing a semiconductor element with a very high aspect ratio (i.e., a ratio of length to width that is too high) in the channel region (i.e., a nanotube or nanowire) will have a response that is different from conventional devices, even with ideal contacts. To avoid this effect, semiconductor elements are chosen which contain micro-strips having a width in the same order of magnitude as the channel length of the transistor. The observed performance (mobility, normalized transconductance, on-off ratio) in this case was about 3/4 for the thin film transistor fabricated after etching Si on the SOI substrate but before lift-off. In these measurements, the embedded SiO2The oxide acts as a dielectric and the substrate carrying the silicon acts as a gate electrode. The results show that the processing steps to produce and transfer printable semiconductor elements to the device substrate do not significantly alter the properties of the silicon or its surface obtained from the initial patterning and silicon etching steps. The results also show that the van der waals interface with SU8 dielectric can support good device performance.
One of the basic advantages of the fabrication method of this embodiment is that it separates the crystal growth and processing of silicon from plastic substrates and other device components. Also, the method of processing printable semiconductor elements of the present invention has a high degree of flexibility in processing sequence and possible material selection. For example, SiO may be formed on one side of silicon in a similar strategy as shown in the present specification for metal coating of integrated source/drain electrodes2The layers are grown (e.g., by first growing a thermal oxide and then stripping the Si elements or stripping the oxide buried in the SOI along with the Si device layer) to produce an integrated dielectric. The dielectric introduced in this way avoids a multiplicity of layers on the plastic substrateA number of problems associated with leakage, hysteresis, doping, trapping (trapping), etc. in solution cast thin dielectrics.
FIGS. 10A-H provide schematic diagrams illustrating the method of the present invention for fabricating a thin film transistor array having combined printable semiconductor elements. As shown in fig. 10A, a gate electrode 547 is deposited on a surface 548 of a thin flexible substrate comprising, for example, Kapton, mylar, or PET. The gate electrode can be patterned on the flexible substrate by any means known in the art including, but not limited to, photolithography, micro-transfer, nano-transfer, soft lithography, or a combination of these methods. As shown in FIG. 10B, the method further comprises the step of fabricating a plurality of combined printable semiconductor elements 550, the printable semiconductor elements 550 comprising layers operatively connected to SiO2The single crystal silicon structure 555 of the dielectric element 560. As shown in FIG. 10B, the combined printable semiconductor element 550 has a strip shape extending a selected length 552 along the central longitudinal axis 551. The combined printable semiconductor element 550 has a selected thickness 553 and a width that varies with the thickness.
As shown in fig. 10C, the method further comprises the step of assembling the combined printable semiconductor element 550 onto the gate electrode 547 and the substrate 548 by dry contact transfer or solution printing. Orienting the combined printable semiconductor element such that the SiO2The dielectric element 560 contacts the gate electrode 547. As shown in fig. 10D, the method further comprises the step of spin coating a thin positive photoresist 561 on the patterned surface of the substrate 548. Alternatively, a roller can be used to apply the thin layer of positive photoresist 561 to the patterned surface of substrate 548. The areas of the photoresist 561 not shielded by the gate electrode 547 are exposed to the electromagnetic radiation beam transmitted through the underside 562 of the substrate 548. For the method of the present invention, a light-transmissive substrate 548 is preferably used, particularly a substrate 548 that is at least partially transparent in the ultraviolet and/or visible region of the electromagnetic spectrum. As shown in fig. 10E, the method further includes the step of developing the thin photoresist layer. As shown in this figure, the region of the thin photoresist layer 561 shielded from light by the gate electrode is not developed. As shown in FIG. 10F, the method further includes aligning the integrated SiO2Dielectric medium is driedOr a step of wet etching, thereby breaking the contact between the source electrode and the drain electrode. In the embodiment shown in FIG. 10F, this is accomplished by exposing the patterned surface of substrate 548 to CF4Plasma is achieved. As shown in fig. 10G, the method further includes a step of determining the source electrode and the drain electrode by light-shielding mask (shadow mask) evaporation. The alignment of the semiconductor element, the source electrode and the drain electrode does not need to be very precise, since the semiconductor channel will be determined in the next manufacturing step. As shown in fig. 10H, the method further includes the step of defining the semiconductor channels by stripping the positive photoresist, for example, by exposure to a solvent such as acetone.
Fig. 11A-D provide schematic illustrations of the method of the present invention for fabricating a printable device with integrated gate electrode, gate dielectric, semiconductor, source and drain electrodes. As shown in fig. 11A, a high quality gate dielectric is created by thermal oxidation of the surface of the SOI wafer. A gate electrode material (e.g., metal or doped polysilicon) is then deposited. Selected areas of the top surface are then masked using, for example, photolithography. In one embodiment, an array of identical patterns with controlled spacing is formed in a single masking step. The printable semiconductor elements are then fabricated by anisotropic wet and/or dry etching. Preferably, three different selective etching methods are performed in sequence to etch away the exposed regions of the gate electrode material, the gate dielectric and the top silicon layer.
A photolithography process as shown in fig. 11B is used to define the channel of the transistor. In this process step, the exposed regions of the gate electrode material are etched away (dry or wet etching). As shown in fig. 11C, the photoresist is then heated above its glass transition temperature, thereby initiating the reflow process. The reflow distance (reflow distance) of the photoresist may be selected by carefully selecting the appropriate thickness of the photoresist layer, the glass transition temperature of the photoresist layer, or the temperature and duration of the reflow process. The exposed region of the gate dielectric is then etched using an HF solution.
Next, a metal coating process is performed as shown in FIG. 11D, and then the metal deposited on the photoresist is stripped off to complete the fabrication of the printable device. The source and drain electrodes are self-aligned to the gate (self align) and the spacing between the source and drain electrodes can be selected by adjusting different parameters, such as the temperature and duration of the reflow process.
The printable device shown in FIG. 11D can be transferred and assembled onto a substrate, such as a plastic substrate, by the dry transfer or solution printing methods of the present invention. The self-alignment method shown in fig. 11A-D provides a simple way to assemble all of the elements required to implement a printable device, such as a MOSFET device. An important advantage of the fabrication method of the present invention is that all process steps that require temperatures that are not suitable for plastic substrates (e.g., required temperatures > about 400 ℃) can be performed on the SOI substrate before the devices are stripped and transferred to the substrate. For example, other processing steps, such as doping of the source and drain electrode contact regions, formation of silicide layers, and high temperature annealing of the device, may be performed prior to transferring the element to the plastic substrate.
Example 2: stretchable printable semiconductor element
The present invention provides stretchable printable semiconductor elements that have good properties when stretched, flexed or deformed. In addition, the stretchable printable semiconductor elements of the present invention can accommodate a variety of device configurations to provide fully flexible electronic and optoelectronic devices.
Figure 12 provides an atomic force micrograph illustrating a tensile printable semiconductor element of the present invention. The stretchable printable semiconductor element 700 includes a flexible substrate 705 having a support surface 710 and a curved semiconductor structure 715 having a curved inner surface 720. In this embodiment, at least a portion of the curved interior surface 720 of the curved semiconductor structure 715 is bonded to the support surface 710 of the flexible substrate 705. The curved inner surface 720 may be joined to the bearing surface 710 at selected points along the inner surface 720 or at substantially all points along the inner surface 720. The exemplary semiconductor structure shown in fig. 12 includes a buckled single-crystal silicon ribbon having a width equal to about 100 microns and a thickness equal to about 100 nanometers. The flexible substrate shown in fig. 12 is a PDMS substrate having a thickness of about 1 mm. The curved inner surface 720 has a profile characterized by a substantially periodic wave that extends along the length of the ribbon. As shown in fig. 12, the amplitude of the periodic wave is about 500 nanometers and the peak spacing is about 20 microns. Fig. 13 is an atomic force micrograph giving an enlarged view of a curved semiconductor structure 715 having a curved inner surface 720. Figure 14 shows an atomic force micrograph of an array of tensile printable semiconductor elements according to the present invention. Analysis of the atomic force micrograph of fig. 14 shows that the buckled semiconductor structure is compressed by about 0.27%. Figure 15 shows an optical micrograph of a stretch printable semiconductor element of the present invention.
The profile of the curved face 720 enables the curved semiconductor structure 715 to expand or contract in a direction along the deformation axis 730 without experiencing significant mechanical strain. The profile may also enable the semiconductor structure to flex, bend, or deform in directions other than along the deformation axis 730 without causing significant mechanical damage or loss of performance due to strain. The curved face of the semiconductor structure of the present invention may have any profile that provides good mechanical properties, including, for example, stretchability, flexibility, and/or bendability, and/or good electrical properties, including, for example, having good field effect mobility, when the semiconductor structure is flexed, stretched, or deformed. Exemplary profiles may exhibit a plurality of raised and/or recessed regions and characteristics of a variety of waveforms including sine waves, gaussian waves, Aries functions, square waves, lorentz waves, periodic waves, non-periodic waves, or any combination thereof. The waveforms useful in the present invention may vary in two or three dimensions.
Fig. 16 shows an atomic force micrograph of a tensile printable semiconductor element of the present invention having a buckled semiconductor structure 715 bonded to a flexible substrate 705, the flexible substrate 705 having a three-dimensional raised pattern on its support surface 710. The three-dimensional raised pattern includes recessed regions 750 and raised features 760. As shown in fig. 16, the bent semiconductor structure 715 is connected to the bearing surface 710 in the recessed region 750 and on the raised features 760.
Figure 17 shows a flow chart illustrating an exemplary method of the present invention for fabricating a stretchable semiconductor element. In this exemplary method, a pre-strained elastomeric substrate is provided in an expanded state. The pre-straining may be accomplished by any means known in the art, including but not limited to rolling and/or pre-bending the elastic substrate. An exemplary elastomeric substrate that can be used in the method of the present invention is a PDMS substrate having a thickness equal to about 1 mm. The elastic substrate may be prestrained by expansion along one axis or by expansion along multiple axes. As shown in fig. 17, at least a portion of the inner surface of the printable semiconductor structure is bonded to the outer surface of the pre-strained elastic substrate in the expanded state. The association may be achieved by covalent bonding between the inner surface of the semiconductor structure and the outer surface of the pre-strained elastic substrate, van der waals forces, the use of an adhesive layer, or any combination thereof. In an exemplary embodiment where the flexible substrate is PDMS, the support surface of the PDMS substrate is chemically modified so that it has a plurality of hydroxyl groups extending from its surface to facilitate covalent bonding with the silicon semiconductor structure. Returning to FIG. 17, after the pre-strained elastomeric substrate is attached to the semiconductor structure, the elastomeric substrate is at least partially relaxed to a relaxed state. In this embodiment, relaxation of the flexible substrate causes the inner surface of the printable semiconductor structure to bend, thereby forming a semiconductor element having a curved inner surface.
As shown in fig. 17, the method of manufacture may optionally include a second transfer step in which the semiconductor structure 715 having a curved inner surface 720 is transferred from an elastic substrate to another substrate, preferably a flexible substrate. This second transfer step may be achieved by: the exposed surface of the semiconductor structure 715 having the curved interior surface 720 is brought into contact with the receiving surface of another substrate that is capable of bonding to the exposed surface of the semiconductor structure 715. Attachment to other substrates may be accomplished by any means known in the art, including covalent bonding, bonding by van der waals forces, and the use of adhesives.
The stretchable semiconductor elements of the present invention can be effectively integrated into a variety of functional devices and device components, such as transistors, diodes, lasers, MEMS, NEMS, LEDs and OLEDs. The stretchable semiconductor elements of the present invention have certain advantages over conventional rigid inorganic semiconductors. First, the stretchable semiconductor element may be flexible and thus less susceptible to structural damage caused by flexing, bending and/or deformation than conventional rigid inorganic semiconductors. Second, the stretchable semiconductor element of the present invention may exhibit higher intrinsic field effect mobility than conventional unstrained inorganic semiconductors, since the flexed semiconductor structure may be in a slightly mechanically strained state to provide a curved inner surface. Finally, stretchable semiconductor elements are likely to provide good thermal performance because they are free to expand and contract during temperature cycling of the device.
Example 3: method for manufacturing printable semiconductor element
The present invention provides methods for manufacturing printable semiconductor elements from a variety of starting materials including single wafers, silicon on substrate wafers, germanium wafers, polycrystalline silicon films, and ultra-thin silicon wafers. In particular, the present invention provides a low cost method of manufacturing large quantities of printable semiconductors in selected relative positions in selected orientations.
FIG. 18A illustrates an exemplary method of fabricating printable semiconductor elements from Si-Ge epi substrates. In this method, selected regions of the Si epi layer are masked by depositing a masking material comprising, for example, a metal-containing, SiO2Or a thin film of SiN. This masking step determines the shape and certain physical dimensions (e.g., the length and width of the ribbon) of the printable semiconductor element to be fabricated. The exposed Si surface of the Si-Ge epi substrate is anisotropically etched by dry or wet chemical etching. This results in raised features of silicon, preferably with smooth sidewalls, which can be effectively stripped by lift-off techniquesFrom a Si-Ge epi substrate, the lift-off technique including, for example, using 1:1:4 NH4OH:H2O2:H2O selective SiGe wet etch at 50 ℃. Optionally, the source electrode, the gain electrode, the gate electrode, the dielectric element, or any combination thereof may be integrated into the semiconductor element prior to lift-off. One advantage of this manufacturing method is that the master can be cleaned and reused.
FIG. 18B illustrates an exemplary method of fabricating printable semiconductor elements from bulk silicon substrates, preferably single crystal silicon substrates. In the method, a silicon wafer is first dry oxidized in, for example, a quartz tube furnace at a temperature selected from the range of about 800 ℃ to about 1200 ℃. A thin layer of gate material is then deposited on the oxidized surface of the silicon wafer. Exemplary gate materials include metal or doped polysilicon. The thin layer of gate material is selectively patterned with photoresist. This patterning step determines the shape and certain physical dimensions (e.g., the length and width of the ribbon) of the printable semiconductor element to be fabricated. The thin layer of gate material and the dielectric layer are subjected to a back etch (back etch) to form a raised feature comprising a photoresist layer, a layer of gate material, a dielectric layer, and a silicon layer, and the raised feature preferably has smooth sidewalls. The photoresist layer is then reflowed, for example, by annealing to a temperature selected from the range of about 100 ℃ to about 130 ℃. The reflow of the photoresist causes a portion of the photoresist to transfer to the sidewalls of the raised features. As shown in fig. 18B, the exposed Si surface is isotropically etched by wet or dry etching to peel off the protruding members and form a combined semiconductor element, which preferably has a smooth surface. The isotropic etch of silicon may use 64:3:33 HNO3:NH4F:H2And O solution. The advantage of this manufacturing method is that the cost of the silicon substrate raw material is low and the master can be reused after planarization (ECMP).
FIG. 18C illustrates another exemplary method for fabricating printable semiconductor elements from bulk silicon substrates, preferably single crystal silicon substrates. In the method, the outer surface of a bulk silicon substrate is selectively textured with a photoresistFigure (a). This patterning step determines the shape and certain physical dimensions (e.g., the length and width of the ribbon) of the printable semiconductor element to be fabricated. The patterned substrate surface is anisotropically etched, preferably using a dry etching process such as reactive ion etching and inductively coupled plasma etching, to form raised features, preferably having smooth sidewalls. By depositing a masking material, e.g. a thin layer of metal, SiO2Or SiN, masking at least a portion of sidewalls of the raised features. In one embodiment, the mask material is applied to the sidewalls of the raised features by an oblique evaporation or sputter deposition technique, which is combined with rotation of the sample to ensure deposition of all exposed sidewalls. The exposed Si surface is isotropically etched using a wet or dry etching process to cause the raised features to fall off and form printable semiconductor elements, preferably having a smooth surface, as shown in fig. 18C. The isotropic etch of silicon may use 64:3:33 HNO3:NH4F:H2And O solution. The advantage of this manufacturing method is that the cost of the silicon substrate raw material is low and the master can be reused after planarization (ECMP).
FIG. 18D illustrates yet another exemplary method of fabricating printable semiconductor elements from bulk silicon substrates, preferably single crystal silicon substrates. In this method, the outer surface of a bulk silicon substrate is selectively patterned with photoresist. The patterned substrate surface is anisotropically etched to form raised features. The silicon substrate is then annealed, for example, in a quartz furnace at a temperature of about 1100 ℃ in nitrogen. The surface of the annealed silicon substrate is then patterned with photoresist by masking selected areas. This patterning step determines the shape and certain physical dimensions (e.g., the length and width of the ribbon) of the printable semiconductor element to be fabricated. The patterned surface of the annealed Si substrate is anisotropically etched using a wet or dry etching process to form a printable semiconductor element, preferably having a smooth surface, as shown in fig. 18D. The advantages of this fabrication method are that the cost of the silicon substrate raw material is low, and the master can be reused after planarization (ECMP), and the source, drain, gate and dielectric device components can be integrated after the annealing step. Further, in the first etching step, wet etching may be used for the 110 silicon wafer.
FIG. 18E illustrates an exemplary method of fabricating printable semiconductor elements from ultra-thin silicon substrates. In the method, the outer surface of an ultra-thin silicon substrate is selectively patterned with a photoresist. This patterning step determines the shape and certain physical dimensions (e.g., the length and width of the ribbon) of the printable semiconductor element to be fabricated. The patterned substrate surface is anisotropically etched through the thickness of the ultra-thin silicon substrate to form the printable semiconductor element. For certain applications of the fabrication method, ultra-thin silicon substrates having a thickness selected from the range of about 10 microns to about 500 microns are preferred. One advantage of this fabrication method is the lower cost of the ultra-thin silicon substrate raw material.
FIGS. 18F and 18G illustrate an exemplary method of fabricating printable semiconductor elements from polysilicon films. In this method, a thin layer of polycrystalline silicon is deposited on a support substrate, such as a glass or silicon substrate, having a sacrificial surface layer, such as comprising SiN or SiO2Coating of (2). The polycrystalline film is then annealed to selectively mask selected regions of the exposed surface by depositing a masking material comprising, for example, a metal-containing, SiO, metal2Or a thin film of SiN. This masking step determines the shape and certain physical dimensions (e.g., length and width of the ribbon) of the printable semiconductor element to be fabricated. The patterned surface is anisotropically etched by dry or wet chemical etching to form raised features of silicon supported by the sacrificial layer, the raised features preferably having smooth sidewalls. Isotropic etching of the sacrificial layer releases the raised features, thereby forming printable semiconductor elements. One advantage of this manufacturing method is that the support substrate can be cleaned and reused. Alternatively, the thin layer of polysilicon can be deposited directly on the SiO2On a substrate. Similar annealing, configuration may be used as shown in FIG. 18GThe patterning, anisotropic etching, and lift-off steps form the printable semiconductor elements. Optionally, in both methods, the source electrode, the gain electrode, the gate electrode, the dielectric element, or any combination thereof may be integrated into the semiconductor element before the lift-off.
FIGS. 18H (1) and 18H (2) illustrate a method of fabricating a single crystal semiconductor film using the printable semiconductor element of the present invention. As shown in FIG. 18H (1), an amorphous or polycrystalline semiconductor thin film is produced on the surface of a substrate containing an insulating material such as SiO2. Amorphous or polycrystalline semiconductor films may be prepared by any route known in the art including, but not limited to, deposition techniques such as vapor deposition or sputter deposition. Referring again to FIG. 18H (1), a printable semiconductor element comprising a single crystal semiconductor structure is transferred to a surface of a substrate covered with an amorphous or polycrystalline semiconductor film. For some applications of the method, it is preferred to use a single crystal semiconductor structure having one long lateral dimension. The invention also includes methods in which a printable semiconductor element comprising single crystal semiconductor structures is first transferred to a substrate surface, followed by deposition of an amorphous or polycrystalline semiconductor film.
As shown in fig. 18H (2), the amorphous or polycrystalline semiconductor thin film is annealed while in contact with the single crystal semiconductor structure, for example, at a high temperature, for example, a temperature greater than 1000 ℃. In this embodiment of the invention, the single crystal semiconductor structure acts as a seed to promote phase transition of the entire film from an amorphous or polycrystalline state to a strictly ordered single crystalline state. As shown in fig. 18H (2), the phase transition occurs as the high temperature gradient front (front) moves across the surface of the wafer. Different high temperature furnaces or focused optical systems may be used to generate the temperature gradient required to achieve effective phase change of the semiconductor film. One advantage of this method is that it can significantly reduce the cost of producing single crystal semiconductor films, such as single crystal silicon or germanium films.
FIG. 18I shows an example of fabrication of printable semiconductor elements containing microwires from GaAs substratesA sexual method. As shown in this figure, the exposed surface of the GaAs substrate is patterned with a masking material, such as photoresist. Patterning can be achieved by micro-or nano-contact printing or conventional photolithography, as shown in fig. 18E. The patterned surface is anisotropically etched by wet etching. In the exemplary method shown, the concavity of the sidewall is H3PO4-H2O2-H2O solution is obtained and the formed raised features are etched until they fall off the GaAs substrate, thereby forming GaAs microwires. As shown, the photoresist layer may be cleaned with acetone and exposed to O2Reactive Ion Etch (RIE) removal. One advantage of this technique is that the GaAs substrate can be reused after planarization (ECMP). This technique can also be used to fabricate microwires from InP substrates.
FIG. 18J illustrates an alternative method of fabricating printable semiconductor elements containing single crystal silicon ribbons. The raw material in the method is a Si (110) wafer. As shown in FIG. 18J, SiO is used for the outer surface of the Si (110) wafer2Selective patterning of thin films, said SiO2The thin film acts as a mask during processing. This masking step determines the shape and certain physical dimensions (e.g., length and width of the ribbon) of the printable semiconductor element to be fabricated. The exposed (i.e., unmasked) surface of the Si (110) wafer is then isotropically etched by dry or wet chemical etching. This processing step forms raised features of silicon, preferably with smooth sidewalls separated by a series of trenches of selected depth. The raised features of silicon are then detached from the Si (110) wafer by an isotropic etch and lift-off process to form printable semiconductor elements. Optionally, the source electrode, the gain electrode, the gate electrode, the dielectric element, or any combination thereof may be integrated into the semiconductor element prior to lift-off. One advantage of this method of manufacture is that the mother wafer can be cleaned and reused. Fig. 18J also shows SET micrographs of Si (110) at various points in the treatment process.
FIG. 18K illustrates an alternative method of fabricating printable semiconductor elements containing single crystal silicon ribbons. The raw material in this method is a Si (111) wafer. The Si (111) wafer is subjected to a selective isotropic etch, for example using a combination of a conventional photolithography mask and wet etch process. This processing step forms raised features of silicon. As shown in fig. 18K, the sidewalls, surfaces, or both of the raised features of silicon are coated using a passivation process. Printable single crystal silicon ribbons were peeled from Si (111) wafers by isotropic etching and lift-off processing. Fig. 18J also shows a SET micrograph of a single crystal silicon ribbon formed by this method just prior to exfoliation.
Example 4: method for manufacturing semiconductor nano-wire and micron-wire
It is an object of the present invention to provide methods for fabricating semiconductor nanowires and microwires having good mechanical and electrical properties that enable their use in a variety of devices, device assemblies and device arrangements. It is another object of the present invention to provide a method of assembling nanowires and microwires to construct selected single-layer structures, multilayer structures and functional devices containing these elements. To evaluate the utility of the method of the present invention, nanowires and microwires of GaAs and InP were fabricated and evaluated for electrical conductivity and mechanical flexibility in a variety of device configurations. Furthermore, the ability of the present method to assemble large numbers of nanowires and microwires in well-defined locations and orientations, corresponding to large substrate surface areas, in well-defined orientations was evaluated by fabricating a variety of complex nano/microwire assemblies containing both single-layer and multi-layer structures. The methods of the present invention for fabricating and assembling GaAs and InP nanowires and microwires have proven to strictly control the width, length and spatial orientation of the wires. In addition, the fabricated GaAs and InP nanowires and microwires exhibit good mechanical and electrical properties when integrated into microelectronic devices.
FIG. 19 provides a schematic diagram illustrating steps of an exemplary method of forming and transferring an array of GaAs nanowires onto a substrate, including, for exampleA plastic substrate comprising a poly (diethyl terephthalate) (PET) sheet coated with a thin layer of cured Polyurethane (PU). As shown in fig. 19, the process starts with a piece of GaAs wafer (American Xtal Technology, Fremont, california) with its surface oriented in the (100) direction. Mixing SiO2Is defined along () Directionally oriented linear form, thus producing a structure for anisotropic etching using a solution containing H in a volume ratio of 1:13:123PO4(85wt%):H2O2(30wt%):H2H of O3PO4And H2O2(ii) (step i in fig. 19). When applied in this manner, the etch chemistry exhibits a high degree of anisotropy, thereby exhibiting a high degree of anisotropy in SiO2A clearly defined inverted mesa GaAs profile is formed under the mask strip. For a sufficiently long etching time, the two sidewalls of each flip-flop intersect, resulting in a line with a triangular cross-section. This triangular cross-section is shown in the top inset of panel a (left side) of fig. 19.
In one embodiment, the patterned SiO2SiO with massive lines2The thin film surrounds, resulting in both ends of each GaAs line being connected to the mother wafer. The connection constrains the wires and maintains the spatial orientation and arrangement as SiO2As determined by the pattern. FIG. 20A provides a scanning electron micrograph of unsupported GaAs lines made from GaAs wafers using isolated SiO2The lines are patterned. Notably, lateral undercutting of GaAs occurs with vertical etching, enabling the width of the resulting GaAs line to be reduced to the nanometer scale, even in SiO2This is also the case when the lines have a width of micrometers.
The array of GaAs wires produced by the method of the present invention can be transferred to a plastic substrate while preserving the orientation and relative position of the individual wires in the array. In the embodiment shown in FIG. 19In one embodiment, a conformable elastomeric transfer element, such as a flat piece of poly (dimethylsiloxane) or PDMS, Sylgard184, A/B =1:10, (Dow Corning), is placed on a GaAs wafer to pick up the wires (as shown in step ii of FIG. 19). In this embodiment, the PDMS sheets are bonded to SiO2A strong bond force is required between the mask layers to break the crystalline connection with the underlying substrate at the wire ends.
Cleaning PDMS stamps with a Weak oxygen plasma and with SiO2The masked GaAs wafer facilitates condensation reaction between PDMS and SiO2Forming covalent silicon oxygen (Si-O-Si) bonds therebetween (see the middle inset of fig. 19). Accordingly, the present invention includes a method in which an elastomeric transfer element, having SiO, is transferred2Exposing the masked semiconductor wafer or both to a weak oxygen plasma to impart SiO to the wafer2The masked semiconductor wafer is firmly transferred to the elastomeric transfer element in an efficient mechanical manner. Density of bonds at the interface and-O on the surface of PDMSnSi(OH)4-nIs proportional and the latter is highly dependent on the strength of the oxygen plasma and the treatment time. A long period of time with a strong plasma treatment can result in too strong a bond to release the wires from the PDMS onto the desired plastic substrate. Controlled experiments have shown that PDMS and SiO coatings2The GaAs wafers of (1) were best processed for 3 seconds and 60 seconds with a Plasma generated from oxygen at 10mTorr pressure, 10sccm flow rate, and 10W power density (Uniaxis 790, Plasma-thermal Reactive Ion Etching System), respectively. In these embodiments, the electron beam evaporated SiO2The strength of the interaction between the mask layer and GaAs is sufficient to prevent delamination (delaminations) during transfer. Contacting a PDMS stamp with a SiO2After the masked GaAs wafer was contacted for-2 hours, it was peeled off from the GaAs substrate so that the lines were all detached (as shown in step iii of fig. 19).
The method of the present invention makes the fabrication and assembly of large numbers of nanowires and/or microwires practically feasible. For example, a GaAs wafer after the transfer step (step iii in FIG. 19) is subjected toThe rows are polished to restore the plane for another round of line manufacturing (step iv of fig. 19). The above-described combination of wafer polishing and wire fabrication makes it possible to produce a large number of GaAs wires from a single wafer. For example, if one cycle of the anisotropic etch and polish process consumes 2 μm thick GaAs, a GaAs wafer 10cm in diameter and 450 μm thick (available from American Xtal Technology) can be produced with sufficient dense coverage area of 1.76m2Of the plastic substrate (22 billion lines with a width of 400nm and a length of 100 μm). These conditions are typical for the results described in the present invention. Thus, such repeated implementation of line fabrication followed by a wafer polishing step can utilize large wafers in a highly cost-effective manner.
As shown in steps v and vi of FIG. 19, with SiO2The GaAs lines of the mask element can be efficiently transferred to a substrate having an adhesive layer on the outer surface, such as a plastic substrate. In one embodiment, the PDMS stamp with the bonded GaAs wires is exposed to the ambient environment for a day or washed with ethanol to restore the PDMS surface to its original hydrophobic state. This hydrophobicity of the PDMS surface substantially prevents the strong interaction of PDMS with the normally hydrophilic adhesive. When the recovered PDMS stamp was placed against the adhesive layer, only the SiO adhered to2The GaAs lines on the masking strip are wettable to an adhesive comprising, for example, a PU layer (available from Nolarland products, Cranbury, N.J.) spin-coated onto a plastic substrate (e.g., PET with a thickness of 175 μm, mylar, south wall Technologies, Palo Alto, Calif.). By controlling the spin speed, the thickness of the PU layer can be varied from 1 to tens of microns. The PU layer was cured by irradiating the sample with an ultraviolet lamp (Model B100AP, Black-Ray, Upland, Calif.) for 1 hour, and the cured PU was cured with GaAs and SiO radiation2Strong bonds are formed between the mask stripes and between the cured PU and the underlying PET sheet (step v of fig. 19). Stripping PDMS stamp to make GaAs line and SiO2The strips were embedded in the cured PU matrix while maintaining the order and crystallographic orientation similar to those of the lines prior to stripping (step vi of fig. 19). SiO 22With PDMS stampsSeparation is achieved by two effects: i) with PDMS and SiO2Moderate adhesive strength associated with sparse silicon-oxygen bonds at the interface, which is further weakened during the restoration of the PDMS surface; and ii) SiO2Ultra-thin SiO remaining on PDMS after bond failure, which can be amorphous, loose and brittle2Layer (thickness of a few nanometers). The plastic sheets were immersed in a buffered oxide etchant solution (BOE, NH)4F (40 wt%) =10: 1) SiO was removed in HF (49wt%) = 15 min2Masking the stripes so that the clean (100) top surface of the GaAs nanowires is facing outward (step vii of fig. 19).
A simple "top-down" method for fabricating and dry printing arrays of GaAs wires provides a number of advantages. For example, the geometry of the lines (i.e., length, width, and shape) and their spatial organization may be determined by an initial lithography step to meet the design of the desired electronic or optical purpose application. The transfer technique can achieve a yield of up to 100% while maintaining the pattern determined by photolithography. The strictly oriented crystal planes of the transfer lines on the plastic substrate (i.e., the top (100) plane) provide an extremely flat top surface (with a flatness similar to that of the original wafer), which is very useful for device fabrication. And, SiO2The masking strip prevents the top surface of the GaAs line from being contaminated by organics such as PDMS, PU, and solvents used in processing. The GaAs wires are embedded in the cured PU to fix them, preventing them from moving in the lateral or vertical direction, especially when the plastic substrate is flexed or twisted. It is important to note that PU and PET are only examples of materials that can be used in the present invention. Accordingly, other adhesives (e.g., NEA 155) will be understood by those skilled in the artAnd other types of plastic substrates (e.g. plastic substrate)Or polyimide film) can be used in the method of the present invention.
Unlike the prior art "bottom-up" method, the "top-down" method of the present invention can produce GaAs nanowires of uniform length from a few microns to tens of centimeters (i.e., the diameter of the original wafer). FIG. 20A shows an SEM photograph of unsupported GaAs nanowires of 400nm width and 2cm length randomly assembled onto a mother wafer. The long nanowires form a curved structure during drying, exhibiting a high degree of flexibility provided by their narrow width. As shown in the lower inset of fig. 20A, the looped nanowires have a bend radius as small as-20 μm, indicating that nanowires with a width of-400 nm can sustain a strain of-1.3%. The upper inset in fig. 20A provides a scanning electron micrograph of the cross-section of the nanowire before it is stripped, which clearly shows the formation of the GaAs inverted mesa-like profile and the undercutting caused by the anisotropic etch.
In one aspect of the invention, SiO is selectively adjusted2The width of the GaAs line is controlled by the width of the mask line, the selective adjustment etch time, or both. Widths between hundreds of microns and tens of nanometers can be achieved using the method of the present invention. Control of the etch time provides a simple etch of SiO with micron-scale widths2Methods of patterning nanowires. FIGS. 20B-E show scanning electron micrographs of single lines obtained by etching a GaAs wafer with 2 μm wide SiO2The lines are patterned. These lines were transferred to a PDMS surface using the method described above to accurately measure the average width of its top surface (noted as). FIG. 20F provides a graph showing the average width of the top surface of a wire made by the method of the present inventionGraph of etch time. The curve shows that GaAs lines down to 50nm in width can be obtained using this embodiment of the invention. Linear relationship between width and etch time and the aforementioned H3PO4-H2O2-H2The results of the study of GaAs etch kinetics in O solution are consistent when H2O2And H3PO4Molar ratio (n) therebetweenH2O2/nH3PO4) Greater than 2.3 and H2Mole fraction of O (r)H2O) 0.9 or less (n of etchant used in this experiment)H2O2/nH3PO4And rH2O7.8 and 0.9, respectively), the etch rate is proportional to the etch time. Statistical results show the distribution of line widths with widths of 50nm (averaged along their length)<9% which is slightly narrower than in a "bottom up" nanowire reported to have an average width of-16.8 nm>Deviation of 14%.
The scanning electron micrographs shown in fig. 20B-D also show that the triangular cross section of the lines remained during thinning, indicating that the etch was highly anisotropic, even for unsupported GaAs lines. The near sight line was found to have some roughness on its sidewalls. Most of this roughness is directly due to the use of the material for forming SiO2Photoetching process of mask strips; some are due to mask line misalignment and etching itself. This roughness determines the minimum continuous line width that can be achieved using this embodiment of the invention. As shown in fig. 20F, the ratio of the width deviation along each line to the average line width ((F))) And is also highly dependent on etch time. When the ratio is less than 100%, continuous GaAs nanowires can be prepared. The curve provided in fig. 20F demonstrates that the width of the nanowires obtained by practicing this embodiment of the invention can be as low as-40 nm. Nanowires with different average widths exhibit substantially the same width variation (i.e., -40 nm) along each wire, as along each SiO2The width deviation of the mask lines (i.e., -36 nm) is close. The roughness of the sidewall of the comparative proof line is mainly formed by SiO2The rough edges of the mask stripes are induced regardless of the etch time. Thus, photolithography, which reduces the roughness of the photomask strip, is used to reduce the roughness of the line edges. It is important to note that the transfer method described in this embodiment exposes the original, ultra-flat, unetched top surface of the lines to the final substrate (i.e., the figure)19 PET) for electrical connection and device fabrication.
FIGS. 21A-G show images of arrays of various GaAs lines printed on PDMS and PU/PET substrates. The width of the line in this example is 400nm and the length is 100 μm. Corresponding SiO2Mask lines on (100) GaAs wafer edge) Oriented in the direction, 2 μm wide and 100 μm long. FIG. 21A is a photograph taken through SiO2Scanning electron micrographs of an array of GaAs wires with a mask layer attached to a PDMS lithographic template, indicating that the order of the wires was preserved. The inset of fig. 21A shows the ends of the three wires at a higher magnification, which clearly reveals the breakage of the ends. As shown in FIG. 21B, peeling the PDMS stamp from the cured PU resulted in SiO2The smooth surface of the mask strip facing outwards (as smooth as the surface of PDMS). As shown in FIG. 21C, the SiO is etched away with BOE2The layer exposes the original top surface of the GaAs wire. FIG. 21D provides an optical image taken from a PU/PET substrate with embedded GaAs lines, showing that large area arrays of lines can be programmed onto the PU/PET substrate using the method shown in FIG. 19. Arrays of GaAs lines with other patterns, such as line strips (patch) of lines of different lengths, can also be transferred onto the PU/PET substrate.
The transfer process was repeated to print arrays of multilayer GaAs wires onto the same PET substrate by spin-coating a new layer of PU. These methods provide an important route to the production of multilayer structures containing nanowires and/or microwires. Figures 21E and 21F provide representative images of a multilayer structure with arrays of bi-layer GaAs lines. In one embodiment, such a multilayer structure is obtained by rotating the second layer by different angles (90 ° and 45 ° for E and F, respectively) with respect to the first layer. Figure 21G provides an image of a PU/PET substrate with a three layer array of GaAs wires obtained by repeating the printing process on the samples shown in figures 21E and 21F. The spacing between the wire arrays can be controlled by adjusting the thickness of the PU layer, which is controlled by the rotation speed. The performance of such multilayers does not necessarily require any form of epitaxial growth, and the PU isolates the array of different layers. This manufacturing capability can be used for a variety of device manufacturing applications.
The wire fabrication and printing techniques of the present invention can produce arrays of wires of other semiconductor materials on plastic substrates by using suitable anisotropic etchants. For example, by adding at 1% (v/v) Br2Etching a (100) InP wafer in a methanol solution of (a) to produce an InP wire having a triangular cross-section, the (100) InP wafer having a cross-section defined by a plane defined by) Directional SiO2The lines are masked. FIGS. 22A-C show scanning electron micrographs of arrays of InP wires on PDMS and PU/PET substrates. These lines are made of SiO with a length of 50 μm and a width of 2 μm2And InP wafers with patterns formed by lines. The lines shown have lengths and widths of 35 μm and 1.7 μm, respectively. InP in Br for line end profile and lateral pitting2The etching characteristics of the methanol solution are obviously different from the etching characteristics of GaAs in H3PO4-H2O2Etching characteristics in aqueous solution. For example, the etching method leaves all InP line ends separated from the mother wafer, even though the etch mask is similar to that used in making GaAs lines (FIG. 21). Furthermore, the degree of pitting in InP is lower than in GaAs, indicating that by using narrow SiO2Small width (less than 500 nm) InP lines can be more easily fabricated by stripes rather than by controlling the etch time.
By measuring the change of electrical properties with bend radius, arrays of GaAs wires (doped with Si and having a carrier density of 1.1-5.6X 10, the same as shown in FIG. 21) on PU/PET substrates were aligned17cm3Made from n-GaAs wafers) was evaluated for mechanical flexibility. The structure is made from an array of GaAs wires determined according to the method of figure 19. Two schottky contacts made of Ti/Au (5 nm/150 nm) spaced 10 μm apart were identified on these lines by photolithography and metal deposition. FIG. 23A provides an exemplary two-terminal diode containing an array of GaAs linesSchematic and pictorial representations of a device. Immediately before electrode deposition, the substrate is immersed in a concentrated HCl solution for 10min to remove the native oxide layer on the surface of the GaAs wire.
Fig. 23B shows the current-voltage (I-V) curves recorded at different bend radii. Both of these curves show the expected diode characteristics. The small difference between these curves indicates that almost no GaAs nanowires break even when the substrate has a bending radius (R) of 0.95 cm. The strain on the PET surface in this case was-0.92%, which is less than the strain estimated to be present in the unsupported GaAs nanowire shown in the inset of fig. 20A. These results further demonstrate that GaAs nanowires produced by the "top-down" fabrication method of the present invention are flexible and can be integrated with flexible plastic sheets. We note that the data show that when the substrate relaxes after the first bend, the current is 40% less than the current recorded for the original device before bending. Fig. 23C shows the current-voltage (I-V) curves measured after the two-terminal diode device relaxes again after bending at different bend radii. For comparison, the black curve in fig. 23C represents the current-voltage curve corresponding to the device configuration before bending. However, the fact that the I-V characteristic does not change with changes in bend radius and does not change with multiple bend/relax cycles after the first bend/relax cycle indicates that the one-time reduction in current may be due to an initial change in performance (initial variation) at the interface between the electrode and the wire.
The use of conventional photolithography in combination with anisotropic chemical etching of high-quality bulk single-crystal wafers of these materials forms an attractive "top-down" route to the fabrication of triangular cross-section GaAs and InP microwires and nanowires. The dimensions of the lines and their organization can be selectively adjusted by appropriate choice of photolithography and etching conditions, such as etching time. The resulting array of wires on the master can be efficiently transferred with high fidelity to a plastic substrate coated with a thin layer of adhesive in which the wires are embedded. The master can be reused after polishing, which enables a large number of wires to be made from a single wafer. The above-described "dry" transfer of "top-down" nanowires/microwires represents a new class of transfer methods that offer many advantages over "bottom-up" nanowire "wet" assembly methods in terms of preserving the order and crystal orientation of the wires and the purity of the active surface. The "top-down" fabrication method of the present invention has many attractive features, especially for large electronic (macroelectronics) applications where wires wider than 100-200nm are used. The wire system on the plastic substrate shown in the present invention illustrates by way of example its excellent flexibility and great potential for use in this type of application.
Example 5: solution printing method of printable semiconductor element
The present invention provides a solution printing process capable of transferring and assembling printable semiconductor elements onto large areas of a number of substrates. This aspect of the invention provides a continuous, high-speed manufacturing process suitable for use in a variety of semiconductor devices and device assemblies.
In one method of this aspect of the invention, a printable semiconductor element having a manipulating element is provided. For purposes of this specification, the term "manipulating element" refers to an assembly that enables the controllable manipulation of the position and/or orientation of the printable semiconductor element after the solution phase has been transferred to the substrate surface. In one embodiment, the semiconductor element is provided with one or more steering elements each comprising a layer of material responsive to a magnetic field, an electric field, or both. This aspect of the invention may be used to provide a method for aligning, positioning and/or orienting printable semiconductor elements on a substrate surface by electrostatic and/or magnetostatic forces. Alternatively, the invention provides a method in which the semiconductor element is provided with one or more manipulating elements each comprising a layer of material responsive to a laser-induced momentum transfer process. This aspect of the invention may be used to provide a method of aligning, positioning and/or orienting printable semiconductor elements on a substrate surface by exposing the printable semiconductor elements containing one or more manipulating elements to a series of laser pulses, such as laser tweezers (laser tweezers) methods. Alternatively, the invention provides a method in which the semiconductor element is provided with one or more steering elements each containing a droplet responsive to a force generated by capillary action. The present invention includes methods and devices employing printable semiconductor elements having one or more steering elements or one or more different types of steering elements, e.g., steering elements responsive to different types of fields. The manipulating elements may be provided in various types of printable semiconductor elements of the present invention including, but not limited to, microstructures, nanostructures, microwires, nanowires, microtablets and nanoribbons.
In this aspect of the invention, one or more printable semiconductor elements, each having one or more manipulating elements, are dispersed into a solution or carrier fluid and delivered onto a substrate surface. The transfer of the printable semiconductor elements with the solution/carrier fluid mixture randomly distributes the printable semiconductor elements over the substrate surface. The semiconductor elements randomly distributed on the substrate surface are then moved in a predetermined manner to selected locations and orientations on the substrate surface by applying a force due to the presence of the manipulating elements of the printable semiconductor elements. This aspect of the invention can be used to arrange printable semiconductor elements having manipulating elements in an ordered array, or in a position and orientation corresponding to a selected device or device component configuration. For example, a printable semiconductor element having one or more manipulating elements containing a layer of magnetic material can be moved to a selected location and orientation on a substrate surface by applying a magnetic field having an appropriate intensity and direction profile. In this embodiment, a magnetic field having a selected distribution of intensities and directions may be applied by placing one or more ferromagnetic or electromagnetic elements adjacent to the substrate (e.g., below the substrate surface, on the substrate surface, and/or along the substrate sides) to form a selected distribution of intensities and directions corresponding to the desired assembly, pattern, or structure of the printable semiconductor element or selected device or device component configuration. In this aspect of the invention, the solvent, carrier fluid, or both may be removed by any means known in the art, including by evaporation or by desorption, before, during, or after selective positioning and orientation of the printable semiconductor element by manipulation of the manipulation element.
FIG. 24 provides a schematic diagram illustrating an exemplary method of the present invention for solution printing printable semiconductor elements having manipulating elements that include magnetic tags (magnetic tags). As shown in fig. 24, a plurality of printable semiconductor elements are provided, each having a plurality of magnetic labels comprising thin layers of nickel. In one embodiment, a thin layer of nickel is provided on the surface of the semiconductor structure on a micro-scale or nano-scale. The use of nickel as the steering element in this embodiment is merely exemplary, and any crystalline or amorphous ferromagnetic material including, but not limited to, Co, Fe, Gd, Dy, MnAs, MnBi, MnSb, CrO may be used in these methods2、MnOFe2O3、NiOFe2O3、CuOFe2O3、MgOFe2O3And amorphous ferromagnetic alloys, such as transition metal-metalloid alloys.
As shown in step I of the schematic diagram in FIG. 24, a plurality of printable semiconductor elements, each having a steering element, are dispersed into a solution and cast onto a substrate surface. This step provides printable semiconductor elements onto the substrate surface in a random distribution of positions and orientations. As shown in step ii of the schematic diagram in fig. 24, a magnetic field, preferably having a selected intensity and directional distribution, is then applied to the printable semiconductor element. In the schematic shown in fig. 24, a magnetic field having a selected intensity and directional distribution is applied by placing the poles of one or more magnets on opposite sides of the surface of the substrate on which the printable semiconductor is disposed. Since nickel is a ferromagnetic material, the interaction between the magnetic field and the layer of nickel that makes up the steering element generates a force that moves the printable semiconductor into a desired location and orientation on the substrate surface. In the embodiment shown in FIG. 24, application of a magnetic field orients the printable semiconductor elements into an ordered array characterized by a substantially parallel arrangement of long sides of the printable semiconductor elements. As shown in step iii of the schematic diagram in fig. 24, electrical connections are deposited on the ends of printable semiconductor elements forming an ordered array in a manner that establishes electrical connections and in a manner that maintains the orientation formed by the application of a magnetic field.
FIG. 25 provides several optical images showing the formation of an ordered array of microstructures containing printable semiconductor elements with steering elements comprising thin layers of nickel using the solution printing process of the present invention. The optical image shown on the left panel of fig. 25 corresponds to the surface of the substrate having the printable semiconductor dispersed on the surface of the substrate in the absence of an applied magnetic field. As shown in these images, the printable semiconductor elements are randomly distributed on the substrate surface. The optical image shown on the right panel of fig. 25 corresponds to the surface of the substrate having the printable semiconductor dispersed on the surface of the substrate after application of the magnetic field. Unlike the image shown in the left panel, the optical image corresponding to the situation where a magnetic field is applied indicates that the printable semiconductor elements are present in a manner corresponding to the selected orientation and position of the ordered array. Comparing the images shown in the left and right panels of fig. 25 shows that application of a magnetic field having a selected intensity and directional distribution can generate a force that moves the individual printable semiconductor elements to a selected position and orientation.
It will be understood by those skilled in the art of device fabrication that the location and orientation of the printable semiconductor elements in the right panel of fig. 25 is only one example of an orientation and location that can be achieved using the solution printing method of the present invention. Selecting the appropriate location of the manipulating element on the printable semiconductor element, and selecting an appropriate magnetic field having a selected distribution of strength and direction, can be used to produce almost any distribution of semiconductor element locations and orientations.
Example 6: fabrication of high performance single crystal silicon transistors on flexible plastic substrates
It is an object of the present invention to provide flexible, large electronic, microelectronic and/or nanoelectronic devices and device assemblies comprising printable, high quality semiconductor elements assembled on flexible substrates. In addition, it is an object of the present invention to provide a flexible electronic device, such as a flexible thin film transistor, which exhibits field effect mobility, switching ratio and threshold voltage similar to or exceeding those of thin film transistors manufactured by conventional high temperature processing methods. Finally, it is an object of the present invention to provide bendable electronic devices compatible with efficient high-throughput methods performed at lower temperatures on large-area flexible substrates, such as processing methods performed on plastic substrates at room temperature.
Experimental studies have demonstrated the ability of the present methods, devices and compositions to provide useful large electronic and/or microelectronic devices and device assemblies that exhibit high device performance characteristics in both curved and planar configurations. The results of these measurements show that the present invention provides a dry contact transfer technique with excellent alignment capability that enables flexible thin film transistors to be assembled onto plastic substrates by depositing a variety of high quality semiconductors including single crystal Si ribbons, Ga-As and InP wires, and single-walled carbon nanotubes. For example, the results of these experimental studies indicate that bendable thin film transistors containing spatially tightly defined arrays of dry-transferred printable single crystal silicon elements exhibit high device performance characteristics, such as average device effective mobility estimated in the linear region of 240cm2Vs and the threshold voltage is close to 0V. In addition, these studies show that the thin film transistor of the present invention exhibits bendability (i.e., strain at which failure occurs) comparable to a device made of an organic semiconductor, and exhibits mechanical strength and flexibility when subjected to forward or backward bending.
High performance printed circuits on large area flexible substrates represent a new form of electronic device with a wide range of applications in sensors, displays, medical devices and other fields. The fabrication of the required transistors on plastic substrates represents one of the challenges facing the implementation of these large electronic systems. Several approaches that have been developed over the past few years are all improved low temperature versions of a class of process steps based on the fabrication of conventional silicon-based Thin Film Transistors (TFTs) on glass/quartz substrates. And a directional solidification (i.e., a Si film on SiO using a continuous laser, a focus lamp, an electron beam, or a graphite bar heater) method developed for the production of a single crystal silicon thin film2Upper region melt recrystallization) makes this approach unsuitable for plastic substrates. Laser-based approaches have met with some limited success, but still face challenges in terms of uniformity, throughput, and use of low-cost plastics that require continued experimentation. Direct full wafer transfer of the generated circuits onto plastic substrates can produce some useful devices, but this approach is difficult to scale up to large areas and does not preserve the printing-type fabrication sequence that may be important for low-cost, large-area, large-scale electronic devices. Organic semiconductor materials provide an alternative approach for flexible electronic devices; in which organic-based electronic materials can be naturally integrated with a variety of plastic substrates by room temperature deposition. However, currently known organic semiconductor materials can only achieve moderate device mobility. For example, even high quality crystals of these materials, for n-type and p-type devices, have only 1-2cm, respectively2Vs and 10-20cm2Mobility in the/Vs range.
Other fabrication techniques, such as fluidic self-assembly, separate the high temperature steps of producing high mobility materials from the low temperature processing required to build devices on plastic substrates. However, these methods do not achieve effective control of the tissue or location of the deposit.
Fig. 26A illustrates steps for fabricating an exemplary bendable thin film transistor device of the present invention. First, a photoresist pattern was lithographically defined on the surface of an SOI wafer (Soitec unibond SOI with a 100nm Si top layer and a 145nm buried oxide layer). The photoresist serves as a photoresist using SF6Plasma (Plasmatherm RIE System, SF)6Flow rate of 40sccm, chamber bottom pressure of 50mTorr, RF power of 100W for 25 s) for the silicon top of the SOI waferA mask for dry etching the layer. The buried oxide layer is etched using a concentrated HF solution and the printable single crystal silicon semiconductor element is detached from its substrate (but not completely detached). A flat piece of poly (dimethylsiloxane) (PDMS) sheet was brought into conformal contact with the top surface of the wafer and then carefully peeled off to pick up the attached tape array. The interaction between the photoresist and the PDMS is sufficient to bond the two for very efficient removal.
A plastic sheet of poly (diethyl terephthalate) (PET; thickness-180 μm) coated with indium tin oxide (ITO; thickness-100 nm) was used as the device substrate. Washed with acetone and isopropanol, rinsed with deionized water, and then dried with a stream of nitrogen to clean the plastic sheet surface. Temporary treatment of ITO with oxygen plasma (plasma RIE System, O)2Flow rate of 20sccm, chamber bottom pressure of 100mTorr, RF power of 50W for 10 s) to promote adhesion to the spin-on epoxy dielectric (Microchem SU8-5 diluted with 66% SU8-2000 diluent was spin-coated at 3000RPM for 30 s). The photosensitive epoxy resin is pre-cured on a hot plate for 1min at 50 ℃. PDMS with a printable single-crystal silicon semiconductor element on its surface was brought into contact with a hot epoxy layer and the PDMS was then peeled off to transfer the printable single-crystal silicon semiconductor element onto the epoxy. The results show that the bonding force between silicon and the soft epoxy layer (partly mechanical, caused by the epoxy flow around the printable single crystalline silicon semiconductor element) is stronger than the bonding force between the photoresist and the PDMS stamp. The epoxy layer was fully cured at 100 ℃ for 5min, exposed to UV light transmitted from the bottom side of the transparent substrate for 10s, and then post-baked (post bake) at 115 ℃ for 5min to crosslink the polymer. The photoresist mask (conveniently protected from contamination of the top surface of the printable monocrystalline silicon semiconductor element during the transfer step) was dissolved with acetone and the sample was then rinsed thoroughly with deionized water.
Ti (70 nm; Temescal electron beam evaporator) is deposited on the top surface of the printable single crystal silicon semiconductor element to form source and drain electrodes. Etching was performed through a photoresist mask patterned over Ti (Shipley S1818) (HF: H at 1:1: 10)2O2:DI, run 2 s) determine the geometry of these electrodes. The last step of fabrication involves dry etching through a photoresist mask (SF)6Using the RIE parameters described above) to define islands of silicon (island) in the location of the device. Fig. 26B provides a schematic illustration of the bottom gate device configuration of the thin film transistor, and high magnification and low magnification optical images of a portion of the device array.
FIG. 27A provides the current-voltage characteristics of a bendable thin film transistor of the present invention evaluated using a standard field effect transistor model that ignores the contact effect, and the results show that the effective device mobility in the saturation regime is 140cm2Vs, effective device mobility in the linear region of 260cm2Vs. However, the high impedance (-90 Ω cm) of the schottky contact in these devices has a significant impact on the device response. Fig. 27B provides the transmission characteristics of several devices plotted on a linear scale (left axis) and a logarithmic scale (right axis). The curves in the inset show that the threshold voltages have a narrow distribution around 0V. Small transmission characteristics (for a current of 10V cycle)<4%) indicates a low density of trapped charges at the interface between the silicon (with native oxide) and the epoxy dielectric. The value of the normalized subthreshold slope is small (≦ 13 V.nF/dec.cm)2) The good quality of this interface is confirmed, which may be determined mainly by the interface between silicon and its native oxide. Fig. 27C shows the linear effective mobility distribution of several bendable thin film transistors fabricated by the method of the present invention. Gaussian fitting showed a center value of 240cm2Vs, standard deviation of 30cm2Vs. Some low values are associated with significant defects in the electrodes or other components of the device. The consistency of epoxy dielectrics was investigated using the same substrates and methods used to prepare transistor gate dielectrics to build arrays of 256 (200 x 200 μm) square capacitors. The inset in fig. 27C shows the measured capacitance values. The standard deviation is less than 2% as shown by Gaussian fitting, and the epoxy resin layer is proved to have excellent electrical property and physical property consistency. At different frequencies (between 1kHz and 1 MHz)The capacitance measurement shows that the dielectric constant has a small value of <3%) frequency dependence.
The mechanical flexibility and strength of the bendable thin film transistor of the present invention were investigated by performing forward and backward bending tests. Fig. 28A provides a high resolution scanning electron micrograph of a solution cast ribbon (left inset) to illustrate the significant flexibility of the printable single crystal silicon semiconductor elements. The right inset in fig. 28 shows a picture of an experimental setup used to bend the bendable thin film transistors evaluated in this study. Thicker (-180 μm) plastic substrates were used in these studies in order to maximize the strain induced in the thin film transistors when the plastic sheet was flexed. Fig. 28B shows a small (< 1%) linear change in the epoxy dielectric capacitance when subjected to tensile and compressive strain (see top inset). The bending radius and strain values were calculated using a finite element model of the buckling sheet. Comparing the bending curve of the warped wafer with the curves obtained using the finite element method (for several bending radii) confirms the accuracy of the simulation. The bottom inset in fig. 28B provides the change in device saturation current measured at both gate and drain bias voltages of 4V. The maximum tensile strain at which the flexible thin film crystal can operate appears to be limited by the failure of the ITO gate electrode (failure at tensile strain values of-0.9%). Bendable thin film transistors perform well even at compressive strains as high as 1.4%. This level of bendable performance is comparable to the recently reported pentacene-based organic transistors. The breakdown of the bendable thin film transistors of the present invention is likely to occur only at very high strains, as recently demonstrated by Takahiro et al, micron-scale single-crystal silicon objects etched from the top layer of SOI wafers can withstand very high tensile stresses (> 6%) [ t.namazu, y.isono, and t.tanaka j.memss 9,450(2000) ].
The causes of small variations in output current with strain are not fully known in our device, and known variations in mobility with strain are one, but not all, of the causes of these current variations. Devices of the type we describe in this example can offer new possibilities for studying charge transport in silicon in a mechanically strained state that is not easily achieved when bulk Si wafers are flexed.
In summary, this example demonstrates the high device performance and beneficial mechanical properties of bendable single crystal silicon transistors formed on plastic substrates by the simple and efficient parallel printing method of silicon provided by the present invention. As is known, the performance of these devices exceeds that of the best devices (based on silicon or other materials) with a similar degree of mechanical flexibility. Top-down control of the shape, physical dimensions and composition (e.g., doped or undoped) of printable silicon semiconductors and printing techniques offer many advantages over other approaches. Also, the mechanical flexibility of the resulting device is very good. Furthermore, these same general approaches are applicable to other inorganic semiconductors (e.g., GaAs, GaN, etc.), and can be used to fabricate a variety of flexible microelectronic and large scale electronic devices and device components, such as solar cells, diodes, light emitting diodes, complementary logic circuits, information storage devices, bipolar junction transistors, and FET transistors. Thus, the present methods and devices can be used in a variety of manufacturing applications for producing flexible electronic products.
Example 7: printable heterogeneous semiconductor element and semiconductor device containing the sameDevice with a metal layer
The present invention provides heterogeneous printable semiconductor elements containing multi-material elements, and related devices and device components. The printable heterogeneous semiconductor element of this embodiment, which includes a semiconductor layer having a selected spatial distribution of dopants, provides enhanced functionality in a variety of large scale electronic, microelectronic and/or nanoelectronic devices.
The ability of the present method to produce heterogeneous printable semiconductor elements exhibiting useful electronic properties was demonstrated through experimental studies. Furthermore, the applicability of the inventive method for assembling printable single crystal silicon semiconductor elements with integrated doped regions for contacts into functional devices is demonstrated by the fabrication of flexible thin film transistors containing printable single crystal silicon semiconductor elements.
Large area mechanically flexible electronic systems, i.e. large electronic devices, are attractive for a variety of applications in consumer electronics, sensors, medical devices and other fields. A variety of organic, inorganic and organic/inorganic hybrid materials have been developed as semiconductors for these systems. The production of single crystal silicon micro/nano-elements (collectively referred to as wires, ribbons, platelets, etc. of printable silicon semiconductor elements) using the "top-down" technology approach of the present invention is a proven alternative route for the fabrication of high performance thin film transistors on flexible substrates. This fabrication approach has proven to be suitable for other important semiconductor materials, such as GaAs, InP, GaN, and carbon nanotubes.
An important feature of the approach of the present invention is that it uses a high quality wafer-based source of semiconductor material, the generation and processing of which is decoupled from the subsequent device assembly steps. The separate semiconductor processing and assembly steps facilitate device assembly at relatively low temperatures (e.g., room temperature ± 30 ℃) compatible with most flexible device substrates, such as plastic substrates. The present invention includes methods in which high quality semiconductors are otherwise generated and processed in manufacturing steps that are independent of subsequent manufacturing steps involving assembly of printable semiconductor elements onto flexible substrates. In one embodiment, the invention includes a method in which dopants enter the semiconductor during high temperature processing and the resulting doped semiconductor material is subsequently used to produce printable heterogeneous semiconductor elements that can be assembled into a variety of useful electronic devices. Processing steps that may be used to dope the semiconductor include high temperature processing, as well as processing steps in which the dopant is introduced in a manner that controls its spatial distribution in one, two, or three dimensions (i.e., controls the area of implantation and the depth of implantation). In one method, the semiconductor is selectively contact doped by a spin on doping (spin on doping) process performed at the wafer fabrication level in a step performed independently of the low temperature substrate. Contact doping provides precise control of the spatial distribution of dopants in the semiconductor material, so that subsequent patterning and etching steps can produce high quality printable heterogeneous semiconductor elements with integrated doped regions. Both solution printing and dry contact transfer are ideally suited for assembling these printable heterogeneous elements into devices such as thin film transistors that exhibit the superior device performance and superior flexibility that can be achieved.
FIG. 29A provides a schematic illustration of a fabrication method for producing transistors containing printable hetero-semiconductor elements on a PET substrate. In this embodiment, the printable hetero-semiconductor element comprises crystalline silicon with doped source (S) and drain (D) electrode contacts. The approach shown in fig. 29A dopes selected regions of the silicon top layer of a silicon-on-insulator wafer (SOI; Soitec unibond with a 100nm Si top layer and a 200nm buried oxide layer) using solution processable spin-on dopants (SOD). Thus, spin-on dopant (SOD) provides phosphorous dopant, and spin-on glass (SOG) is used as a mask to control where dopant diffuses into the silicon. The doped SOI provides a source of printable foreign semiconductor elements.
To produce printable hetero-semiconductor elements, we first spin-coat a spin-on-glass (SOG) solution (Filmtronic) onto an SOI wafer and subject it to Rapid Thermal Annealing (RTA) at 700 ℃ for 4 minutes to form a uniform film (300 nm thick). The source/drain windows in the SOG are opened by etching (6: 1 Buffered Oxide Etchant (BOE) for 50 seconds) through the photolithographically patterned layer of photoresist (Shipley 1805). After the photoresist was stripped, sod (filmtronic) containing phosphorus was deposited uniformly by spin coating. RTA5 seconds at 950 ℃ allowed phosphorus to diffuse from the SOD through the photolithographically defined pathways (openings) in the SOG and into the underlying silicon. SOG blocks diffusion in other areas. The wafer was rapidly cooled to room temperature, immersed in BOE for 90 seconds to remove SOG and SOD, and then rinsed thoroughly with DI water to complete the doping process.
Printable heterogeneous semiconductor elements were assembled onto PET plastic substrates coated with indium tin oxide (ITO; 100nm, gate electrode) and epoxy (SU 8; 600nm, gate dielectric) using the method of the present invention. The epoxy not only provides a dielectric but also facilitates transfer of the printable heterogeneous semiconductor elements. Ti (100 nm) source and drain electrodes are formed on the doped contact regions by an aligned photolithography step, followed by an etch back. FIG. 29B shows optical images of several devices having heterogeneous printable semiconductor elements fabricated using the techniques of the present invention.
We estimated the doping level and contact impedance using a standard Transmission Line Model (TLM). Specifically, we measured the amount of ink printed onto a plastic substrate,
Resistance between Ti contact pads with a spacing (L) of 5 to 100 microns and a width (W) of 200 microns on a printable hetero-semiconductor element containing uniformly doped crystalline silicon. The inset in fig. 30A shows an image of the arrangement of printable heterogeneous semiconductor elements and contact pads used to characterize contact resistance. A linear current (I) -voltage (V) curve (not shown) indicates that the contact complies with ohm's law and that the doping level is higher. The dependence of the impedance on L can be determined by RGeneral assembly＝2Rc+(Rs/W) L description, wherein RGeneral assembly(═ V/I) is the impedance between two contact pads, RcAs contact resistance, RsIs the sheet impedance. FIG. 30A shows the normalized impedance RGeneral assemblyCurve of W as a function of L. RGeneral assemblyLinear fitting of W yields Rs228 ± 5 Ω/sq, and RcW is 1.7 +/-0.05 omega cm. Normalized contact resistance RcThe value of W is more than an order of magnitude lower than that observed for undoped printable monocrystalline silicon semiconductor elements treated in a similar manner. Resistivity of about 2.3X 10-3Ω · cm, which corresponds to 1019/cm3If we assume for simplicity that doping is uniform throughout 100nm of doping printable for semiconductor elements. FIG. 30B shows time-of-flight secondary ion mass spectrum (TOF-SIMS), which indicates that the use of patterned SOG as a diffusion barrier (see schematic in fig. 29A) localizes dopants in desired regions in silicon. In the image shown in fig. 30B, bright red indicates that the phosphorus concentration is high.
Fig. 31A-D show measurements corresponding to transistors containing contact doped printable silicon semiconductor elements on an epoxy/ITO/PET substrate. Fig. 31A plots the current-voltage characteristics of the device of the present invention (L ═ 7 μm, and W ═ 200 μm). Effective device mobility (μ) by applying a standard field effect transistor modeleff) In the linear section of 240cm2Vs and in the saturated region is 230cm2Vs. FIG. 31B shows the transmission characteristics of the device of the present invention with a channel length of 2 μm to 97 μm and a channel width of 200 μm. The current ratio from the ON state to the OFF state was 10 in all cases4. When L was changed from 97 μm to 2 μm, the threshold voltage was monotonously changed from-2V to-0V. FIG. 31C provides the measured ON state device impedance (R) at small drain voltageson) The product with W varies with L at different gate voltages. At each gate voltage RonA linear fit of W-L provides information about intrinsic device mobility and contact resistance. In this simple model, RonBy the channel impedance (proportional to L) and the combined contact impedance R associated with the source and drain electrodescIs continuously added (series addition). FIG. 31C shows R as measured by linear fit interceptcNegligible compared to the channel impedance at all channel lengths evaluated. The inset in fig. 31C shows the substrate conductance as a function of gate voltage as determined by the inverse of the slope of the linear fit in fig. 31C. As shown by the inset in FIG. 31C, linear fitting of these data yields intrinsic device mobilities of 270cm2Vs and an intrinsic threshold voltage of-2V.
FIG. 31D compares the effective mobility μ of transistors having undoped and contact doped printable single crystal silicon semiconductor elementseffThe effective mobility mueffDirectly from the linear section (i.e. without subtracting the contact effect)The resulting transmission characteristics are obtained. For undoped devices, μ as the channel length L decreases from 100 microns to 5 micronseffFrom 200cm2the/Vs is rapidly reduced to 50cm2Vs. When the channel length is below-50 microns, the contacts begin to control the performance of the device. In the case of contact doping, the mobility is about 270cm2Vs, change in mobility when the channel length is within the above range<20%, which is consistent with the intrinsic device mobility measured by the inset of fig. 31C. These data provide additional evidence that the effects of contact resistance are negligible for these devices. We note that in addition to the mobility differences, devices with doped contacts are more stable, their performance is more consistent, and less sensitive to processing conditions than devices with undoped contacts.
Mechanical flexibility is an important property of such devices. We performed systematic bending tests on contact doped mus-Si transistors in bending directions that put the device in compression and tension. We also performed some fatigue tests. Details of the experimental set-up are given in example 6. FIG. 32A shows the value μ from the unbuckled state0effThe normalized effective device mobility varies with strain (or bend radius). Positive and negative strain correspond to tension and compression, respectively. For this range of strain (corresponding to a bend radius as low as-1 cm for a 200 micron thick substrate), we observe only a small (in most cases, small) strain<20％）μeff/μ0effThreshold voltage and switching ratio variations. This level of mechanical flexibility is comparable to reported organic and a-Si transistors on plastic substrates. FIG. 32B provides normalized effective mobility μ after hundreds of bend cycles (to a radius of 9.2 mm) to induce a compressive strain in the device of 0 to 0.98%eff/μ0eff. Little variation in device performance was observed; after 350 cycles, μeff/μ0effThe threshold voltage and the switching ratio all varied by less than 20%. These results show the good fatigue stability of the inventive transistor containing the printable hetero-semiconductor element.
This example demonstrates the utility of a spin-on dopant process for contact doped printable single crystal silicon semiconductor elements in transistors on plastic substrates. Scaling analysis (Scaling analysis) showed that the devices produced by the method of the present invention are not limited by contact, which indicates the applicability of the method of the present invention to the fabrication of high frequency silicon devices on plastic substrates. This feature, combined with the very good mechanical flexibility and fatigue stability of the device, makes this contact doped printable heterogeneous semiconductor approach a valuable route to the fabrication of a variety of flexible macroelectronic, microelectronic and/or nanoelectronic systems.
The present invention also provides heterogeneous integration methods for integrating printable semiconductor elements into a variety of devices and device configurations. This aspect of the invention provides a manufacturing approach for producing a variety of devices in which disparate classes of materials are assembled and interconnected on the same platform. The heterogeneous integration process of the present invention uses solution printing and/or dry contact transfer to combine two or more different materials in a manner that establishes their electrical, optical, and/or mechanical interconnectivity. Printable semiconductor elements of the present invention may be integrated with different semiconductor materials or other types of materials, including dielectric, conductor, ceramic, glass, and polymeric materials.
In one embodiment of the concept, heterogeneous integration involves transferring and bonding printable semiconductor elements onto semiconductor die (chips) of different compositions, for example, to assemble systems on die-type devices. In another embodiment, multiple unsupported devices and/or device assemblies are fabricated on different kinds of semiconductor wafers (e.g., silicon wafers and GaN wafers) and then integrated together onto the same receiving substrate, e.g., a receiving wafer. In yet another embodiment, heterogeneous integration involves the introduction of one or more printable semiconductor elements into a complex pre-formed (formed) integrated circuit by assembling printable elements in a particular orientation and effectively interconnecting the printable elements with other components in the integrated circuit. The hetero-integration method of the present invention may employ a number of other techniques known in the art for assembling and joining micro-and/or nano-printable semiconductor elements, including, but not limited to, wafer joining methods, the use of adhesives and intermediate bonding layers, annealing steps (high and low temperature annealing), processes for stripping external oxide layers, semiconductor doping techniques, photolithography, and additional multi-layer processing methods by sequential thin film layer transfer.
Fig. 33 provides an SEM image of a composite semiconductor structure containing gallium nitride microstructures directly bonded to a silicon wafer (100) fabricated using the hetero-integration method of the present invention. To fabricate the combined semiconductor structure shown in fig. 33, GaN was micromachined on a silicon (111) wafer using inductively coupled plasma etching to produce printable semiconductor elements containing GaN, and detached from the silicon using anisotropic wet etching in hot (100 ℃) aqueous KOH. The printable GaN element was removed from the master and printed onto a receiving silicon wafer by dry contact transfer using a PDMS stamp. The bond between the printable GaN element and the silicon wafer is provided by intermolecular attraction without the use of an adhesion layer. The SEM images provided in FIG. 33 demonstrate that the printable semiconductor element and transfer assembly method of the present invention enable heterogeneous integration of different semiconductor materials.
Example 8: fabrication of high performance solar cells with printable semiconductor elements
It is an object of the present invention to provide a method for fabricating solar cells, solar cell arrays, and integrated electronic devices with solar cells on large area substrates with a variety of compositions, including flexible plastic substrates. Furthermore, it is an object of the present invention to provide a hetero-printable semiconductor element capable of providing P-N junctions in a solar cell exhibiting a photodiode response comparable to that of solar cells fabricated by conventional high temperature processing methods.
Experimental studies demonstrate the ability of the printable semiconductor elements of the present invention to provide heterogeneous printable semiconductor elements in solar cells comprising P-N junctions with high quality P-N layer interfaces. Solar cells were fabricated using two different routes for producing P-N junctions, and the photodiode response of devices produced by these routes was evaluated. The experimental results provided by this example demonstrate that the printable hetero-semiconductor elements and associated assembly methods of the present invention can be used to provide high quality P-N junctions in solar cells.
Fig. 34A provides a process flow diagram schematically illustrating processing steps in a fabrication route for a solar cell containing printable P-N segments. As shown in fig. 34A, a high quality semiconductor material, such as a single crystal silicon wafer, is provided and processed in a manner to yield an N-doped semiconductor region directly adjacent to a P-doped semiconductor region. To fabricate a solar cell exhibiting good efficiency, it is preferable to have the P and N regions in physical contact and have an abrupt interface between them where no undoped semiconductor is present. The processed semiconductor material is then patterned and etched to determine the physical dimensions of the printable P-N junctions. Subsequent processing by lift-off techniques produces an overall structure containing a printable P-N junction with a P-doped layer directly adjacent to the N-doped semiconductor layer. The printable P-N segments are then assembled onto a substrate using the solution printing or dry contact transfer methods of the present invention. As shown in fig. 34A, contacts (i.e., electrodes) on the P-and N-doped semiconductor layers can be formed by two routes: depositing onto the monolithic structure prior to subjecting the printable P-N junction to a lift-off process; or deposited onto the printable P-N segments after assembly onto the substrate. In one embodiment, the contacts are formed using vapor deposition of one or more metals.
Fig. 34B shows a schematic diagram of a solar cell device configuration produced by the fabrication approach shown in fig. 34A. A5 micron thick P-doped semiconductor layer with boron dopant was brought into direct contact with two N-doped semiconductor layers with phosphorus dopant. The contacts are directly disposed on the N-doped layer and on the two P-enriched doped layers in contact with the P-doped semiconductor layer forming the P-N junction. The introduction of phosphorus and boron doped contact regions overcomes the contact resistance of the system. Fig. 34C provides a current-bias curve of the photodiode response observed upon illumination of a solar cell device having the configuration shown in fig. 34B. As shown in fig. 34C, when the solar cell is irradiated and a positive bias is applied, a current is generated.
Fig. 35A provides a process flow diagram schematically illustrating processing steps in an alternative fabrication approach to produce a semiconductor layer containing P-doped and N-doped that can be printed independently. As shown in fig. 35A, a high quality semiconductor material, such as a single crystal silicon wafer, is provided and processed in a manner that results in discrete N-doped and P-doped semiconductor regions. The processed semiconductor material is then patterned and etched to determine the physical dimensions of the separate P-doped and N-doped layers. Subsequent processing by lift-off techniques produces a separately printable P-doped semiconductor layer and/or a separately printable N-doped semiconductor layer. P-N junctions are then assembled by printing a first doped semiconductor element (N-doped or P-doped) onto a second doped semiconductor element having a different composition such that the second doped element is in contact with the first doped element. In one embodiment, the P-N junction is assembled by printing P-doped and N-doped semiconductor layers, which may be achieved, for example, by printing a first doped semiconductor layer onto a substrate and then printing a second doped semiconductor layer onto the first doped semiconductor layer. Or the assembly of PN junctions may be performed by printing the first doped semiconductor layer onto a substrate containing the second doped semiconductor layer. Any P-doped layer and N-doped layer orientation that provides a good interface between these elements can be used in the present invention, including but not limited to an orientation in which a first doped semiconductor element is in contact with the top surface of a second doped semiconductor element.
The bonding of the N-and P-doped printable semiconductor elements can be achieved by wafer bonding techniques well known in the art (see, e.g., "Materials Science and engineering R", Jan hasma and g.a.c.m. springs, 37, pages 1-60 (2002)). Optionally, the P and N doped semiconductor layers are treated before, during or after printing to strip off any outer insulating layer thereon, such as an outer oxide layer, that may prevent the creation of a P-N junction with a high quality interface between the P-N doped layers. Optionally, in certain embodiments, any water present on the doped semiconductor surfaces to be joined is removed, e.g., by heating, prior to contacting the elements to improve the quality of the interface in the P-N junction. The assembly of the first and second doped semiconductor elements may be performed using the solution printing or dry contact transfer method of the present invention. Optionally, the fabrication approach of this aspect of the invention may further include the step of annealing the P-N junction to establish a good interface between the P-doped and N-doped semiconductor layers. The annealing is preferably performed at a temperature sufficiently low not to significantly damage the substrate supporting the P-N segments, for example, at a temperature below about 200c for P-N segments assembled to a plastic substrate. Alternatively, the P-N junctions may be annealed in processing steps that do not involve the substrate. In this embodiment, the annealed P-N segments are allowed to cool and then assembled to the substrate by solution printing or dry contact transfer. As shown in fig. 35A, contacts (i.e., electrodes) on the P-and N-doped semiconductor layers can be formed by two routes: depositing onto the freestanding doped semiconductor layer prior to performing the lift-off process; or deposited onto printable P-N segments after assembly onto a substrate. In this embodiment, the contacts are formed using vapor deposition of one or more metals.
Fig. 35B shows a schematic view of a solar cell device produced by printing an N-doped semiconductor layer onto a P-doped semiconductor layer of a silicon wafer. The combined structure is annealed to a temperature of about 1000 ℃ to produce a P-N junction having a high quality interface between the N-doped semiconductor layer and the P-doped semiconductor layer. Electrical contacts are provided directly on each doped semiconductor layer by vapor deposition of an aluminum layer. Fig. 35C shows a top-view SEM image of the solar cell schematically depicted in fig. 35B. The SEM images show the N-doped semiconductor layer on the P-doped semiconductor layer and also show the aluminum contacts on each doped semiconductor layer. Fig. 35D provides a current-bias curve illustrating the photodiode response of the solar cell shown in fig. 35C. As shown in fig. 35D, when the solar cell is illuminated and a positive bias is applied, a current is generated. Fig. 35E provides a plot of photocurrent versus time after illumination of the solar cell shown in fig. 35C with different light intensities.
The physical dimensions of printable heterogeneous semiconductor elements, such as printable doped semiconductor elements and printable P-N junctions, that can be used in the solar cells of the present invention depend on a number of variables. First, the thickness must be large enough so that a significant proportion of incident photons per unit area are absorbed by the P-N junctions. Thus, the thickness of the P-doped and N-doped layers depends at least in part on the optical properties of the underlying semiconductor material, such as its absorption coefficient. For certain beneficial applications, the printable silicon element has a thickness of about 20 microns to about 100 microns and the gallium arsenide element has a thickness of about 1 micron to about 100 microns. Second, in certain device applications, the thickness of the printable elements must be small enough so that they exhibit a degree of flexibility that is beneficial for the particular device application. Using thin (< 100 microns) elements enables flexibility even for brittle materials such as single crystal silicon semiconductors and reduces manufacturing costs due to the need for less raw material. Third, the surface area of the printable element should be large enough to capture a significant number of incident photons.
Dopants can be introduced into a semiconductor material by any method that results in a high quality doped semiconductor material with a well-defined spatial distribution, including methods that use spin-on dopants (see, e.g., example 8). Exemplary methods of introducing dopants into semiconductor materials demonstrate control of the spatial distribution of the dopants in one, two or three dimensions (i.e., depth of incorporation and area of the semiconductor layer doped with the dopant). An important advantage of the fabrication approach shown in fig. 34A and 35A is that dopant incorporation and activation can be performed independently under clean room conditions and at high temperatures. However, subsequent fabrication and assembly of printable doped semiconductor elements and/or P-N junctions can be performed at lower temperatures and under non-clean room conditions, thereby enabling high throughput solar cell fabrication on a variety of substrate materials.
Example 9: stretchable circuit and electronic deviceDevice with a metal layerManufacture of
The present invention provides stretchable circuits, electronic devices and arrays of electronic devices that have good performance when stretched, flexed or deformed. Similar to the stretchable semiconductor element described in example 2, the present invention provides a stretchable circuit and an electronic device comprising a flexible substrate having a supporting surface in contact with a device, an array of devices, or a circuit having a curved inner surface, for example, a curved inner surface in a wave configuration. In this structural arrangement, at least a portion of the curved interior surface of the device, device array or circuit structure is bonded to the support surface of the flexible substrate. Unlike the stretchable semiconductor of example 2, however, the device, device array or circuit of this aspect of the invention is a multi-component element containing a plurality of integrated device components, such as semiconductors, dielectrics, electrodes, doped semiconductors and conductors. In one exemplary embodiment, flexible circuits, devices, and device arrays having a net thickness of less than about 10 microns contain a plurality of integrated device components, at least a portion of which have periodic wave bending structures.
In one useful embodiment of the invention, an unsupported circuit or device is provided that contains a plurality of interconnected components. The inner surface of the circuit or device is in contact with and at least partially bonded to the pre-strained elastomeric substrate in the expanded state. The pre-straining may be accomplished by any means known in the art, including, but not limited to, rolling and/or pre-bending the elastomeric substrate, and the elastomeric substrate may be pre-strained by expansion along one axis or expansion along multiple axes. The attachment may be achieved directly by covalent bonding or van der waals forces between at least a portion of the interior surface of the circuit or device and the pre-strained elastomeric substrate, or by the use of an adhesive or an intermediate tie layer. After the pre-strained elastomeric substrate is attached to a circuit or device, the elastomeric substrate is at least partially relaxed to a relaxed state, which causes the inner surface of the printable semiconductor structure to flex. The curvature of the inner surface of the circuit or device in certain useful embodiments produces a curved inner surface having a periodic or non-periodic waveform. The invention includes embodiments in which all of the components making up an electronic device or circuit are in the form of periodic or non-periodic waveforms.
The periodic or non-periodic waveforms of the stretchable circuit, electronic device or array of electronic devices allow them to adapt to a stretched or flexed configuration without significant strain on the individual components of the circuit or device. This aspect of the invention provides stretchable circuits, electronic devices and arrays of electronic devices with beneficial electrical properties when present in a flexed, stretched or deformed state. The period of the periodic waveform formed by the method of the present invention may vary with the following parameters: (i) the net thickness of the collection of integrated components that make up the circuit or device and (ii) the mechanical properties, such as young's modulus and flexural rigidity, of the materials comprising the integrated device components.
Figure 36A shows a process flow diagram of an exemplary method of producing a stretchable thin film transistor array. As shown in fig. 36A, unsupported printable thin film transistor arrays are provided using the present technology. The thin film transistor array was transferred onto the PDMS substrate by dry contact transfer so that the inner surface of the transistor was exposed. The bare inner surface is then contacted with a room temperature cured, pre-strained PDMS layer that exists in an expanded state. Subsequent sufficient curing of the pre-strained PDMS layer bonds the inner surfaces of the transistor to the pre-strained PDMS layer. The pre-strained PDMS layer is allowed to cool and assume an at least partially relaxed state. Relaxation of the PDMS layer introduces the periodic wave structure into the transistors in the array, making it stretchable. The inset in figure 36A provides an atomic force micrograph of an array of stretchable thin film transistors made by the method of the present invention. Atomic force micrographs demonstrate periodic wave structures that provide good electrical properties in the stretched or deformed state.
Figure 36B provides an optical micrograph of the stretchable thin film transistor array in a relaxed and stretched state. Stretching the array in a manner that results in about a 20% net strain on the array does not fracture or damage the thin film transistors. The transition of the transistor from the relaxed state to the strained state is observed as a reversible process. Figure 36B also provides leakage current-drain voltage curves for several potentials applied to the gate electrode, which indicate that the stretchable thin film transistor exhibits good performance in both the relaxed and stretched states.
Example 10: large area, selective transfer of printable micro-structured silicon (μ s-Si): obtaining a flexible substrate supportPrinting-based approach to high performance thin film transistors
The method, apparatus and apparatus assembly of the present invention provide a new print-based fabrication platform for producing high performance integrated microelectronic devices and device arrays. Advantages of the present invention over conventional processing methods in the technical approach to large scale electronic and microelectronic devices include compatibility with a variety of substrate materials, physical dimensions, and surface morphology. In addition, the printing-based approach of the present invention enables a low-cost, high-efficiency manufacturing approach for producing integrated microelectronic devices and device arrays on large area substrates that is compatible with existing high-throughput printing devices and techniques.
Advanced information technology that shapes modern society structures is critically dependent on the use of microelectronic devices, i.e., microelectronic devices involving higher and higher integration densities. Beginning with early circuits (ICs) including less than 4 transistors in the late fifties of the twentieth century, ICs in the prior art integrated millions of transistors in substantially the same size packages. However, much attention has been directed to developing new device form factors (device form factors) that incorporate the performance of semiconductor devices into structures that include large areas and/or flexible material supports using manufacturing methods that seek to reduce costs while maintaining high levels of device performance. Such device technology finds application in active matrix pixel display driving and RF identification tags. Recent reports detail models for constructing such circuits using solution processingIn particular, models of circuits based on semiconductor Nanowires (NWs) or mesh nanotubes. While functional devices prepared in this manner are promising, they typically have characteristics that are significantly below the device performance levels of conventional high temperature semiconductor processing approaches. For example, Thin Film Transistors (TFTs) prepared using solution processing have reported field effect mobilities of 2cm2from/Vs to-40 cm2Vs.
In one aspect, the present invention provides a "top-down" fabrication strategy using micro-structured single crystal silicon (μ s-Si) ribbons made from silicon wafers on insulator for use in ultra-high performance TFTs. The fabrication techniques are compatible with a variety of useful semiconductor materials and have been successfully adapted to other industrially useful semiconductor materials including GaN, InP, and GaAs.
In this example, we present a number of important processing steps for implementing this technique, including manufacturing methods that achieve selective transfer and accurate positioning of silicon ribbons across large substrate areas, and general printing methods suitable for rigid (e.g., glass) and flexible plastic substrates. In this example, we report specifically two methods that can be used to selectively remove μ s-Si from an SOI wafer and then transfer it onto a plastic substrate in the form of the formed pattern. For simplicity, the method is divided into method I (FIG. 37A) and method II (FIG. 37B), which use different adhesive bonding mechanisms to achieve a μ s-Si print-based pattern transfer. Method I utilizes a physical bond between a stamp molded from Sylgard3600 poly (dimethylsiloxane) (PDMS), a new experimental, high modulus PDMS product offered by Dow Corning, inc, and a μ s-Si object. Method II uses a recently developed masterless soft lithography (master soft lithography) technique to chemically bond μ s-Si to PDMS coated substrates.
FIG. 37A provides a schematic diagram showing the process of the present invention (method I) for patterning a μ s-Si element onto a plastic substrate. In this embodiment, the plastic substrate comprises a poly (diethyl terephthalate) (PET) sheet. Use markThe quasi-lithography technique develops a peanut-like photoresist pattern on the SOI substrate. Plasma etching and subsequent photoresist stripping produce a μ s-Si "peanut" that rests on a buried oxide layer. The sample was then incompletely etched using HF to obtain an undercut peanut-shaped pattern supported only by the residual oxide layer present on the dumbbell-shaped ends of the mus-Si. The SOI wafer was then laminated with a hard 3600PDMS stamp molded with features corresponding to the latent image of the desired pattern transfer. The raised features of the stamp correspond to regions where μ s-Si is selectively removed from the SOI surface due to strong self-adhesion with PDMS. After the stamp was peeled off the SOI wafer, it was placed in contact with a poly (diethyl terephthalate) (PET) sheet coated with Polyurethane (PU) that had been partially cured with a UV lamp. The bar coating technique can be used to deposit PU bondcoat to ensure coating thickness over large areas (600 cm)2) Uniform on the plastic substrate. The μ s-Si on the stamp was then placed in contact with the PU-coated side of the plastic sheet and a second UV/ozone exposure was performed from the PET side of the sandwich to fully cure the PU and enhance its bonding with the μ s-Si. The stamp was peeled off the plastic substrate, causing the microstructure silicon to separate from the PDMS, thereby completing the transfer to the PU-coated substrate.
FIG. 37B provides a schematic diagram illustrating an alternative inventive process (process II) for patterning a μ s-Si element onto a plastic substrate. In this embodiment, the plastic substrate comprises a poly (diethyl terephthalate) (PET) sheet. A recently reported Decal Transfer Lithography (DTL) technique uses an unshaped, photochemically processed, thick slab of PDMS to give the bond a spatially modulated intensity. A UV/ozone (UVO) treated pattern was formed on the entire surface of a thick piece of conventional Sylgard184PDMS using a microreactor photomask, thereby forming a high spatial resolution UVO modified pattern. After exposure, the PET coated with photochemically modified PDMS was placed in contact with the peanut-like SOI wafer and heated to 70 ℃ for 30 minutes. The same procedure as in method I was used to fabricate peanut-shaped patterns on SOI wafers(see FIG. 37A), plus SiO after the HF etch step2The film (5 nm) was evaporated onto the surface. The SiO2The layer contributes to a strong chemical bond with the PDMS. After heating, the PDMS was peeled off the SOI and the μ s-Si was transferred in a pattern to the UVO modified region of the PDMS.
FIG. 38A shows a design of a so-called peanut-like μ s-Si object for use in the method of the invention. The optical image inset in FIG. 38A shows optimized HF etch conditions where the buried oxide under the via is removed and the SiO of the sacrificial layer is removed2And part remains. The peanut shape is particularly beneficial because the ends of the structure are slightly wider than the body. Etching the underlying oxide layer in an HF solution can be time optimized to allow complete removal of the central underlying oxide layer while leaving the SiO of the sacrificial layer portion2Remaining on one of the two ends (the dumbbell-shaped area shown in the inset of fig. 38A). It is this residual SiO2The layer fixes μ s-Si in its initial position. Without this oxide bridge layer, the order of μ s-Si grown on SOI wafers by photolithography would be easily lost. Fig. 38B illustrates an example of losing this order when the Si object is over-etched in an HF solution. As shown in fig. 38B, when the sample was over-etched in the HF solution, the Si object began to float in the HF solution. When μ s-Si is removed from the SOI wafer by method I or method II, a fracture occurs at the edge of the sacrificial region.
38C, 38D, 38E, and 38F show a series of photomicrographs depicting the performance of each μ s-Si transfer step performed using method I. FIG. 38C shows μ s-Si on SOI wafers after optimized HF undercut etching. FIG. 38D shows the SOI wafer after a portion of the μ s-Si has been removed from the PDMS stamp. As shown in fig. 38D, the PDMS stamp removed a portion of the μ s-Si, thereby preserving the integrity of the adjacent regions on the SOI. Since the unused microstructure silicon objects on the SOI wafer remain in their original positions, they can be picked up by the stamp and transferred in a subsequent printing step (as described below). FIG. 38E shows the μ s-Si structure transferred onto the PDMS stamp. The missing centers at each end of the μ s-Si ribbon show the pattern of breaks that occur during the transfer of the microstructured silicon from the SOI to the PDMS stamp. FIG. 38F shows typical results of a μ s-Si secondary transfer (this time from a PDMS stamp to a PU-coated plastic substrate) where μ s-Si adhered to the PU is supported on the plastic.
Multiple transfers are possible from a small PDMS stamp to a larger plastic surface. FIGS. 39A and 39B provide optical images of the selective transfer of μ s-Si onto PU/PET sheets through a 3600PDMS stamp. In large area (15 × 15 cm) transfer as shown in fig. 39A, μ s — Si was sparsely transferred onto a plastic substrate by multiple transfers using an 8 × 8cm stamp. The individual pixels in the image have the same arrangement as shown in fig. 38F and follow the same procedure described in fig. 38C-38E. The inset of fig. 39B shows a more complex molded form, i.e., the text of "DARPA macro E" consisting of peanut-like μ s-Si objects smaller than the object size highlighted in fig. 38C-38E. High fidelity of the transferred pattern is illustrated by the quality of the object (circle of inset) forming the letter "a" as shown in fig. 39B. These data indicate that only the areas directly touched by the stamp are ultimately transferred to the plastic substrate. We note that there are two reasons why such transfer is more difficult when using conventional Sylgard184 PDMS. First, Sylgard184 will sag when the separation distance between the components exceeds 20 times the height of the components. The embodiments shown in this specification take advantage of this design criterion and exclude high fidelity transfer using low modulus polymers. Second, we also found that Sylgard184 did not have sufficient adhesion to pick up each μ s-Si peanut from the SOI wafer at some times, and defects were observed in some applications using stamps made from this polymer. 3600PDMS from Dow Corning also did not sag significantly at an aspect ratio of 1:200 and, perhaps more importantly, adhered stronger to μ s-Si objects than 184 PDMS.
An example of μ s-Si transfer using method II is shown in FIGS. 39C and 29D. Fig. 39C is an optical micrograph of a fragment of a Sylgard184 coated PET substrate to which μ s-Si has been chemically bonded and which will subsequently be transferred. The higher magnification image of μ s-Si transferred in this manner is shown in FIG. 39D. It should be noted that the peanut shape used in this example is relatively small in size, with a band width of 25 μm. Interestingly, we found that these smaller features have different breaking points after removal from the SOI wafer. In the enlarged fig. 39D, it can also be noted that the PDMS surface is no longer flat. The reason for this is that a portion of the PDMS, which in turn is transferred to the SOI, peels off the bulk in the contact area activated by the UVO treatment pattern where the PDMS sags and contacts the wafer surface between the peanut-like objects.
FIG. 40A illustrates an exemplary device geometry for a device fabricated using peanut-like μ s-Si transferred by method I. To construct these devices, a sheet of PET coated with Indium Tin Oxide (ITO) was used as the substrate. ITO was used as the gate electrode and diluted SU-85 (measured capacitance of 5.77 nF/cm) was used2) As a gate dielectric. FIG. 40B provides μ s-Si TFTs at multiple gate voltages (V)g-2.5V to 20V). These plastic-supported peanut-like μ s-SiTFTs exhibited accumulation-mode n-channel transistor behavior, as shown in FIG. 40B. As shown in the inset of fig. 40c, the channel length of this device is 100 μm and the width of the device is 400 μm. FIG. 40C shows the voltage at constant source-drain voltage (V)sd1V), which indicates an effective mobility of 173cm2Vs. The inset in fig. 40C shows an optical micrograph of an actual device of the present invention. The transfer characteristics showed an effective mobility of 173cm2Vs time threshold voltage (V)th) It was-2.5V. These values are consistent with the expected performance characteristics of such bottom gate structures 100nm thick.
The selective transfer method described in this embodiment provides an efficient way to transfer micro-structured silicon from an SOI wafer to a flexible, large-scale system. Unlike conventional solution casting methods, using these techniques, the microstructured silicon object can be transferred from the SOI master wafer with precise positioning and in a manner that minimizes waste. The mechanical properties of the new 3600PDMS studied in this application show that it has a number of important advantages compared to the commercial Sylgard184PDMS resin, in particular its dimensional stability and higher surface adhesion properties. It has also been demonstrated that printing techniques are compatible with the construction of large systems containing high-performance μ s-Si thin film transistors.
Experiment of
Method I
The manufacture of μ s-Si bodies was carried out using commercially available SOI wafers (SOITEC, P-type, top layer Si thickness 100nm, resistivity 13.5-22.5 ohm cm, 145nm buried oxide). The SOI wafer was patterned into the desired peanut-like geometry (center length: 200 μm, width: 25 μm, diameter of peanut: 50 μm) using photolithography (Shipley 1805 photoresist). Then dry etching (Plasmatherm RIE system, SF)6Flow rate of 40sccm, 50mTorr, RF power 100W, 45 s) to remove the bare silicon. Followed by etching of the underlying SiO layer in HF (49%) solution2For 80 seconds. For the 3600PDMS stamp of method I, a custom made PDMS (Dow Corning, 3600, elastic modulus 8 Mpa) was mixed with Sylgard184 (Dow Corning, elastic modulus 1.8 Mpa) in a one-to-one ratio and cured using standard soft lithography patterning. Using a UV light source (ozone activated mercury lamp, 173. mu.W/cm)2) The PU film adhesive layer was cured (Norland Photoadhesive, No. 73). These latter films were coated onto a PET substrate (180 μm thick, polyester film, southwall technologies) using a bar coating method (Meyer bar, RD speciality).
Method II
For method II, the peanut-like objects used had dimensions (middle length: 10 μm, width: 2 μm, end diameter: 5 μm) smaller than those used for method I. These structures were produced using a similar fabrication method except that the RIE etch time was reduced to 25 seconds (to minimize sidewall etching) and the buried oxide layer was etched in a concentrated (49%) HF solution for 30 seconds. When the latter etching step was completed, the sample was rinsed in a water bath and dried in an oven at 70 ℃ for 5 minutes. Then will beSiO of (2)2The layers were evaporated onto the sample (Temescal FC-1800E-beam evaporator). To attach a thin PDMS layer to a PET substrate, a layer of PU was first spin coated onto the PET at 1000rpm for 30 seconds and exposed to UVO (173W/cm)2) For 4 minutes. The PDMS film was then spin coated onto the PU at 1000rpm for 30 seconds and thermally cured at 65 ℃ for three hours.
The selective area soft lithography patterning method included placing the unpatterned PDMS side of the coated PET substrate in contact with the patterned side of the UVO photomask. The microreactor mask was fabricated using the method described by Childs et al. The pattern consisted of two interlocking rectangular arrays (1.2X 0.6 mm). The PDMS was then irradiated through a UVO photomask at a distance of 3cm from the mercury bulb (UVOCS T10X 10/OES) for 3 minutes. After exposure, the PDMS stamp was peeled off the UVO photomask and the PDMS exposed side was placed in contact with an SOI wafer containing peanut-like objects. After heating at 70 ℃ for 30 min, the PDMS was slowly peeled off using tweezers, removing the μ s-Si fragment corresponding to the irradiated area.
Device fabrication
SU-85 diluted with 66% (v) SU-82000 diluent was spin coated onto the ITO side of the coated PET samples and spin coating was performed at 3000rpm for 30 seconds. The SU-8 epoxy was then pre-cured on a hot plate at 60 ℃ for-1 minute. The PDMS stamp with μ s-Si on the surface (method I) was then contacted with the epoxy layer for 30 seconds and peeled off to transfer μ s-Si to the epoxy. The SU-8 dielectric was then allowed to fully cure at 115 ℃ for 2 minutes, exposed to UV10 seconds, and post-baked at 115 ℃ for 2 minutes. Metal (40 nm) for titanium contact was then added by e-beam evaporation and patterning of the source-drain regions was performed using standard photolithography in combination with etching using a 1% HF solution.
Example 11: bendable GaAs metal semiconductor field effect formed by printing GaAs wire array on plastic substrateTransistor with a metal gate electrode
The fabrication method of the present invention has versatility in the metals that can be assembled and integrated into useful functional devices and device components. In particular, the method of the present invention is applicable to the fabrication of semiconductor-based microelectronics and large-scale electronic devices using a variety of high-quality semiconductor materials, including non-silicon materials. To demonstrate this capability of the inventive method, bendable metal-semiconductor field effect transistors (MESFETs) with GaAs nanowires were fabricated using the inventive method and their electrical and mechanical properties were evaluated.
Field effect transistors formed with high quality single crystal semiconductor nano-and microstructures on large area mechanically flexible plastic substrates are of great interest in a variety of applications in displays, sensors, medical devices and other systems. Various approaches have been demonstrated to transfer high quality semiconductor materials (e.g., silicon nanowires, micro-ribbons, platelets, etc.) onto plastic substrates to obtain mechanically flexible metal-oxide-semiconductor field effect transistors (MOSFETs). The invention can be used to fabricate bendable metal-semiconductor field effect transistors (MESFETs) on plastic substrates using GaAs microwires (a class of materials known as micron-structure GaAs or μ s-GaAs) that have integrated ohmic source/drain contacts. Among these methods, high quality bulk GaAs wafers provide the starting material for "top-down" fabrication methods to form micro/nanowires. Furthermore, transfer techniques using elastomeric stamps integrate an ordered array of these lines with a plastic substrate. The electrical and mechanical measurements of MESFETs formed in this manner indicate that good performance and excellent flexibility can be obtained using the method of the present invention.
Fig. 41 provides a schematic illustration of the main steps in fabricating a MESFET on a flexible plastic substrate (poly (diethyl terephthalate) (PET)) using an array of single crystal GaAs wires with epitaxial (epitaxial) n-type channel layers and integrated AuGe/Ni/Au ohmic contacts. N-type GaAs layer (concentration 4.0X 10) with epitaxial Si doping17/cm3IQE Inc., Bethlehem, Pa. (100) semi-insulating GaAs (SI-GaAs) wafers provide the starting material for the production of microwires. Photolithography with metal coating by electron beam (and/or thermal) evaporationThe cloth process produced an array of narrow metal strips (2 μm wide and 13 μm apart) comprising a conventional multilayer stack, AuGe (120 nm)/Ni (20 nm)/Au (120 nm), used as ohmic contacts. The wafers were passed through N in a quartz tube at elevated temperature (i.e., 450 ℃ C. for 1 minute)2Annealing is performed under the conditions of (1) to form ohmic contact with n-GaAs.
Confining the metal strip to GaAs: () The crystal orientation enables the production of microwires (with integrated ohmic contacts) using a top-down fabrication approach. As shown in the processing step in fig. 41, a pattern of photoresist (3 μm wide) is determined on the metal strip; the gaps between the lines are located between adjacent metal strips. These gaps allow for etchant (H at a volume ratio of 1:13: 12)3PO4(85wt%):H2O2(30wt%):H2O) can diffuse to the GaAs surface to anisotropically etch the GaAs. The photoresist protects the interface between the ohmic strips and the GaAs from exposure. The anisotropic etch creates a reverse mesa and undercuts along the GaAs surface, forming GaAs lines with triangular cross-section and narrow width that are peeled off the mother wafer. Undercutting produces GaAs lines down to the micrometer and/or nanometer scale by controlling the photoresist geometry and etch time. Each line has two ohmic strips separated by a gap that determines the channel length of the resulting MESFET. As shown in process step ii in fig. 41, a flat elastomeric poly (dimethylsiloxane) (PDMS) stamp was brought into line contact with the GaAs coated photoresist, forming van der waals bonds between the PDMS and the hydrophobic surface of the photoresist. This interaction causes all GaAs wires to be removed from the wafer to the PDMS surface when the stamp is peeled off the master wafer, as shown in step iii in fig. 41. The transfer process preserves the spatial organization (i.e., the arrayed array) of the lines defined by the photoresist. A PDMS stamp with GaAs lines was then placed on a PET sheet covered with a thin layer of liquid polyurethane (PU, NEA121, Norland Products, Inc., Cranbury, N.J.) (a light curable polymer)And (6) laminating.
As shown in process step iv in FIG. 41, the PU was cured, the PDMS stamp was peeled off and passed through O2Reactive ion etching (RIE, Uniaxis790, Plasma-Therm RIE system) removed the photoresist, resulting in ordered GaAs lines with bare ohmic stripes embedded on the surface of the PU/PET substrate. During the transfer process, the photoresist serves not only as an adhesive layer but also as a protective film that prevents the surface of the GaAs line and ohmic contacts from being contaminated. Further photolithographic processing performed on the PU/PET substrate identified the electrodes (250 nm Au) connecting the ohmic strips to form the source/drain electrodes, and the gate electrodes (Ti (150 nm)/Au (150 nm)) as shown in processing step v in fig. 41. The resulting MESFET array is mechanically flexible due to the flexibility of the PU/PET sheet (thickness 200 μm) and GaAs wire (width and thickness less than 5 μm).
Fig. 42A provides a schematic diagram showing a cross-section of a GaAs wire based MESFET geometry on a plastic substrate (PU/PET). The source/drain electrodes form ohmic contacts with the n-GaAs layer. The gate electrode forms a schottky contact with the layers. The strong interaction between the cured PU and GaAs wire sidewalls links the wires to the PU/PET substrate. With this geometry and using the aforementioned processing approach, the active n-GaAs layer (i.e., the transistor channel) never comes into contact with any polymeric material other than photoresist. The Ti/Au gate electrode forms Schottky contact with the surface of the n-GaAs; the potential barrier enables the application of a relatively negative voltage (i.e., < 0.5V) to modulate the current between the source and drain electrodes as in conventional MESFETs, a representative image of two MESFETs based on GaAs lines on a plastic substrate fabricated according to the process flow diagram of fig. 41 is shown in fig. 42B, each using an array of 10 GaAs lines. These lines have a well-aligned orientation and a uniform width of-1.8 μm. Gold pads 150 μm wide and 250 μm long connect the ohmic strips on the 10 GaAs lines to form the source and drain electrodes of each individual MESFET. A Ti/Au strip 15 μm wide and deposited in a 50 μm gap (transistor channel) provides the gate electrode. These strips are connected to larger metal pads for probing (probing). The contrast difference between the metal on the wire and the metal on the plastic (contrast difference) is likely due to the surface roughness on the PU created during the RIE etching of the photoresist. FIG. 42C shows an image of a 2cm by 2cm PET sheet with hundreds of transistors, which clearly shows its flexibility. Multiple printing steps and/or line fabrication runs can be used to produce a large number of lines patterned across a large area plastic substrate. Various parameters, such as the width of the GaAs line, the width of the source/drain electrodes, the channel, and the gate electrode length, can be readily adjusted to produce a MESFET with a variety of desired output characteristics.
The DC performance of the transistor was characterized to evaluate its electrical and mechanical properties. FIGS. 43A, 43B and 43C provide results for a GaAs MESFET similar to the MESFET shown in FIG. 42B with a channel length of 50 μm and a gate length of 15 μm. Fig. 43A shows the current-voltage (between drain and source electrodes) curve for gate voltages between 0.5V and-2.0V (step size of 0.5V). I isDS-VDSThe characteristics are comparable to conventional wafer-based MESFETs constructed with n-type GaAs layers and standard technology, i.e., IDSAt high VDSRegion is saturated, and IDSDecreases with decreasing gate voltage. In the linear region, VGSChannel impedance R at 0VChannel6.4k Ω. FIG. 43B shows the effect at different VDSThe following measured transfer characteristics (i.e., I) for the GaAs MESFET of the present inventionDS-VGS). All curves have a minimum at the same gate voltage, i.e. -2.65V. At high forward gate voltage IDSIs due to leakage current from the gate electrode to the source electrode, which is caused by the schottky contact in that segment. FIG. 43C shows a cross-sectional view at VDS4V hour pair (I)DS)1/2-VGSThe resulting transmission curve is plotted and clearly shows the expected linear relationship for the MESFET. I isDS0.19mA and VDSThe pinch-off voltage and transconductance at 4V are respectively Vp2.65V and gm0168 mus. These characteristics indicate that transistors fabricated on PET substrates have similar performance to typical GaAs MESFETs fabricated on wafers by conventional approaches.
For many target applications under consideration, mechanical flexibility represents an important parameter for devices on plastic substrates. We tested the transistors by bending the supporting PET sheet. Fig. 44A and 44B show the current-voltage characteristics of the gate modulation of a GaAs wire-based MESFET on a flexible PET substrate in two cases: (A) before bending; (B) after bending to a bending radius of 8.4 mm. These figures compare the performance of the transistor before and after flexing the substrate to a radius of 8.4mm, i.e. a corresponding surface strain of 1.2% (in this case tensile), for a 200 μm thick substrate. The results show that the transistors can withstand these high strains without failure. In fact, in this example, VGSThe saturation current at 0V was increased by-20%. Fig. 44C shows the current-voltage characteristics of the gate modulation of a GaAs wire-based MESFET after relaxation of the flexed substrate to its flat, unflexed state. Comparing fig. 44C with fig. 44A shows that the transistor regained its original state performance after the strain was released, i.e., the substrate was again flattened. FIG. 44D shows the strain at V during three bending (with different surface strains)/relaxation cyclesDS4V and VGSWhen equal to 0V, IDSShows that these MESFETs remain intact after multiple bending cycles that change the tensile strain of the device between 0% and 1.2%, without significant change in their performance: (<20%). The observed systematic variation in strain may be related to the displacement of the GaAs wire lattice and its energy level distribution due to mechanical strain.
This example describes a pathway that includes (i) creating an ohmic contact on a GaAs wafer by a high temperature annealing process; (ii) (ii) using these integrated ohmic contacts to create GaAs micrometer wires by anisotropic chemical etching, (iii) dry transferring these wires onto a plastic substrate using an elastomeric stamp; and (iv) fabricating high quality MESFETs by low temperature processing of the wires on plastic to produce flexible GaAs MESFETs on plastic substrates. The intrinsic properties of GaAs (e.g., high mobility), the ability to fabricate MESFETs using short gate lengths, and the direct approach to integrating these devices into complex circuits (possibly integrated with transistors using similar approaches but built using other semiconductors) suggest the use of achieving high frequency response for advanced communications, space, and other systems. The above-described advantages of these devices, coupled with excellent mechanical flexibility, make GaAs wire-based MESFETs of interest for flexible large electronic systems.
In summary, GaAs microwire/nanowire with integrated ohmic contacts have been fabricated from bulk wafers by metal deposition and patterning, high temperature annealing, and anisotropic chemical etching. These threads provide a unique class of materials for high performance devices that can be built directly on a variety of unusual device substrates, such as plastic or paper. In particular, the transfer of an organized array of these wires onto a plastic substrate at low temperatures produces high quality, flexible metal semiconductor field effect transistors (MESFETs). Electrical and mechanical characterization of the devices on poly (diethyl terephthalate) (PET) demonstrated the performance levels that could be achieved. These results indicate the promise of this approach to emerge in high-speed flexible circuits in consumer and military electronic systems.
Example 12: using printable semiconductor elementsDevice with a metal layerConfiguration of
Fig. 45 provides a schematic diagram illustrating an exemplary device configuration of the present invention for a P-type bottom gate thin film transistor on a plastic substrate. As shown in fig. 45, a P-type bottom gate thin film transistor includes a printable silicon semiconductor element with doped contact regions, an indium tin oxide bottom gate electrode, an epoxy dielectric layer, and source and drain electrodes. The plastic substrate is a poly (diethyl terephthalate) (PET) sheet. Fig. 45 also provides typical current-voltage characteristics of such devices at multiple gate voltages.
Fig. 46 provides a schematic diagram illustrating an exemplary device configuration of the present invention for complementary logic gates on a plastic substrate. As shown in fig. 46, the complementary logic gates include P-type thin film transistors and N-type thin film transistors, each containing a printable semiconductor element and disposed on a poly (diethyl terephthalate) (PET) sheet.
Figure 47 provides a schematic diagram illustrating one exemplary device configuration of the present invention for a top-gate thin film transistor on a plastic substrate. As shown in FIG. 45, a top-gate thin film transistor includes a printable silicon semiconductor element, SiO, with doped contact regions2A dielectric layer, and a gate electrode, a source electrode, and a drain electrode. The plastic substrate is a poly (ethylene terephthalate) (PET) sheet with a thin layer of epoxy to facilitate transfer and assembly of the thin film transistor and its components. Fig. 47 also provides typical current-voltage characteristics of such devices at multiple gate voltages.