Gain adjustable sensor pixel, array and array system and method thereofCross reference to related applications
The present application claims priority from canadian patent application No.2,628,792 entitled "high dynamic range active PIXEL SENSOR (HIGH DYNAMIC RANGE ACTIVE PIXEL SENSOR)" filed on 10.4.2008. The contents of the above-mentioned patent application are expressly incorporated by reference into the detailed description of the present application.
FIELD
The present application relates to imaging systems, sensor pixels, and methods of operation of such systems, pixels, and arrays.
Background
Sensor pixel circuits (sensor pixels) have a variety of applications. For example, when used in a pixel array as part of a pixel array system for reading out sensed data, such a pixel array system may be used as a Charge Coupled Device (CCD) for a digital camera. Sensor pixels, pixel arrays, and pixel array systems also find use in biomolecular and biomedical imaging, chemical sensing, and a wide range of other fields.
It is desirable to provide alternative circuits, arrays and systems. There is also a need to provide alternative methods of operating existing circuits, arrays and systems, and to provide methods of operating alternative circuits, arrays and systems.
Disclosure of Invention
In one aspect, one embodiment provides a sensor 100, the sensor 100 including a sensor 3, a charge storage 5, a reset block 7 having a reset input 11, a readout block 9, and a charge leakage gain adjustment block 17 having a gain adjustment control input 19. The sensor 3, the charge storage 5, the reset block 7, the readout block 9, and the charge leakage gain adjustment block 17 are each operatively connected to node a.
The gain adjustment block and the charge storage may be separate components. The gain adjustment block and the charge storage may be the same component.
Block 17 may include active components operatively connected to leak charge from node a, while readout block 9 may include active components as amplifiers operatively connected to node a, where these active components have operating parameters that vary similarly over time.
These active components may be transistors. The components of the pixel 100 may be an integrated circuit containing active components. The sensor 3 may be integrated in the back plate.
All components of the sensor pixel 100 may be in the form of an integrated circuit.
In another aspect, an embodiment provides a method of adjusting the gain of a sensor pixel 100. The method includes storing charge from the sensor 3 in a charge storage 5 connected to node a, leaking charge from the charge storage 5 to reduce the charge at node a, and reading out the pixel state represented by the charge at node a.
The method may further include resetting the charge at node a after reading out the state. Leaking charge from the charge storage 5 may further include leaking charge through the charge leakage gain adjustment block 17 according to a signal at the gain adjustment control input 19 of the block 17.
The method may be repeatedly performed, and the amount of charge leaked after storing the charge may be reduced according to a change in an operating parameter due to instability of an active component as an amplifier actively connected to the node a as time passes, and reading out the state of the pixel may include reading out the state of the pixel through the amplifier.
Leaking charge may further include leaking charge through the active component whose operating parameters vary similarly over time to the operating parameters of the active component of the amplifier. The method may further include applying the same bias stress to the active components over time.
Leaking charge may include leaking an amount of charge based on the dynamic range of the signal entering the sensor 3 to adjust the dynamic range of the charge at node a. Leaking charge may include leaking charge to adjust the dynamic range of charge at node a to avoid saturation during readout. Leaking charge may include leaking charge to adjust the dynamic range of charge at node a to avoid saturation during readout, the amount of adjustment being based on a previous readout.
Leaking charge, reading out, and resetting may include leaking charge, reading out, and resetting through different channels.
In another aspect, an embodiment provides a sensor pixel array 302, the array 302 including a plurality of pixel sensors 100 according to any of the above-described sensor pixels 100 connected as an array.
In yet another aspect, an embodiment provides a sensor pixel array system 300, the system 300 including a sensor pixel array 302 according to the sensor pixel array 302 described above, an address driver module 304, and a readout module 306. The sensor pixel array 302 is operatively connected to an address driver module 304 and a readout module 306.
Sensor pixel array system 300 may further include a controller 308 operatively connected to address driver module 304 and readout module 306.
Other aspects and detailed additional features of the above aspects will be apparent from the detailed description herein, the drawings, and the claims.
Brief Description of Drawings
For a better understanding of the presented embodiments and to show more clearly how the embodiments and aspects may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:
fig. 1 is a block diagram illustrating a sensor pixel circuit according to a prior art architecture.
FIG. 2 is a block diagram illustrating a sensor pixel circuit including a gain adjustment block in accordance with an embodiment.
Fig. 3 is a diagram showing an example of an array system comprising sensor pixels according to fig. 2.
Fig. 4 is an example circuit diagram of an embodiment of a pixel sensor circuit according to the block diagram of fig. 2.
Fig. 5 is an example embodiment of a timing diagram for the sensor pixel of fig. 4.
FIG. 6 is a plot of an example pixel readout current versus collected charge for the circuit of FIG. 5 using the timing of FIG. 6.
Fig. 7 is an example timing arrangement for a real-time imaging application of the array system of fig. 2, where the sensor pixel is a sensor pixel according to fig. 4.
Fig. 8 is another example circuit diagram of an embodiment of a pixel sensor circuit according to the block diagram of fig. 2.
Fig. 9 is an example embodiment of a timing diagram for the sensor pixel of fig. 8.
Fig. 10 is an example timing arrangement for a real-time imaging application of the array system of fig. 2, where the sensor pixel is a sensor pixel according to fig. 8.
Fig. 11 is another example circuit diagram of an embodiment of a pixel sensor circuit according to the block diagram of fig. 2.
Fig. 12 is a further example circuit diagram of an embodiment of a pixel sensor circuit according to the block diagram of fig. 2.
Fig. 13 is an example embodiment of a timing diagram for the sensor pixel of fig. 11.
Fig. 14 is an exemplary embodiment of a timing diagram for the sensor pixel of fig. 12.
Fig. 15 is another example embodiment of a timing diagram for the sensor pixel of fig. 11.
Fig. 16 is yet another example embodiment of a timing diagram for the sensor pixel of fig. 11.
Fig. 17 is yet another example embodiment of a timing diagram for the sensor pixel of fig. 11.
FIG. 18 is a graph of an example normalized amplifier gain over time for the sensor pixel of FIG. 2 with and without aging compensation.
Fig. 19 is a further example circuit diagram of an embodiment of a pixel sensor circuit according to the block diagram of fig. 2.
Fig. 20 is another example circuit diagram of an embodiment of a pixel sensor circuit according to the block diagram of fig. 2.
Fig. 21 is an example embodiment of a timing diagram for the sensor pixel of fig. 19.
Fig. 22 is an example embodiment of a timing diagram for the sensor pixel of fig. 20.
Fig. 23 is another example embodiment of a timing diagram for the sensor pixel of fig. 19.
Fig. 24 is a further example circuit diagram of an embodiment of a pixel sensor circuit according to the block diagram of fig. 2.
Fig. 25 is an example embodiment of a timing diagram for the sensor pixel of fig. 24.
Fig. 26 is a schematic diagram of an example embodiment of a pixel array including example pixels according to the embodiment of fig. 2.
Detailed Description
The embodiments are described using a pixel circuit having at least one transistor. The transistors in the pixel circuit may be fabricated by any technology, including polysilicon, nano/micro silicon, amorphous silicon, CMOS, organic semiconductors, and metal oxide technologies. The pixel array with the pixel circuit may be an active matrix image sensor array and may be used, for example, for medical applications ranging from tissue and organ level to molecular and cellular level imaging. Example applications include large area multimode biomedical and other x-ray imaging (when coupled to a relief layer) to optical biomolecular imaging, including imaging of fluorescence-based biological sequences. Example applications also include sensitive applications with single-event (single photon, single DNA) detectors. The foregoing are merely examples and possible applications are not limited thereto.
In the following description, "pixel" and "pixel circuit" are used interchangeably. In the following description, "signal" and "line" may be used interchangeably as appropriate in context. In the following description, the terms "line" and "node" are used interchangeably, as appropriate, in context. In the following description, the terms "select line" and "address line" are used interchangeably. In the following description, "connected (or connected)" and "coupled (or coupled)" may be used interchangeably, and may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other.
Included in this specification are a variety of pixel circuits that can be used to fully exploit the gain setting, aging reduction, and aging compensation features and other features described herein; however, it should be understood that these circuits need not utilize these features and may advantageously operate in alternative ways. Methods of biasing the pixel circuit will be described herein to provide features such as gain setting and instability compensation. It should be understood that such methods may be applied to the novel pixel circuits described herein; moreover, these methods may also be applied to alternative pixel circuits including existing pixel circuits.
The pixel circuits described herein will be described with reference to photosensor pixel circuits; however, it should be understood that other sensors such as chemical sensors, temperature sensors, biomedical transducers, optical sensors, and direct x-ray sensors, and the transistors used for these sensors, generate charge to be read out by the pixel circuits described herein and other pixel circuits to which the features herein may be applied. These other sensors may be mechanical or chemical sensors, for example, as desired. Such sensors may themselves be capacitors, as is known in the art.
Like reference numerals are used to refer to like parts throughout the several views and several embodiments. Descriptions for these same components should be understood as applying to these components of the various embodiments unless the context clearly dictates otherwise or exceptionally. Similarly, for ease of reference, identical components may be given different reference numerals; however, descriptions of these same components should be understood to apply to these components of the various embodiments unless the context clearly dictates otherwise.
Referring to fig. 1, a conventional sensor pixel 1000 generally has a sensor 3, a charge storage 5, a reset block 7, and a readout block 9 respectively connected to a charge node a. The sensor 3 converts an environmental or biological signal 1, such as for example light or capacitance, and converts the sensed signal 1 into an electrical charge. The output of the sensor 3 is an electrical property such as voltage or current. The storage section 1 stores a representation of the output of the sensor 3 as a voltage. The charge reservoir 5 stores charge from the sensor 3 such that the charge reservoir 5 appears at node a. The amount of charge at node a represents the state of the pixel 1000. The reset block 7 has a reset control input 11 and resets the state of the pixel 1000 in dependence on a signal received at the reset control input 11. Reset block 7 resets the state of pixel 1000 by changing the charge of charge storage 5, thereby changing the charge at node a. The readout block 9 has a sensor pixel output 15 and provides access to the state of the pixel 1000 at the sensor pixel output 15 so that the state of the pixel 1000 can be read at the sensor pixel output 15 by an external module not shown (but see the example for the pixel 100 in fig. 3). Referring to fig. 2, the charge leakage gain adjustable sensor pixel 100 also has a sensor 3, a charge storage 5, a reset block 7, and a readout block 9 respectively connected to the node a. The gain adjustable sensor pixel 100 also has a gain adjustment block 17 connected to node a. The gain adjustment block 17 has a charge leakage gain adjustment control input 19. The gain adjustment block 17 leaks charge from the charge storage 5 in accordance with the signal at control input 19, thereby leaking charge at node a. This adjusts the effective charge-to-voltage conversion of the sensor pixel 100. Thus, the voltage read out by the readout block 9 is adjusted and the sensor pixel output 15 is adjusted. Thus, the overall gain of the pixel 100 receiving the signal 1 from the sensor 3 to the pixel output 15 is also adjusted.
The dynamic range of the sensor pixel 100 can be adjusted. In addition, sensor pixel 100 instability can be compensated. The dynamic range can be adjusted by adjusting the gain on the pixel. The sensor pixel drive scheme can provide low noise, high sensitivity, and high dynamic range. The gain adjustment block 17 can adjust the dynamic range of the charge stored by the charge storage 5 from the sensor 3, thereby adjusting the dynamic range of the charge at node a. This may prevent saturation of the active readout block 9 within the pixel or of external modules. Instability can be compensated for by making a gain adjustment to sensor pixel 100 in an amount corresponding to the change in instability in the pixel gain.
A sensor pixel 100 having components formed on an integrated circuit may have a backplane containing active components such as transistors and diodes. The sensor 3 within the sensor pixel 100 may be integrated in the backplane or may be provided as a discrete component. Passive components, such as capacitors, may be integrated into the backplane or provided as discrete components. Thus, the entire sensor pixel 100 may be an integrated circuit, a discrete component, or a combination of an integrated circuit and a discrete component. In the case where instability compensation is part of the pixel 100, then the active components will be formed in the integrated circuit, which will match the component fabrication parameters.
Referring to fig. 3, a sensor pixel array system 300 has a sensor pixel array 302 connected to an address driver module 304 and a readout module 306. The modules 304, 306 are each connected to a controller 308. The array 302 has a plurality of sensor pixels 100 connected as an array. The address driver module 304 provides control signals to the pixels 100 and the array 302. The readout module 306 reads the output 15 of each pixel 100 and sends the readout pixel output to the controller 308. The controller 308 controls the timing of the modules 304, 306, thereby controlling the timing of the blocks 7, 9, 17.
The controller 308 may adjust the gain of the pixel 100 by adjusting the timing of the block 9. The adjustment may be based on feedback received by the controller 308 from the readout module 306. This may provide an immediate gain adjustment to individual sensor pixels based on data collected from the sensor pixels 100. Alternatively, where the sensor array system is used in a different application, the gain may be adjusted based on the expected signal strength of the application.
Referring to fig. 26, an example pixel array 2600 that can be used as pixel array 302 is shown. It will be appreciated that the control inputs "reset", SPR, V1 and V2 will not be used in all embodiments of the array 302, as will be apparent from the pixel embodiments described later herein. Idata (I)Data of) A pixel output 15 is provided. For example, V1(i) (i ═ 1, 2.) denotes a bias line of the ith row, and V2(i) denotes another bias line of the ith row; and IData of(j) And (j ═ 1, 2.) denotes a data line in the j-th column. Reset, SPR, V1, and V2 are driven by address drive circuit 304. I isData of(j) Read by the readout module 306. By aligning the corresponding V1 and V2 lines (e.g., V1[1 ]]And V2[1 ]]) A pulse is applied to select a row. The output current of each pixel 100 in the selected row is typically sensed by a transresistance or charge amplifier of the readout module 304.
Various exemplary embodiments of the sensor pixel 100 and exemplary embodiments of timing driving schemes will now be described. The gain adjustment block 17 will provide charge-based compensation in the pixel circuit 100 suitable for use in a real-time imager. The gain adjustment block 17 of the particular embodiment shown provides a discharge path that can be used to compensate for aging and gain mismatch and adjust the gain of the pixel 100 for different applications.
Referring to fig. 4, the pixel circuit 400 has a sensor 3, a capacitor C forming a charge storage 5SA switching transistor T forming a reset block 72And an amplifier transistor T forming a sense block 91And a diode-connected transistor T forming a gain adjustment block 17DAnd a switching transistor T3. Reset control input 11 is provided to T2And switching the transistor T3Provides the gain control input 19. V1 provides bias inputs for storage 5, sense block 9, and gain adjust block 17.
Referring to fig. 5, in an example timing of the drive circuit 400, during a reset cycle (reset control input 11 is asserted high to cause transistor T)1On), node A is charged to a reset voltage (V)R). The next cycle may be discharging to compensate as will be described in the embodiments below. For the present embodiment, the discharge is not illustrated for compensation. Thus, the next cycle is an integration cycle. During integration, the sensor 3 output is stored by a storage capacitor CSAnd (6) collecting. SPR enables T during a gain adjustment cycle3Is turned on and some of the stored voltage from node A passes through TdAnd (4) leaking out. Leakage time (tau)L) -namely T3The period of time that is on and the gain adjustment block 17 is active-adjustments may be made to control the gain of the pixel 100 for different applications. V1 is reduced during the gain adjustment cycle to ensure Td is forward biased.
After integration and gain adjustment by charge leakage, a readout cycle is performed. By making the amplifier transistor T during the read-out cycle1Low bias to V1, making it conductive. Thus, V1 provides a sense control input 21 to sense block 9. The read control input 21 is used to include an amplifying transistor T1Of the active sensor pixel. The timing of the readout control input 21 is provided by the controller 308 in a similar manner to the other control inputs, the reset input 11. The non-readout switch passive sensor pixel circuit can avoid switch crystalBody tube T1And a readout control input 21, wherein the switching function is implemented out of the circuit, for example by the readout module 306.
Flow-through transistor T1Provides a sensor pixel output 15, which output 15 is read by the readout module 306 to be provided to the controller 308. The read operation is not destructive because the pixel circuit 400 operates in an active mode.
The remaining voltage (V) at node A after the gain adjustment cycledmp) Is given by
Here, VgenIs the resulting voltage produced by the collected charge. By assuming VgenMuch less than VRThe linear approximation can be used to calculate the attenuation effect (A)dmp) The following were used:
example measurements of different leak times are shown in fig. 6. The gain of the pixel may be adjusted for various applications. For example, for very low intensity input signals (e.g., fluoroscopy), the leakage time may be close to zero, which allows for high gain. On the other hand, for higher intensity input signals (e.g., radiology), the leak time may be increased (e.g., 27 μ s). The pixel response to the collected charge may be smoothed so that the pixel gain may be more linear or flat linear.
The pixel circuit 400 can provide parallel operation of reset and readout cycles for different rows of pixels 400 in the array 302. It is therefore useful for real-time imaging applications such as fluoroscopy. Fig. 7 shows an example timing arrangement for an array 302 intended for real-time imaging, where R is a reset cycle, Int is an integration cycle, G is a gain adjustment cycle, and Rd is a readout cycle.
Referring to fig. 8, in sensor pixel 800, T3 and Td may be combined, and Td may replace the storage capacitor CS. This results in a 3-TFT gain adjustable sensor pixel 800. This may provide improved resolution by reducing the components within the pixel and increasing the pixel intensity. V1 biases only the amplifying transistor T1 to turn T1 on and off. Td now acts as both charge storage 5 and gain adjustment block 17. V2 biases Td.
Referring to fig. 9, V2 turns Td off and on to provide the gain adjustment control input 19, while the other timings remain the same.
Referring to fig. 10, the pixel 800 provides separate paths for gain adjustment, reset, and readout (the biasing of Td and T1 is performed by V1 and V2, respectively); thus, the scheduling can be improved to achieve more parallelism as shown. When the pixels 800 in one row are reset, the pixels of the next adjacent row are in a gain cycle and the rows following that row are read out. Thus, pixel 800 may provide a fast refresh rate suitable for high frame rate real-time imaging.
Referring to fig. 11, a sensor pixel 1100 is similar to pixel 100, but with separate bias lines V1 and V2 to allow separate gain adjustment, reset, and readout paths. Other control inputs are similar to those in pixel 100. The pixel 1100 has four control inputs: v1, V2, reset, and SPR.
Referring to fig. 13, an example driving timing of the pixel 1100 is shown. V1 ensures forward biasing of gain adjust block 17 while V1 is turned on at the gate of T3.
Referring to fig. 12, the switching passive pixel 1200 is also similar to the pixel 100; however, T1 is configured as a passive switching transistor and Read provides the readout control input 21. Other control inputs are similar to those in pixel 100.
Referring to fig. 14, an example driving timing of the pixel 1200 is shown. V1 ensures forward biasing of gain adjust block 17 while V1 is turned on at the gate of T3. Sensing ensures that the output transistor T1 is off except during the sensing cycle.
Note that for pixels 1100 and 1200, Td may be substituted for the storage capacitor Cs, as described in pixel 800. Td may also be a diode. Furthermore, the positions of Td and T3 may be interchanged without affecting the pixel operation.
Referring to fig. 13 and 14, during the reset cycle, T2 is turned on and thus node a is charged to the reset Voltage (VR). During the integration cycle, the charge generated by the sensor is accumulated in a CS (charge storage). During the gain adjustment cycle, T3 turns on, so that a portion of the charge stored in CS leaks out through Td. Thus, the dynamic range of the output of the sensor can be controlled. During the sensing cycle, the voltage at node a is converted to a current through T1 and sent to the external sensing/driving circuit module 306.
Referring to fig. 15, another example driving timing of the pixel 1100 is shown, where V1 and V2 have the same timing signal. During the gain adjustment cycle and the readout cycle, the combined signal is low. This takes advantage of the separate paths within the pixel 1100 while reducing the complexity of timing control.
Referring to fig. 16, another example drive timing for a pixel 1100 is shown. A new drive cycle has been added to the pixel operation to provide intra-pixel leakage discharge gain adjustment through transistor Td to match the operating characteristics of the amplifying transistor T1 to compensate for the time instability of T1. The characteristics of T1 change over time, which is referred to as time instability or threshold voltage shift. Transistor Td will match the operating characteristics of T1 over time because they have the same bias conditions. Therefore, if the gain of T1 decreases over time, the gain of Td will also decrease. While T1 will provide less amplification for a given bias voltage remaining at node a, Td will release less charge from charging node a, leaving more charge at node a to bias T1, so the gain of the pixel will remain unchanged over time.
During the compensation cycle, T3 turns on, so that a portion of the reset Voltage (VR) is discharged through Td. Since the discharge voltage is a function of the Td parameter, any change in the Td parameter will affect the remaining voltage at node a in the opposite direction. For example, if the threshold voltage of Td rises due to instability caused by bias, the discharge voltage will be small at a given moment, and thus the remaining voltage at node a will be large. Furthermore, because Td and T1 experience similar bias conditions and thus similar bias stresses over time, their parameters follow the same trend. Instability compensation does not require that the bias conditions be the same at all times, but rather that similar bias conditions be experienced over a longer period of time. For example, if Td is turned on for 10us and turned off for the remainder of the frame, T1 is also high and has the same level for these 10 us. This means that a reset voltage change based on the Td parameter will also compensate for the T1 parameter change. Such instability compensation may be used for other pixels described herein.
Referring to fig. 17, another example drive timing for a pixel 1100 is shown. This timing loop is similar to the loop of fig. 15, with the addition of a drive loop similar to that described with respect to fig. 16 to compensate for instability of T1.
Referring to fig. 18, an example effect of instability compensation on aging of the amplifying transistor T1 over time is shown compared to non-instability compensated drive timing. The vertical axis is the gain of the pixel 1100 from the sensor 3 output to the pixel output 15. The gain (instability compensated) of pixel 1100 at the timing of FIG. 17 is shown as a straight line with square points, while the gain (instability uncompensated) of pixel 1100 at the timing of FIG. 15 is shown as a non-linear decreasing curve with dots.
Referring to fig. 19, pixel 1900 is similar to pixel 800 in that T1 is diode connected and replaces T3. V1 biases Td and performs the switching function in the same manner as V2 does for pixel 800. Pixel 1900 holds the storage capacitor CS in the same manner as, for example, pixel 400, and does not rely on the inner capacitance of Td.
Referring to fig. 20, a pixel 2000 is similar to the pixel 1900 except that the transistor T1 is a passive switch connected for the readout block 9, similar to T1 of the pixel 1200, rather than a switch that amplifies the connection. This results in a passive pixel 2000. The read input to the gate of T1 performs a switch for sensing purposes instead of V2.
Referring to fig. 21, an example driving timing of a pixel 1900 is shown. Referring to fig. 22, an example driving timing of the pixel 2000 is shown.
Referring to fig. 21 and 22, example timing for pixels 1900 and 2000 are similar to the timing in fig. 13 and 14, respectively; except that V1 is low so that Td is on during the gain adjustment cycle. When Td is turned on, a portion of the charge stored at node a is discharged through Td, thereby adjusting the gain.
Referring to fig. 23, an example timing embodiment of a pixel 2100 is provided. This timing embodiment is similar to the timing of fig. 21, with additional compensation cycles similar to fig. 16.
Referring to fig. 24, a pixel circuit 2400 is similar to the pixel circuit 1900; the difference is that the reset block 7 and the gain adjustment block 17 are incorporated together in a diode-connected transistor Td. Td performs reset and gain adjustment of node a by leakage from node a.
Referring to fig. 25, an example driving timing of the pixel of fig. 24 is shown. During the reset cycle, V1 drops to a very low voltage (-VR), and thus the voltage at node A will become "-VR + VT". However, V1 becomes the bias Voltage (VB). This way not only does node a reset to a known voltage, but the reset voltage can compensate for the instability of T1 and Td. During the integration cycle, the charge generated by the sensor accumulates in the charge storage. During the gain adjustment cycle, the voltage at node a is discharged to tune the gain. During the read cycle, the signal is read back through T1.
The gain adjustment for transistor instability may be set separately from the dynamic range gain adjustment.
As the number of pixel components is reduced in different embodiments, the density of the corresponding pixel array is increased. This may allow for an increase in resolution.
In the above-described pixel, it will be well understood that the storage capacitor Cs may be a transistor. Similarly, the sensor 3 may be a capacitor for a non-optical sensor, such as for example a mechanical or chemical sensor application.
In some embodiments, the sensor pixels described herein may be used in place of pixels in existing Charge Coupled Devices (CCDs) commonly used in a variety of applications including biometric imaging.
Although terms such as high and low and ground have been used, this is not intended to limit the embodiments to a particular drive polarity or component orientation. For example, it is well understood by those skilled in the art that PMOS circuit components can be used instead of NMOS circuit components, using the concept of complementary circuit design, thereby resulting in changes in drive polarity and component orientation. A consequent circuit change may be required to connect circuit components or external modules of unchanged drive polarity or orientation.
Although specific embodiments of gain-adjustable pixels have been described herein, it should be understood that gain adjustment may be combined with other techniques known to improve the performance or applicability of a particular application. For example, in the above-described pixel, the storage capacitor Cs may be a variable capacitor for further varying the pixel performance at different input intensities. For example, for an x-ray imager, a low capacitor may be used to obtain low x-ray intensity to improve charge-to-voltage conversion. On the other hand, for high x-ray intensities, a large capacitance may provide better performance in terms of dynamic range. One way to implement a variable capacitor is to use a metal-insulator-semiconductor (MIS) structure instead of a metal-insulator-metal (MIM). By varying the bias condition of the capacitor Cs, the storage capacitance can be adjusted for different applications.
It is recognized that gain-adjustable pixels may be combined with such other techniques while remaining within the scope of the description herein.
One or more presently preferred embodiments have been described as examples. It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.