The present application relates to U.S. patent application serial No. 10/791,241 entitled System and Method for Reducing Heat dissipation during Burn-In, filed 3/1 2004 by e.sheng et al, U.S. patent application attorney docket No. TRAN-P281, assigned to the assignee of the present invention, and the entire contents of which are hereby incorporated by reference.
The present application relates to U.S. patent application serial No. 10/791,099 entitled System and Method for Reducing Temperature variation during aging, entitled System and Method, filed 3/1 2004 by e.sheng et al, and assigned to the assignee of the present invention and the entire contents of which are hereby incorporated by reference.
Detailed Description
Reference will now be made in detail to the various embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, one of ordinary skill in the art will realize that the invention may be practiced without these details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, bytes, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as "applying," "selecting," "measuring," "adjusting," "regulating," "accessing," or the like, refer to the action and processes of a computer system, or similar intelligent electronic computing device (e.g., flowchart 400 of FIG. 4), that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
The following description of embodiments of the invention describes coupling a body bias voltage to a p-channel field effect transistor (pFET) or a p-type metal oxide semiconductor field effect transistor (p-type MOSFET) formed in a surface N-well via an N-type doped conductor sub-surface region when utilizing a p-type substrate and N-well process. However, embodiments in accordance with the present invention can be equally applied to coupling a body bias voltage to an n-channel fet (nfet) or n-type MOSFET formed in a surface P-well via a P-type doped conductive subsurface region when utilizing an n-type substrate and P-well process. Thus, embodiments in accordance with the present invention are suitable for semiconductors that utilize and are formed in either p-type or n-type materials.
Fig. 1 shows a top view of a pFET50 (or p-type MOSFET) formed in an N-well 10 when a p-type substrate and N-well process is utilized, in accordance with one embodiment of the present invention. The N-well 10 has an N-type doping. A semiconductor device region doped with an n-type dopant has one type of conductivity and a region doped with a p-type dopant has another type of conductivity. Typically, a variety of different dopant concentrations are utilized in different regions of a semiconductor device.
In this embodiment, pFET50 has a body bias voltage Vnw applied to its bulk or body terminal B. As shown in fig. 1, pFET50 has a gate G, a drain D (p-type doped), a source S (p-type doped), and a bulk/body terminal B. In particular, the bulk terminal B is coupled to the N-well 10. Thus, the voltage applied to the bulk/body terminal B is received by the N-well 10. In the case of body bias, the block/body terminal B receives a body bias voltage Vnw. Accordingly, the body bias voltage Vnw is applied to the N-well 10.
The pFET50 is body biased to affect its performance. Without body biasing, the source S and the block/body terminal B are coupled together. With body biasing, the source S and bulk/body terminal B are not coupled together. The body bias enables control of the potential difference between the source S of the pFET50 and the bulk/body terminal B, thereby providing the ability to control the threshold voltage level of the pFET 50. Other parameters such as leakage current associated with the pFET50 may also be controlled thereby. Increasing the threshold voltage will reduce the leakage current. Thus, body biasing for increasing the threshold voltage may be used to reduce leakage current.
Burn-in operations for detecting integrated circuit defects are typically performed at strain temperatures (e.g., 150 degrees celsius), strain voltages (e.g., 1.5 times the normal operating voltage), and at low operating frequencies (typically on the order of lower than the normal operating frequency).
Fig. 2 illustrates an exemplary apparatus 100 including a plurality of Devices Under Test (DUTs) 101, 102,. and N (e.g., integrated circuit devices) configured for burn-in operations, according to one embodiment of the invention. According to an embodiment of the present invention, the integrated circuit devices 101, 102. As noted above, the integrated circuit devices 101, 102, N may be replaced with nfets.
The integrated circuits 101, 102, N of fig. 2 may be arranged on a printed wiring board 110, which printed wiring board 110 may comprise a socket for receiving the integrated circuit device 101, 102. Because it is desirable to operate the integrated circuit device to be tested at elevated temperatures, the wiring board 110 is typically placed in a temperature chamber capable of temperature regulation at the test temperature (e.g., 150 degrees celsius). A typical burn-in chamber may include multiple circuit boards.
The wiring board 110 includes, for example, wiring traces (traces) that conduct electrical signals between various power supplies, test controllers and/or measurement instruments and the integrated circuit devices 101, 102. In this embodiment, wiring board 110 includes an operational voltage source distribution system 151 and a test control distribution system 152. It should be appreciated that distribution systems 151 and 152 may be configured using a bus, point-to-point, separate topologies, or the like.
Test control distribution system 152 couples test controller 150 and integrated circuit devices under test 101, 102, N and delivers signals from test controller 150 to integrated circuit devices under test 101, 102, N. As will be described in more detail below, the test controller 150 may also be coupled to a voltage source, a temperature monitoring device, and an ambient temperature sensor in order to measure and control electrical parameters related to the power consumption and temperature of the integrated circuit devices 101, 102.
The test controller 150 may be located on the wiring board 110. However, due to various factors (e.g., the physical size and/or characteristics of the equipment used to implement the test controller 150), embodiments in accordance with the present invention are also suitable for locating the test controller 150 components at another location within the test environment (e.g., on a separate wiring board coupled to the wiring board 110, or outside of the thermal test chamber). For example, if test controller 150 is implemented as a workstation computer, it is often impractical to place such a workstation in a thermal test chamber due to limitations in its size and operating temperature.
The test unit controller, which may or may not be part of the test controller 150, may be used to simulate the integrated circuit devices 101, 102, N to be tested with a sequence of test patterns and/or test commands, and to access the results. Embodiments in accordance with the present invention are also suitable for a wide range of test cell controllers and test methodologies, including, for example, Joint Test Action Group (JTAG) boundary scan and array built-in self test (ABIST).
An operating voltage source distribution system 151 couples the operating voltage source 140 and the integrated circuit devices 101, 102. The operating voltage source 140 provides a voltage (Vdd) and a current to operate the integrated circuit devices 101, 102. In this embodiment, the operational voltage source 140 is also coupled to the test controller 150, for example, via the bus 156, so the operational voltage source 140 may receive control signals from the test controller 150.
In the present embodiment, each integrated circuit device under test 101, 102, N is coupled to a respective forward body bias voltage generator 121, 122, N. The positive body bias voltage generators 121, 122, ·, N provide a positive body bias voltage to N-type wells disposed below pFET devices in the integrated circuit devices 101, 102, ·, N to be tested. Such body biasing enables, for example, adjusting the threshold voltage of the pFET device to reduce leakage current of the pFET device. In one embodiment, the body bias voltage provided by generators 121, 122. In this embodiment, the positive body bias voltage generators 121, 122,. N are also coupled to the test controller 150, for example, by a bus 157, so the body bias voltage generators may receive control signals from the test controller 150.
In a similar manner, each integrated circuit device under test 101, 102, N is coupled to a respective negative body bias voltage generator 131, 132. The negative body bias voltage generators 131, 132, N provide a negative body bias voltage to a p-type well disposed beneath the nFET devices in the integrated circuit devices 101, 102, N under test. Such body biasing enables, for example, the threshold voltage of the nFET device to be adjusted to reduce leakage current of the nFET device. In one embodiment, the body bias voltage provided by the generators 131, 132. In this embodiment, the negative body bias voltage generators 131, 132.
It should be appreciated that the positive body bias generators 121, 122, the. -, N and the negative body bias voltage generators 131, 132, the. -, N may be located on the wiring board 110, or they may be located outside the wiring board 110, according to embodiments of the present invention.
Typically, the body bias voltage generators 121, 122, ·, N and 131, 132, ·, N are variable voltage sources. Their output voltages may be set to a specific value (within a range). It is desirable, but not necessary, to set this particular value digitally (e.g., by a command from the test controller 150). The body bias current is typically on the order of less than a microampere per integrated circuit. Accordingly, the bias voltage generators 121, 122, ·, N and 131, 132,. and N may be relatively small and inexpensive voltage sources.
In this embodiment, the apparatus 100 further includes an ambient temperature monitor 160 that measures the ambient temperature within the test chamber. The ambient temperature measurement is reported back to the test controller 150, for example, via the bus 154. The apparatus 100 may include a plurality of ambient temperature monitors.
With continued reference to fig. 2, each integrated circuit device under test 101, 102, N is coupled to a respective temperature monitor 111, 112. The temperature monitors 111, 112, a. The temperature measurement is reported back to the test controller 150, for example, via the bus 153.
FIG. 3 is a cross-sectional side view of an integrated circuit device 101 configured for burn-in testing according to one embodiment of the present invention. Fig. 3 shows integrated circuit device 101 connected to wiring board 110 by a plurality of pins 350. In the present embodiment, integrated circuit device 101 includes a Ball Grid Array (BGA)340, a package 330, a die 320, and a heat sink 310. It should be understood that the elements comprising integrated circuit device 101 are by way of example only and that the present invention is not limited to use with the integrated circuit device illustrated by fig. 3.
In the present embodiment, the temperature monitor 111 is located between the heat sink 310 and the die 320. The temperature monitor 111 may be, for example, a thermocouple. The temperature monitor 111 is connected to a trace 315, which trace 315 may in turn be connected to the bus 153 of FIG. 2, or which trace 315 may in turn represent a portion of the bus 153 of FIG. 2.
The temperature measured at the integrated circuit device under test is referred to herein as the "junction temperature". In the example of fig. 3, the junction temperature refers to the temperature at the die 320.
Referring to fig. 2, the junction temperature (T) of the integrated circuit devices under test 101, 102junction) Can be approximated according to the following relationship:
Tjunction＝Tambient+Pθi [1]
wherein, TambientIs the ambient temperature measured by the ambient temperature monitor 160; p is the power consumed by the integrated circuit device; and thetaiIs a thermal resistance of the integrated circuit device (e.g., a thermal resistance associated with heat transfer from the die 320 of fig. 3 to the ambient air).
The power consumed (P) is a function of both the operating voltage supplied to the integrated circuit and the body bias voltage applied to the integrated circuit. According to an embodiment of the invention, θ may beiIs considered to be constant for all integrated circuit devices 101, 102, N to be tested, since (as will be seen) the power consumption P can be adjusted such that the junction temperature is substantially the same for all integrated circuit devices 101, 102, N to be tested.
The apparatus 100 of fig. 2 will now be described in operation according to one embodiment of the present invention. In summary, the power consumption of an integrated circuit (P in equation [1]) can be adjusted by adjusting the threshold voltage of the integrated circuit, even if the operating voltage of the integrated circuit remains constant. The threshold voltage may be adjusted by adjusting a body bias voltage supplied to a body bias well disposed below an active semiconductor of the integrated circuit. Adjusting the threshold voltage of an integrated circuit may increase or decrease the leakage current of the integrated circuit, which is an important component of the power consumption P of the integrated circuit, especially during low frequency operation, such as during the burn-in process. Thus, controlling the leakage current provides control over power consumption, and controlling the body bias voltage controls the leakage current.
According to one embodiment of the present invention, equation [1] above]Shown when the ambient temperature (T)ambient) And thermal resistance (theta)i) At substantially constant time, the junction temperature (T) of the integrated circuit to be tested can be controlled by controlling the power (P) consumed by the integrated circuitjunction). The power (P) consumed by an integrated circuit operating at a fixed operating voltage may be controlled by adjusting the body bias voltage applied to the integrated circuit.
Referring to fig. 2, a particular junction temperature (e.g., 150 degrees celsius) is selected for the burn-in test. The ambient temperature of the thermal test chamber may also be specified. A thermal resistance (θ) associated with each integrated circuit device under test 101, 102i) Are also known quantities, at least approximate to meet the requirements. And the voltage supplied by the operating voltage source 140 is known. Using this information, the initial magnitude of the body bias voltage applied to each integrated circuit device under test 101, 102.
However, because the temperature at each integrated circuit device under test 101, 102, the body bias voltage initially applied to the device under test is monitored using temperature monitors 111, 112, the body bias voltage initially applied to the device under test. Instead, the amount of body bias voltage to be applied can be determined empirically by measuring the junction temperature, and then by adjusting the body bias voltage to obtain the junction temperature required for the burn-in test.
After the burn-in test operation begins, the junction temperature at each integrated circuit device under test 101, 102. If any one of the devices under test experiences a junction temperature different from that required for burn-in testing, the body bias voltage of the device under test can be adjusted (increased or decreased) until the junction temperature returns to the required value. In this embodiment, the integrated circuit devices 101, 102, the.. and N are each associated with a respective positive body bias voltage generator 121, 122, the.. and N and negative body bias voltage generators 131, 132, the.. and N, and thus the body bias voltage applied to one dut can be adjusted without affecting the body bias voltages applied to the other duts.
The body bias voltage applied to each integrated circuit device under test 101, 102, N may be adjusted automatically by the test controller 150 based on feedback from the temperature monitor, or may be adjusted manually.
Thus, the junction temperature at each integrated circuit device under test 101, 102,. and N can be controlled separately by controlling the body bias voltage applied to each device. In this way, variability from one device under test to another can be handled such that each device is subjected to the same test temperature.
For example, the ambient temperature within the test chamber may not be uniform, so some devices under test are subjected to higher ambient temperatures than others. Assuming this occurs, it will be reflected in the measurement of junction temperature, since junction temperature is a function of ambient temperature (see equation [1] above). Thus, the junction temperatures of devices in the higher temperature regions of the test chamber can be adjusted by adjusting the body bias voltage applied to these devices until their respective junction temperatures reach the desired test temperature.
In a similar manner, differences in heat sink performance from one dut to another dut may be addressed. There may be other variables that affect junction temperature and introduce variability between various devices under test. Generally, by applying different body bias voltages to different devices under test as needed, the variability from one device to the next can be reduced so that each device under test is subjected to substantially the same burn-in test temperature.
In addition, the bulk bias voltage may be adjusted over the course of the burn-in test to account for variations in test conditions that may occur over time. For example, when the test chamber begins to heat up, the body bias voltage can be adjusted to not only maintain the desired junction temperature, but also to control the ambient temperature within acceptable limits.
FIG. 4 is a flow diagram 400 of a method for controlling temperature during burn-in testing according to one embodiment of the invention. Although specific steps are disclosed in flowchart 400, such steps are exemplary. That is, the present invention is well suited to performing various other steps or variations of the steps recited in flowchart 400. It should be understood that the steps in flowchart 400 may be performed in a different order than that shown.
In block 410 of FIG. 4, an operating voltage is applied to the device under test.
In block 420, a body bias voltage is applied to the device under test. The amount of body bias voltage is chosen such that a specific test temperature is obtained at the device under test. In one embodiment, the device under test comprises a P-channel metal oxide semiconductor (PMOS) device and the body bias voltage is in the range of about zero to five volts. In another embodiment, the device under test comprises an n-channel metal oxide semiconductor (NMOS) device and the body bias voltage is in a range of approximately zero to minus ten volts.
In block 430, a temperature (e.g., junction temperature) at the device under test is measured.
In block 440, the amount of body bias voltage applied to the device under test is adjusted, if necessary, and by an amount necessary to maintain a desired test temperature (e.g., junction temperature) at the device under test. The flow diagram 400 then returns to block 430. In this way, the temperature is continuously measured during burn-in, and the body bias voltage is adjusted to maintain the correct junction temperature throughout burn-in.
For example, referring to FIG. 2, an integrated circuit device under test 101 receives an operating voltage supplied by a voltage source 140. The integrated circuit device under test 101 also receives a body-bias voltage from either the positive body-bias voltage generator 121 (if the device 101 is an NFET device) or the negative body-bias voltage generator 131 (if the device 101 is a PFET device). The temperature at the integrated circuit device 101 to be tested is measured using a temperature monitor 111. The temperature at the integrated circuit device under test 101 is provided to the measurement controller 150. If the temperature at the integrated circuit device under test 101 is less than or greater than the desired test temperature, the test controller 150 may adjust the body bias voltage provided to the device by either the positive body bias voltage generator 121 or the negative body bias voltage generator 131. Similarly, if the temperature measured by the ambient temperature monitor 160 increases, the test controller 150 may adjust the body bias voltage provided by the positive body bias voltage generator 121 or the negative body bias voltage generator 131 to the integrated circuit device 101 under test to maintain a desired test temperature at the device.
In summary, embodiments of the present invention provide systems and methods for controlling the temperature during burn-in such that all devices experience substantially the same temperature during burn-in. Thus, all devices under test may be subjected to substantially the same test conditions. Thus, one source of instability that would otherwise be introduced into the test results can be eliminated.
Although described with respect to testing in which all devices under test are subjected to substantially the same testing temperature, it should be understood that embodiments of the present invention may also be used to test devices at a range of temperatures at the same time. For example, some devices may be tested at one junction temperature and others at another junction temperature by subjecting various different devices under test to different body bias voltages.
Additionally, although described with respect to testing in which a device under test is subjected to a testing temperature that remains substantially constant during burn-in operations, it should be understood that embodiments of the present invention may also be used to vary the temperature during testing. For example, by varying the body bias voltage during burn-in a controlled manner, the junction temperature during burn-in is also varied in a controlled manner.
Thus, in accordance with an embodiment of the present invention, a system and method for controlling temperature during burn-in is described. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the below claims.