Background
Many techniques are used to package-on-package integrated circuits. Some methods require special packaging, while others stack conventional packaging. In some stacks, leads of the packaged integrated circuit are used to build up the stack, while in other systems, additional structures such as traces provide all or part of the interconnection between the packages. In still other techniques, flexible conductors with specific characteristics are used to selectively interconnect packaged integrated circuits.
The main packaging structures applied during the last decade encapsulate Integrated Circuits (ICs) in a plastic surround, which generally has a rectangular structure. The encapsulated integrated circuit is connected to the application environment by leads emanating from the end periphery of the plastic encapsulation. Such "leaded packages" are becoming the most widely used component for package-on-package integrated circuit technology.
Lead packages play an important role in electronics, and efforts to minimize electronic components and assemblies have driven the development of techniques to maintain circuit board surface area. Because the leaded package has leads emanating from the perimeter of the package, the leaded package occupies not only a minimal amount of circuit board surface area. Therefore, alternatives to leaded packages have recently gained market share.
One type of alternative package is generally defined as a "chip scale package" or CSP. CSP generally refers to a package that provides connection to an integrated circuit through a set of contacts (often embodied as "pads" or "balls") arranged across a major surface of the package. Instead of leads emanating from the perimeter side of the package, contacts are placed on the major surface and emanate from a generally flat bottom surface of the package.
The purpose of the CSP is to occupy as little area as possible, preferably about the area of the encapsulated IC. Thus, CSP leads or contacts generally do not extend beyond the outline perimeter of the package. The lack of "leads" on the package side reflects most stacking techniques designed for lead packages that are not suitable for CSP stacking.
CSP can reduce the size and weight parameters for many applications. For example, micro-ball grid arrays (μ BGA) for flash and SRAM and wire bonding on tape or grid laminated CSP for SRAM or EEPROM have been applied in many applications. CSPs are a wide variety of packages ranging from near chip size to die size packages, such as the Die Size Ball Grid Array (DSBGA) recently introduced in the proposed JEDEC Standard 95-1 for DSBGA. To meet the increasing demand for increased memory capacity while reducing cost and form factor, CSP technologies for integrating integrated circuits in CSP technology have recently been developed. For example, Sharp, Hitachi, Mitsubishi and Intel have recently worked on the support for flash and SRAM specifications known as S-CSP. However, those S-CSP specifications describe stacking multiple dies within a single chip scale package and do not provide techniques for stacking chip scale packages. Stacking integrated circuits within a single package requires a particular technology, including modification and significant expense within the package, which can have a series of weaknesses.
There are several known techniques for stacking packages that are hinged in chip scale technology. The assignee of the present invention has developed the aforementioned system for staging BGA packages in a space-saving topology. The assignee of the present invention holds a system for stacking BGA packages on a DIMM in a RAMBUS environment.
In US patent No.6205654B1, owned by the assignee of the present invention, a stacked ball grid array package system is described that employs lead carriers to extend connectable points out of the package. Other known techniques add to the structure of the stacked BGA package I C. Other known techniques build up CSPs on DIMMs, with the packages placed at an angle. These techniques provide an alternative, however, require topologies of additional cost and complexity.
US patent No.6262895B1 to Forthun ("the Forthun patent") is intended to disclose a technique for packaging ICs in a stacked chip size. The Forthun patent discloses a "package" that appears as a flex circuit (flexcircuit) that is partially wrapped about the CSP. Flex circuits are defined as having arrays of pads on the top and bottom surfaces of the flex.
The flex circuit of the Forthun "package" has an array of pads on its upper surface and an array of pads centrally located with respect to its lower surface. There are third and fourth arrays on the curved lower surface on opposite sides of the array of pads from the central lower surface. To produce a Forthun package, the CSP contacts an array of pads on the upper surface of the flex circuit. As described in the Forthun patent, the contacts on the lower surface of the CSP protrude through "slits" in the pads on the upper surface and through the flex from the pads of the lower surface array and thus from the bottom surface of the package. Thus, the CSP contacts serve as contacts for the package. The curved edge is partially wrapped about the CSP to adjacently place the third and fourth pad arrays on the upper major surface of the CSP to create from the combination of the third and fourth pad arrays a fifth pad array for connection to another such package. Thus, as introduced in the Forthun publication, the CSP stacked module produced with the package will appear as a flex circuit wrapped about each CSP in the module.
The aforementioned known methods of stacking CSPs obviously have a number of drawbacks, including complex structural arrangements and thermal or high frequency performance issues. Reliability of chip scale packages is generally of great concern. During such reliability evaluations, CSP devices often exhibit temperature cycling performance issues. The CSP is typically mounted directly on the PWB or other platform at a height offset only from the PWB by the array of solder balls or pads emanating from the lower surface of the CSP. As a result, stresses resulting from temperature gradients over time are concentrated in the short lever arms of the low-height ball array. Problems associated with temperature cycling performance in individual CSPs tend to arise in prior art CSP stacking schemes where the stack deviates only from the height of the lower CSP ball grid array from the PWB or application platform.
Thermal performance is also an important feature in CSP stacks. To increase the dissipation of heat generated by the constituent CSPs, the thermal gradient between the lower CSP and the upper CSP in the CSP stack or module should be minimized. However, prior art approaches to CSP stacking emphasize the minimization of thermal gradients in the disclosed structure.
There is therefore a need for techniques and systems for stacking integrated circuits packaged in chip scale technology packages that provide thermally efficient, reliable structures that perform well at higher frequencies without adding an additional height to the stack, while making the product cost reasonable with materials and methods that are already known and used.
Detailed Description
Fig. 1 is an elevational view of a module 10 designed in accordance with a preferred embodiment of the present invention. Module 10 includes upper CSP12 and lower CSP 14. Each CSP12 and 14 has an upper surface 16 and a lower surface 18 and opposite sides 20 and 22.
The present invention uses CSP packages of various types and configurations, such as die-sized and near-chip-sized and various ball grid array packages known in the art. These will be collectively known herein as chip scale package integrated Circuits (CSPs), and the preferred embodiments will be described in terms of CSPs, although the particular structure used in the exemplary figures is not intended as a limitation. For example, the elevation views of FIGS. 1 and 2 depict a contoured CSP as is known in the art, with the understanding that the figures are exemplary only. The following figures illustrate embodiments of the invention that employ CSPs of other configurations as examples of another of the many alternative CSP configurations to which the invention may be applied. The invention is useful in a wide range of CSP structures available in the technology of arrays of connectable elements emanating from at least one major surface, with good results. The present invention advantageously employs CSPs that include memory circuits, while the use of logic and computational circuits produces good results, with no commensurate PWB or other board surface area consumption, while adding capacity.
Typical CSPs, such as ball grid arrays ("BGA"), micro-ball grid arrays ("μ BGA"), and fine pitch ball grid arrays ("FBGA") packages have an array of connectable contacts, such as leads, pads, solder balls, or balls extending from the lower surface 18 of the plastic housing in any of several patterns and pitches. The outer portions of the connectable contacts are often terminated with solder balls. Fig. 1 shows CSP contacts 24 along lower surfaces 18 of CSPs 12 and 14. CSP contacts 24 provide connections to integrated circuits within the respective packages. CSP contacts 24 collectively include CSP array 26, and CSP arrays 261 and 262, collectively including CSP array 26, are shown with respect to lower CSP14 in the particular package structure depicted.
In fig. 1, flex circuits ("flex," "flex circuit," or "flex circuit structure") 30 and 32 are shown partially wrapped about lower CSP14, flex 30 partially wrapped about side 20 of lower CSP14, and flex 32 partially wrapped about side 22 of lower CSP 14. Sides 20 and 22 may act as sides or ends if the CSP is particularly thin. Any flexible or suitable substrate having multilayer innerlayer connectivity can be used as the flex circuit of the present invention. The entire flex circuit may be flexible or one skilled in the art will recognize that a PCB structure that is flexibly fabricated in certain areas (to have conformability around the lower CSP14 and rigidity in other areas along the CSP surface for planarity) may be employed as an alternative to the flex circuit of the present invention. For example, a structure known as stiff and flexible may be applied.
Portions of flex circuits 30 and 32 are secured to upper surface 16 of lower CSP14 by adhesive 34, adhesive 34 being shown as a tape adhesive, which may be a liquid adhesive or which may be placed in discrete locations on the package. The adhesive 34 is preferably thermally conductive. The use of an adhesive comprising a flux in the assembly of the module 10 produces good results. Layer 34 may also be a thermally conductive medium to promote heat flow between CSPs of module 10.
Flex circuits 30 and 32 may be a multi-layer flex circuit structure having at least two conductive layers. The conductive layer is preferably a metal such as alloy 110. It will be seen that the use of multiple conductive layers provides advantages and those skilled in the art will recognize that the creation of distributed capacitance on the module 10 reduces noise or bounce effects that can degrade signal integrity, particularly at high frequencies. The module 10 of fig. 1 has module contacts 36 collectively identified as a module array 38.
Fig. 2 shows a module 10 designed according to a preferred embodiment of the invention. Fig. 2 illustrates the use of an underfill material 40, which is provided in a preferred embodiment, to assist in establishing conformal structural regions of the module 10. The planarity of the module is enhanced by the underfill material 40. The underfill material 40 is preferably thermally conductive. In another embodiment, a heat spreader or thermal medium may be placed as indicated by reference numeral 41. Upper flex contact 42 and lower flex contact 44 at one of the conductive layers of flex circuits 30 and 32 can be identified in fig. 2. Upper flex contact 42 and lower flex contact 44 are conductive materials, preferably solid metals. Lower flex contacts 44 collectively are a lower flex contact array 46. The upper flex contacts 42 are collectively an upper flex contact array 48. Only certain upper flex contacts 42 and lower flex contacts 44 may be identified in fig. 2 to maintain clarity of the drawing. It should be understood that each flex circuit 30 and 32 has an upper flex contact 42 and a lower flex contact 44. Lower flex contacts 44 apply lower CSP14 and upper flex contacts 42 apply upper CSP 12. Fig. 2 has the area marked "a", which is subsequently shown in fig. 3 in an enlarged view.
Fig. 3 depicts the area marked "a" in fig. 2 in an enlarged view. Fig. 3 illustrates the connection between example CSP contacts 24 and module contacts 36 through lower flex contacts 44, illustrating the solid metal path from lower CSP14 to module contacts 36 and thus to the application PWB to which the module may be connected. Those skilled in the art will appreciate that heat transfer from the module 10 is thereby facilitated.
With continued reference to fig. 3, CSP contacts 24 and module contacts 36 together offset module 10 from the application platform, e.g., PWB. The combined height of CSP contacts 24 and module contacts 36 provides a moment arm that is longer than the height of only a single CSP contact 24. This provides a longer moment arm through which temperature gradient stress (e.g., as represented by temperature cycling) can be distributed over time.
The bend 30 is shown in fig. 3 as comprising multiple layers. The bend 30 has a first outer surface 50 and a second outer surface 52. Flex circuit 30 has at least two conductive layers inside first and second outer surfaces 50 and 52. There may be more than two conductive layers in bends 30 and 32. In the preferred embodiment, first conductive layer 54 and second conductive layer 58 are interior to first and second outer surfaces 50 and 52. An intermediate layer 56 is present between the first conductive layer 54 and the second conductive layer 58. More than one intermediate layer may be present, and preferably one polyimide intermediate layer.
As depicted in fig. 3 and as will be seen in greater detail in subsequent figures, lower flex contact 44 is preferably formed of metal at the level of second conductive layer 58 inside second outer surface 52. In the preferred embodiment, lower flex contact 44 is a solid metal and is comprised of a metal alloy such as alloy 110. This creates a solid metal path from lower CSP14 to the application board, thereby providing a significant thermal path for dissipating the heat generated in module 10.
Fig. 4 is an enlarged detail view of an exemplary connection between example CSP contact 24 and example module contact 36 through lower flex contact 44, illustrating a solid metal path from lower CSP14 to module contact 36, and thus to an application PWB to which module 10 may be connected. As shown in fig. 4, lower flex contact 44 is at second conductive layer 58, and second conductive layer 58 is internal to first and second outer surface layers 50 and 52, respectively, of flex circuit 30.
FIG. 5 is an enlarged depiction of an exemplary area around lower flex contact 44 in a preferred embodiment. Openings 60 and 62 are provided in first and second outer surface layers 50 and 52, respectively, to provide access to the particular lower flex contact 44 that is present at the level of second conductive layer 58 in the flex. Upper flex contacts 42 are contacted by CSP contacts 24 of upper CSP 12. Lower flex contact 44 and upper flex contact 42 are specific areas of conductive material (preferably a metal such as alloy 110) at the level of second conductive layer 58 in the flex. Upper flex contact 42 and lower flex contact 44 are separated in second conductive layer 58 as shown in subsequent figures, and upper flex contact 42 and lower flex contact 44 may be connected to or isolated from the conductive plane of second conductive layer 8. The distinction of lower flex contact 44 from second conductive layer 58 is depicted in fig. 5 by demarcation gap 63 shown at second conductive layer 58. Where upper or lower flex contact 42 or 44 is not completely isolated from second conductive layer 58, the bounding gap does not extend completely around the flex contact as shown, for example, by lower flex contact 44C in subsequent fig. 12. CSP contacts 24 of lower CSP14 pass through openings 60 through first outer surface layer 50, first conductive layer 54, and intermediate layer 56 to make contact with appropriate lower flex contacts 44. Through the second outer surface layer 52 openings 62, the module contacts 36 pass through the second outer surface layer 52 to contact the appropriate lower flex contacts 44.
Respective CSP contacts 24 of upper CSP12 and lower CSP14 are connected at the level of second conductive layer 58 in flex circuits 30 and 32 to interconnect the appropriate signal and voltage contacts of the two CSPs. The various CSP contacts 24 of upper CSP12 and lower CSP14 carrying ground (VSS) signals are connected at the level of first conductive layer 54 in flex circuits 30 and 32 by vias through intermediate layer 56 to connect the levels, the structure of which will be described in further detail subsequently. Thereby connecting CSPs 12 and 14. Thus, when flex circuits 30 and 32 are placed with respect to lower CSP14, corresponding CSP contacts 24 of each of upper and lower CSPs 12 and 14 make contact with upper and lower flex contacts 42 and 44, respectively. Connecting selected upper flex contacts 42 and lower flex contacts 44. Thus, module contacts 36 make contact with upper and lower CSPs 12 and 14 by making contact with lower flex contacts 44.
In a preferred embodiment, module contacts 36 pass through openings 62 in second outer layer 52 to contact lower CSP contacts 44. In certain embodiments, as will be shown subsequently, module 10 will present module contact array 38 having a greater number of contacts than the constituent CSPs of module 10. In this embodiment, some of module contacts 36 may be in contact with lower flex contacts 44, with lower flex contacts 44 not in contact with one of CSP contacts 24 of lower CSP14 and connected with CSP contacts 24 of upper CSP 12. This allows module 10 to express a wider data path than the constituent CSPs 12 and 14. Module contacts 36 may also contact lower flex contacts 44 to provide a location through which different levels of CSP in the module may be enabled when unused CSP contacts are not available or convenient for that purpose.
In a preferred embodiment, first conductive layer 54 serves as a ground plane, while second conductive layer 58 provides the function of being a signal conductive layer and a voltage conductive layer. Those skilled in the art will note that the function of the first and second conductive layers may be reversed with concomitant changes in the openings and the equivalent amount of interconnects.
Those skilled in the art will recognize that the interconnection of respective voltage CSP contacts 24 of upper and lower CSPs 12 and 14 provides a thermal path between the upper and lower CSPs to assist in mitigating thermal gradients within module 10. This flattening of the thermal gradient profile across module 10 is further facilitated by the connection of common ground CSP contacts 24 of upper and lower CSPs 12 and 14 through first conductive layer 54. Those skilled in the art will note that there is at least one intermediate layer 56, which in the preferred embodiment is polyimide, between the first and second conductive layers 54 and 58. The placement of this intermediate layer combination between the conductive ground first conductive layer 54 and the signal/voltage conductive second conductive layer 58 provides a distributed capacitance that helps mitigate ground bounce phenomena to improve the high frequency performance of the module 10.
In a preferred embodiment, fig. 6 depicts a first outer surface layer 50 that is curved 30 (i.e., to the left in fig. 1). This view is looking down on the bend from the perspective of first conductive layer 54 to bend 30. Throughout the figures, position "B" is a directional diagram for the bend 32 and the transverse-to-layer bend layer 30. An opening 60 is opened through first outer surface layer 50, first conductive layer 54, and intermediate layer 56. CSP contacts 24 of lower CSP14 pass through openings 60 of first outer surface layer 50, first conductive layer 54, and intermediate layer 56 to the level of second conductive layer 58 of flex 30. At second conductive layer 58, selected CSP contacts 24 of lower CSP14 make contact with selected lower flex contacts 44. The lower flex contacts 44 provide several types of connections in the preferred embodiment as will be described with reference to subsequent fig. 12. When module 10 is assembled, a portion of flex 30 will wrap around side 20 of lower CSP14 to place end 62 on upper surface 16 of lower CSP 14.
In a preferred embodiment, fig. 7 depicts a first outer surface layer 50 that is curved 32 (i.e., to the right in fig. 1). The view is from above the bend looking down onto bend 32 from the perspective of first conductive layer 54. The position marker "B" is oriented relative to the views of fig. 6 and 7. Viewing fig. 6 and 7, it will be understood that the reference "B" for each view is placed closer to each other than any corner of the other view of the paired views of the same layer. As shown in fig. 7, openings 60 are formed through first outer surface layer 50, first conductive layer 54, and intermediate layer 56. CSP contacts 24 of lower CSP14 pass through first outer surface layer 50, first conductive layer 54, and openings 60 of intermediate layer 56 to the level of second conductive layer 58 of flex 30. At second conductive layer 58, selected CSP contacts 24 of lower CSP14 make contact with lower flex contacts 44. The lower flex contacts 44 provide several types of connections in the preferred embodiment as will be described with reference to subsequent fig. 12. When module 10 is assembled, a portion of flex 32 will wrap around side 22 of lower CSP14 to place end 64 on upper surface 16 of lower CSP 14.
Fig. 8 depicts first conductive layer 54 of bend 30. Opening 60 continues to open an aperture in flex 30 through which CSP contacts of lower CSP14 pass to second conductive layer 58 and thus to selected lower flex contacts 44 at the level of second conductive layer 58.
Those skilled in the art will recognize that because flex 30 is partially wrapped about side 20 of lower CSP14, first conductive layer 54 becomes the lowermost conductive layer of flex 30 from the perspective of upper CSP12 on the portion of flex 30 disposed on upper surface 16 of lower CSP 14. In the illustrated embodiment, those CSP contacts 24 of upper CSP12 that provide a ground (VSS) connection are connected to first conductive layer 54. But first conductive layer 54 is located below second conductive layer 58 and over the portion of flex 30 that is wrapped around lower CSP 14. Accordingly, some means must be provided to connect upper flex contact 42 to first conductive layer 54, with ground-conveying CSP contact 24 of upper CSP12 connected to upper flex contact 42. Thus, in the preferred embodiment, those upper flex contacts 42 that contact ground-transferring CSP contacts 24 of upper CSP12 have vias that route through intermediate layer 56 to first conductive layer 54. The locations of those vias that meet first conductive layer 54 are shown in fig. 8 as vias 66. These vias may be "on-pad" or coincident with the flex contacts to which they are connected. Those skilled in the art will note the matching between vias 66 shown in fig. 8 and vias 66 shown in subsequent figures of second conductive layer 58 of the preferred embodiment. In the preferred embodiment, the through-hole 66 in the position consistent with fig. 8-12 is one through-hole. To simplify the illustration, the through-holes depicted in the drawings are shown larger in diameter than in the manufacturing embodiment. Those skilled in the art will recognize that the connection between the disposed conductive layers may be provided by vias (on or off the pads), any of several well-known techniques such as plated holes or solid lines or wires, and not necessarily literally vias.
An off-pad via 74 is also shown in fig. 8. An off-pad via 74 is provided on first conductive layer 54 near but not coincident with selected opening 60. Off-pad vias 74 connect selected lower flex contacts 44 to first conductive layer 54, as opposed to vias 66 connecting selected upper flex contacts 42 to first conductive layer 54. In the vicinity of upper flex contacts 42, second conductive layer 58 is between the CSP connected to module 10 by upper flex contacts 42 (i.e., upper CSP12) and first conductive layer 54. Thus, vias between ground transmitting upper flex contacts 42 and first conductive layer 54 may be directly attached to selected upper flex contacts 42, with ground signals transmitted through selected upper flex contacts 42. In contrast, near lower flex contacts 44, first conductive layer 54 is between the CSP connected to module 10 by lower flex contacts 44 (i.e., lower CSP14) and second conductive layer 58. Thus, the path between ground-transferring lower flex contact 44 and first conductive layer 54 is offset from the selected lower flex contact 44 by off-pad via 74 shown in the offset position.
Fig. 9 illustrates first conductive layer 54 of flex 32. The application of the position reference "B" is relative to the orientation of fig. 8 and 9. Opening 60, via 66 and off-pad via 74 are shown in fig. 9. Fig. 9 also shows actuation vias 68 and 70 and actuation traces 72. Enable vias 70 connect the pad exterior to selected lower flex contacts 44 corresponding in the preferred embodiment to unused CSP contacts of lower CSP12 (i.e., N/C). Module contact 36 in this position transmits an enable signal (C/S) for upper CSP12 through the selected lower flex contact 44 (which is at the level of second conductive layer 58) to off-pad enable via 70, which off-pad enable via 70 transmits the enable signal to first conductive layer 54 and thus to enable trace 72. Enable trace 72, in turn, transmits an enable signal to enable via 68, which enable via 68 extends through intermediate layer 56 to a selected upper flex contact 42 at the level of second conductive layer 58 at the contact made with the C/S pin of upper CSP 12. Thus, upper and lower CSPs 12 and 14 are independently enabled.
Fig. 10 depicts intermediate layer 56 of flex 30. The opening 60 is shown in the intermediate surface 56. CSP contacts 24 of lower CSP14 pass through openings 60 in intermediate layer 58 to reach lower flex contacts 44 at the level of second conductive layer 58. Those skilled in the art will note that in the preferred embodiment, the openings 60 are narrower in diameter than they behave in the first outer layer 50. Vias 66, off-pad vias 74, and enable vias 68 and 70 pass through intermediate layer 56 to connect selected conductive areas at the level of first and second conductive layers 54 and 58, respectively. Fig. 11 depicts intermediate layer 56 of flex 32 showing opening 60, via 66, off-pad via 74, and enable vias 68 and 70 through intermediate layer 56.
Fig. 12 depicts second conductive layer 58 of flex 30 of the preferred embodiment of the present invention. Various types of upper flex contacts 42, various types of lower flex contacts 44, signal traces 76, and VDD plane 78 are depicted, as well as the previously described vias 66 and off-pad vias 74. Throughout fig. 12 and 13, only example specific features are shown to clarify the drawings. Flex contact 44A is connected to a corresponding selected upper flex contact 42A with signal trace 76. To enhance the clarity of the drawing, the exemplary respective flex contacts 44A and 42A are only literally shown in FIG. 12. As shown, in the preferred embodiment, signal traces 76 exhibit a path that is determined to provide a substantially equal signal length between corresponding flex contacts 42A and 44A. As shown, trace 76 is separated from the larger surface area of second conductive layer 58, represented as VDD plane 78. VDD plane 78 may be one or more depicted portions, preferably one portion. Lower flex contact 44C provides a connection to VDD plane 78. In a preferred embodiment, upper flex contacts 42C and lower flex contacts 44C connect upper CSP12 and lower CSP14, respectively, with VDD plane 78. Lower flex contact 44, which is connected to first conductive layer 54 by off-pad via 74, is shown as lower flex contact 44B. To enhance the clarity of the drawing, the exemplary lower flex contacts 44B are only literally shown in FIG. 12. Upper flex contact 42, which is connected to first conductive layer 54 by via 66, is shown as upper flex contact 42B.
Fig. 13 depicts second conductive layer 58 of right side bend 32 in accordance with a preferred embodiment of the present invention. Various types of upper flex contacts 42, various types of lower flex contacts 44, signal traces 76, and VDD plane 78 are depicted, as well as the previously described vias 66, off-pad 74, and enable vias 70 and 68. Fig. 13 illustrates upper flex contact 42A connected to lower flex contact 44A by trace 76. VDD plane 78 provides a voltage plane at the level of second conductive layer 58. Lower flex contacts 44C and upper flex contacts 42C connect lower CSP14 and upper CSP12, respectively, to VDD plane 78. Lower flex contact 44D is shown with activation via 70 previously described. Corresponding upper flex contact 42D is connected to lower flex contact 44D by enable vias 70 and 68, and enable vias 70 and 68 are connected to each other by previously described enable traces 72 at the level of first conductive layer 54 of flex 32.
Fig. 14 depicts second outer layer 52 of flex 30. The opening 62 is shown. Those skilled in the art will recognize that module contacts 36 pass through openings 62 to contact the appropriate lower flex contacts 44. When flex 30 is partially wrapped about side 20 of lower CSP14, a portion of second outer layer 52 becomes the uppermost layer of flex 30 from the perspective of upper CSP 12. CSP contacts 24 of upper CSP12 pass through openings 64 to second conductive layer 58 and make contact with appropriate upper flex contacts 42 located at that level. Fig. 15 reflects second outer layer 52 of flex 32 and reveals openings 64 and 62. Module contacts 36 pass through openings 62 to contact the appropriate lower flex contacts 44. CSP contacts 24 of upper CSP12 pass through openings 64 to second conductive layer 58 and make contact with appropriate upper flex contacts 42 located at that level.
Fig. 16 depicts another preferred embodiment of the present invention, showing module 10. Those skilled in the art will recognize that the embodiment depicted in fig. 16 differs from that of fig. 12 in the presence of module contacts 36E. Module contacts 36E provide a portion of the data path of module 10 and may provide a means for making up the various starts of the CSP. Module contacts 36E, which are not used in a wide datapath offering, may provide contact points to provide enable signals to differently enable upper CSP12 or lower CSP 14.
In the broad datapath module 10, the combination of the datapaths making up the upper CSP12 and lower CSP14 provide a module 10, the module 10 being expressed as a module datapath of twice the width of the datapaths making up the CSPs in the two high modules 10. The preferred method of combining is associative and other combinations may be applied to combine the datapaths of CSPs 12 and 14 on the arrays of module contacts 36 and 36E.
As an example, fig. 17, 18 and 19 are provided to illustrate that the use of added module contacts 36E in alternative embodiments of the present invention provides a wider data path for module 10 than is present in constituent CSPs 12 and 14. FIG. 17 illustrates pin outputs for a DIDR-II FBGA package. Fig. 18 illustrates the pin out set through module contacts 36 and 36E of module 10, representing an 8-bit wide data path. Module 10 is designed in accordance with the present invention, and in an exemplary embodiment, module 10 includes upper CSP12 and lower CSP14 that are DDR-II compliant in timing, each of which is only 4 bits wide in the datapath. It will be appreciated that the module 10 depicted in fig. 18 expresses an 8-bit wide data path. For example, fig. 18 depicts different DQ pins in the power supply to aggregate into 8 bits between upper CSP12 ("top") and lower CSP14 ("bottom"). Fig. 19 illustrates the pin-out provided through module contacts 36 and 36E of module 10, representing a 16-bit wide data path. Module 10 is designed in accordance with the invention and is made up of upper CSP12 and lower CSP14 that follow DDR-II in timing in this example embodiment, but are each only 8 bits in the datapath. Those skilled in the art will recognize that the wide datapath embodiment may be applied to any of a variety of CSPs available in the art, and that such CSPs need not be DDR compliant.
Fig. 20 illustrates a general pin-out of a memory circuit configured as a CSP and usable in the present invention. The individual array locations are indicated by the JEDEC convention for numbered columns and alphabetical rows. Unoccupied central regions (e.g., A3-A6; B3-B6, etc.). CSP contacts 24 are present at alphanumeric positions such as a3 as shown by example CSP contacts 24. Fig. 21 depicts second metal layer 58 of flex 30 in another embodiment of the invention in which module 10 expresses a wider data path than represented by either of the constituent CSPs 12 and 14. Lower flex contacts 44E do not contact CSP contacts 24 of lower CSP14 but rather contact module contacts 36E, thereby providing a datapath for module 10 that is 2 n-bits wide with selected module contacts 36, where the datapaths of CSPs 12 and 14 have a width of n-bits. As shown in fig. 21, lower flex contact 44E is connected to upper flex contact 42E. As previously shown in fig. 14, the opening 62 passes through the second outer layer 52. In another preferred embodiment of second conductive layer 58 shown in fig. 21, module contacts 36 and 36E pass through openings 62 in second outer layer 52 of flex circuit 30 to make contact with the appropriate lower flex contacts 44.
Fig. 22 illustrates second metal layer 58 of flex 32 in another embodiment of the present invention in which module 10 expresses a wider datapath than that expressed by either of the constituent CSPs 12 and 14. Lower flex contacts 44E do not contact CSP contacts 24 of lower CSP14 but rather contact module contacts 36E, thereby providing a datapath for module 10 that is 2 n-bits wide with selected module contacts 36, where the datapaths of CSPs 12 and 14 have a width of n-bits. As shown in fig. 22, lower flex contact 44E is connected to upper flex contact 42E. As previously shown in fig. 14, the opening 62 passes through the second outer layer 52. In another preferred embodiment of second conductive layer 58 shown in fig. 22, module contacts 36 and 36E are contacted with the appropriate lower flex contacts 44 through openings 62 in second outer layer 52 of flex circuit 32.
Particularly in the embodiment depicted in fig. 21 and 22, module contact 36E contacts flex contacts 44E and 44 EE. Those skilled in the art will recognize that lower flex contacts 44E are eight (8) in number in the illustrated embodiment, and that there is another lower flex contact indicated by reference numeral 44EE shown in fig. 21. Lower flex contact 44EE is contacted by one of module contacts 36E to provide differential actuation between the upper and lower CSPs. Those skilled in the art will recognize that lower flex contacts 44E connect with corresponding upper flex contacts 42E. CSP contacts 24 of upper CSP12 transmitting the data make contact with upper flex contacts 42E. Thus, combining the datapaths of upper CSP12 and lower CSP14 provides a wide datapath on module 10. With the connections described in fig. 21 and 22, lower flex contacts 44E of flex circuits 30 and 32 transfer to module contacts 36E, the datapath of upper CSP12, while other lower flex contacts 44 transfer the datapath of lower CSP14 to module contacts 36, thereby providing module 10 with a module datapath that is a combination of the datapaths of upper CSP12 and lower CSP 14. In the particular embodiment depicted in FIGS. 21 and 22, module 10 represents a 16-bit datapath and CSP12 and CSP14 each represent an 8-bit datapath.
Although the present invention has been described in detail, it will be apparent to those skilled in the art that the present invention may be embodied in various specific forms, and various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are to be considered in all respects only as illustrative and not restrictive, and the scope of the invention is, therefore, indicated by the appended claims.