The present invention is a divisional application of a patent application having the same name and having an application number of 95193897.5, which was filed on 13.6.1995.
Detailed Description
Fig. 1 depicts a data field structure proposed for use in a system that processes packetized data streams in a large alliance HDTV system in the united states. An output symbol data stream representing the data field structure is generated by the transport processor from input data packets from a preceding transport processor. The transport processor and transport processor will be discussed in conjunction with fig. 4. Each data field structure includes a housekeeping field sync segment (which does not contain payload data) preceding a group of field data segments, and each field data segment has an associated sync portion. Each field data segment includes a 187-byte data packet portion, a one-byte sync portion at the beginning of each data segment, and a Forward Error Correction (FEC) portion following the data. Associated with each segment is an interval "Y" that defines the data failure interval between each data packet. The transport processor provides the input data of the 188 byte packet plus the segment sync to the transport processor. The transport processor adds the FEC coding and field sync overhead information and generates an output segment in the form of symbols to be transmitted to the output transport channel.
The sync and field sync portions associated with each segment facilitate the collection of the packet and symbol clocks at the receiver end under extreme noise and interference conditions, as well as phase locking. The 4-symbol synchronization part is binary (2-level) in order to make the recovery of the packet and clock more robust and appears as a regularly single repeating pattern to allow reliable detection at the receiver under noise and interference conditions. The synchronization symbols are not Reed-Solomon (Reed-Solomon) coded or trellis coded, nor are interleaved codes. The field sync component may contain a pseudo-random sequence and it serves several functions. It provides a method of determining the start of each data field and can also be used by an equalizer in the receiver as a training reference signal to remove intersymbol interference and other forms of interference. It also provides a method by which a receiver can determine whether to use an interference suppression filter, and it can also be used for diagnostic purposes, such as measuring signal-to-noise characteristics and channel response. The field sync portion may also be used by a phase tracking network in the receiver to determine phase control loop parameters. Like the sync portion, the field sync portion is not error correction coded, trellis coded, or interlaced. In this example, the data fields do not necessarily correspond to interlaced image fields, which constitute an image frame of an NTSC television signal.
Fig. 2 shows, in general form, the processing of one type of data field segment 22 by the transport processor and output processor unit of fig. 4. The segment is one of 312 data segments of a given data field, for a total of 832 symbols. The segment shown in fig. 2 comprises a 187-byte MPEG-2 transport data packet preceded by a one-byte sync portion followed by a subsequent FEC portion comprising 20 RS (Reed-Solomon) parity bytes. Each transport packet, as used in the big alliance HDTV system, includes a 4-byte concatenated data header, the first byte of which is a sync byte that facilitates synchronization of the packet. This may be followed by an optional adaptation header, with the remainder of the packet being an MPEG data payload. The one-byte sync part is converted into 4 symbols before being subjected to 2-VSB (vestigial sideband) modulation. The 187 byte MPEG packet segment and FEC encoding portion are 2/3 trellis encoded and converted into 828 symbols before 8-VSB modulation. Techniques for performing such 2-VSB and 8-VSB modulation are well known. The final output field segment 24, which is transmitted to the output channel, contains a 4-symbol sync portion followed by a 828-symbol data field portion containing MPEG data and FEC data.
Fig. 3 shows a packetized data stream consistent with the data field structure shown in fig. 1. Each data field has 312 segments, each segment including sync, data and FEC portions, and more particularly, each data field segment includes an interval of 188 data bytes ("packet bytes") including sync bytes and an interval of 20 FEC bytes. 188 clock intervals (cycles) accompany the 188 data bytes of each segment, and 20 clock intervals (cycles) accompany the 20 FEC bytes of each segment. When the time to insert the field sync segment arrives, the transmission of the data/FEC segment should be prohibited for an interval of 288 clock cycles corresponding to one segment clock interval (i.e., 20+188+20 clock cycles). The field sync segment does not contain a data payload as contained in each packet data segment. This splitting of the data stream undesirably creates uneven spacing or gaps between packets as shown in fig. 3. This split data flow and uneven inter-packet gaps greatly complicates signal control and hardware requirements at the transmitter and receiver ends for the interface between the transport processor and the transport processor, and also reduces data throughput. Furthermore, it is difficult to synchronize with the data field structure when playing back prerecorded materials. The task of recording packetized data streams on a broadcaster's or consumer's recording device is greatly complicated by the non-uniform gaps between packets, since the non-uniform inter-packet gaps must be maintained as they occur, i.e., the recording device must faithfully reproduce the timing of the MPEG packets. In addition, non-uniform gaps must also be maintained in the output signal produced by the demodulator at the receiver.
A system according to the present invention addresses and solves the above-described problems caused by non-uniform inter-packet gaps due to irregular overhead data. In the disclosed system, a transport processor processes data packets at a constant uniform data rate according to a clock selected as a function of the data modulation scheme used. The clock also controls the operation of a buffer/interface network located between the transport processor and the transport layer that processes data according to a predetermined data field structure. An advantage of the disclosed system is that the original data field structure does not have to be modified to achieve the desired operation at a constant uniform data rate. In addition, parameters such as symbol rate, segment interleaving, RS (Reed-Solomon) error correction coding, and synchronization components are not affected.
In the transmitter system of fig. 4 in accordance with the present invention, transport processor 14 operates at an uninterrupted constant uniform data rate for providing MPEG byte data at a uniform data rate to buffer interface network 16. The interface 16 provides the output byte data at a non-uniform rate to the data field construction network and encoder 17. The network 17 operates at a non-uniform data rate to generate a sequence of output symbol field structures based on byte data and non-data overhead information (FEC and field sync). Network 17 requests data at a non-uniform rate via a data field packet request signal. Interface network 16 converts the request into a uniform data rate request signal (to transport packet request) that is provided to transport processor 14.
More specifically, transport processor 14 is included in a system transport layer, and network 17 is included in a system transport layer (which also includes output processor 18), the system transport layer being separated from the transport layer by interface 16. Data source 12 comprises an MPEG compatible data compression network and provides MPEG-2 byte data to transport processor 14. The transport processor packs the MPEG bytes into fixed length data words which ultimately constitute fixed length (188 byte) data packets. Each packet is preceded by a header containing information illustratively representing the source of the program, the type of service, etc., and other information describing and relating to the data in the payload data of the associated packet. Transport processor 14 also synchronously inserts 1 byte MPEG packets into the beginning of each packet. The transport processor 10 performs operations including input buffering, FEC error detection/correction coding, field sync insertion, trellis coding to improve carrier-to-noise ratio, interleaving to reduce the impact of data burst transmission errors, and symbol transformation.
The network 17 implements a data field construction function in which the input data packets are structured into a data field structure including data, FEC and field sync components as previously described. Data packets are supplied from network 16 to network 17 at constant uniform inter-packet gaps so that the data field is seamlessly formed by network 17 and does not disrupt the data flow. The transmission system of fig. 4 operates according to a symbol clock SC and is clocked according to a clock derived therefrom, as will be discussed below. A suitable symbol clock frequency is 10.762237 MHz.
The disclosed system in accordance with the present invention enables the transport processor to operate at a uniform data rate without modifying the original data field structure, e.g., one field sync segment per 312 data segments, thereby producing a uniform data stream using 313 field segments. Furthermore, there is no need to interrupt the data stream in order to insert field sync overhead information between data fields.
The transmitter system of fig. 4 uses an 1/4SC clock and a 3/8SC clock, where SC is the system symbol clock. As will be seen, the 1/4SC clock is selected for signal processing because 1 byte (8 bits) includes 4 symbols when each symbol is 2 bits. It is within the scope of the present invention to prefer 3/8SC clock for the 8-VSB system and 3/4SC clock for the faster data rate 16-VSB system. In the system to be described, the network 16 contains a FIFO buffer (first in first out buffer) 46 between the output of the transport processor 14 and the data field construction network 17. Byte data packets from transport processor 14 are read from transport processor 14 and written to buffer 46 according to the 3/8SC clock, and data packets are read from buffer 46 to encoder 17 according to the 1/4SC clock. Both clocks are generated by digital circuitry rather than by the more expensive phase-locked loop network. 3/8 the SC signal clocks both the transport processor 14 and the buffer 46 so that data is transferred synchronously between the transport processor and the buffer. The same requirements apply to the receiver as will be discussed below.
Referring to fig. 6-9, the symbol clock (fig. 6) and the derived synchronous clock 1/4SC (fig. 7) are generated by a timing control network 40 (e.g., a microprocessor) in the network 17. The network 40 also generates a data field packet request message (fig. 10) which is synchronized to the symbol clock SC because the data field packet request is generated using the 1/4SC clock. Timing generator 42 in network 16 generates 3/8SC clocks (fig. 8) that are synchronized with the SC and 1/4SC clocks from timing network 40. Fig. 9 (shown for reference only) depicts a byte wide pulse that follows the occurrence of a one byte sync pulse, which occurs as the first byte at the beginning of each data packet.
3/8 the SC clock is generated by counting the periods of the symbol clock SC. The unit 42 generates 3 output pulses in every 8 symbol clock SC pulses. Fig. 7 and 8 show one possible relationship between 1/4SC clocks and 3/8SC clocks. The 3/8SC clock can be derived with an arbitrary relationship of 3 clocks out of 8 clock pulse intervals, but the three pulses must have a fixed phase relationship with the 1/4SC clock, and this same relationship must be maintained between the 3/8SC clock and the 1/4SC clock in the transmitter and receiver. The 3/8SC clock structure shown in fig. 8 has the advantage that the signal is easy to derive and align with the sync bytes (sync bytes are easily detected at the beginning of each packet) and the signal is also easy to duplicate in the receiver. Similar results are suitable for using any 6 of the 8 symbol clocks to generate 3/4SC clocks, particularly for 16-VSB signals. The relationship shown between the clocks is generated in timing control network 40 by resetting the counter with the rising edge of the 1/4SC clock, which causes the packet sync byte to be output from buffer 46. The symbol clock counts from 0 to 7, where 0 is synchronized with the packet sync byte output from buffer 46. Any 3 of the 8 counts of the symbol clock SC may be used, but the same 3 must be used in the receiver/decoder.
The timing control network 40 facilitates the generation of a data field structure including 312 data segments and 1 field sync segment. The data field packet request signal from network 40 (fig. 10, 13) assumes a high logic level for 188 bytes and a low logic level for 20 bytes according to the 1/4SC clock. The data field packet request signal (fig. 10) from controller 40 exhibits non-uniform inter-packet gaps. A part of a data field is depicted, in particular the last two data segments 311 and 312 of one data field, the field sync segment 313 at the start of the next data field, and the first data segment of the next data field. This signal presents a data "enable" interval (each comprising 188 data bytes synchronized to the 188 1/4SC symbol clocks) when data is requested, and a data "disable" interval (each comprising 20 1/4SC symbol clock intervals) when FEC information is to be added to the data stream, or 228 1/4SC symbol clock intervals when field synchronization information is to be added between the data fields. This signal is a self-oscillating input to a system control network 44 associated with network 16.
The control network 44 generates an outgoing packet request to the transport signal based on the 3/8SC and 1/4SC clocks, as shown in fig. 11. Which requests a 188 byte data packet from transport processor 14 every 313 th clock cycle of the 3/8SC clock. The packet request signal contains a constant uniform gap between packet requests to produce a uniform data rate and uninterrupted data flow. The constant uniform gap of 125 cycles of the 3/8SC clock between packet requests facilitates the seamless insertion of housekeeping data (e.g., FEC information and field synchronization between data fields) into the data stream by network 17 to produce a data field structure, as will be described later.
The disclosed system is concerned with processing a data stream having a field structure of 313 segments per field, each field consisting of a field sync segment followed by 312 data field segments. In this case, the disclosed system will operate at multiples of the 3/8SC byte clock, for example, the faster clocks included in the 3/4SC, 3/2SC, and 3SC data modulation schemes (including 8-VSB and 16-VSB, for example). These alternatives will be best understood from the following discussion in connection with fig. 10 and 11 and fig. 30, 31 and 32. From this discussion, it will also be apparent that the principles of the present invention are also applicable to other types of data field structures.
For the illustrated embodiment, the waveform of FIG. 10 is constant with the depicted 313-segment data field structure. The structure of the waveform of fig. 11 may then vary as a function of several factors as follows. Fig. 30 corresponds to fig. 11, which depicts a uniform data rate packet request sent by network 44 to transport processor 14 in an 8-VSB signal according to an 3/8SC byte clock. If a clock faster than 3/4SC is used for the same 8-VSB modulation, the packet request to the transport processor 14 will form the shape shown in fig. 31. Since the size of each data packet is fixed to 188 bytes, the data packet interval remains unchanged, again at 188 cycles of the 3/4SC clock. However, the data inhibit interval between packets is greatly increased, reaching 438 cycles of the 3/4SC byte clock. In this example, the number of cycles per data segment has increased to 626 (twice as fast as the previous example) due to a clock twice as fast as 3/4SC bytes. In other words:
626-segment clock-188 data clock (fixed) ═ 438 clocks
Although the number of bytes per segment increases, the data packet structure remains unchanged. Since each data field still comprises 312 segments, each segment containing 188 bytes of data packets and having a field sync segment as a start, the structure of the data field remains unchanged. Similar results apply to other faster clock multiples, such as 3/2SC or 3SC, where the number of byte clocks in the interval between data packets will increase proportionally. It has been found that for a 313 byte/segment clock in a 313 segment data field, the 3/8SC clock is the lowest rate clock.
Fig. 32 shows the use of the faster 3/4SC clock in the higher data rate 16-VSB modulation system. The results are the same as in fig. 30. In the 16-VSB case, the symbol clock frequency (SC) is doubled, and there can be up to twice the throughput of packets per unit time compared to the 8-VSB system. The forbidden intervals between 188 bytes-clock data interval and 125 bytes-clock data interval are the same as in the case of 8-VSB, depending on the relationship between the clock speed and the data rate of its associated modulation type. The slower 3/8SC clock is used for 8-VSB modulation at the lower data rate, while the faster 3/4SC clock is used for 16-VSB modulation at the higher data rate.
It can be seen that the desired symbol clock relationship (e.g., 3/8SC, 3/4SC, etc.) can be derived in terms of the following expression in relation to the number of symbols per field:
NX(188+Y)＝S(X+1)；
wherein X (188+ Y) and S (X +1) both represent the number of symbols per field;
(188+ Y) represents a symbol/data segment;
(X +1) represents a segment/field (e.g., 313);
s represents a symbol/segment (e.g., 832);
x represents a data segment/field (e.g., 312);
y represents an interval between data; and
n is the factor to be determined.
In the case of the 3/8SC clock in the 8-VSB system, N is found to be 8/3, and in the case of the 3/4SC clock, N is found to be 4/3.
Transport processor 14 is clocked by the 3/8SC clock to read out the data and sends out 188 bytes of MPEG data packets during 188 cycles of the 3/8SC clock in response to the packet request signal from unit 44 as shown in fig. 12. Fig. 12 actually depicts the data valid signal output by the transport processor 14 and the 188 byte data packet at the same time. The data valid signal takes the form of a packet request signal to transport (fig. 11). The data field packet request from the timing circuit 40 of the network 17 (fig. 10) and the packet request signal to the transport from the network 40 (fig. 11) are not synchronized.
Data packets (Data) from transport processor 14 are applied to a buffer 46 of network 16. The buffer is quite small, only a few packets deep. The buffer 46 also receives a data valid signal at a Write Enable (WEN) input to enable writing of data packets to the buffer 46 according to the 3/8SC Write Clock (WCK). Buffer 46 also receives a start of packet (SOP) identification from transport processor 14. The identification is generated at the beginning of each data packet and at the sync byte located at the head of each data packet. A request to transport processor 14 that requests it to send a data packet to network 17 via interface network 16 is not committed until buffer 46 reaches a predetermined fullness level (e.g., before half full). The fullness level of buffer 46 is represented by a fullness flag that is applied to a control input of controller 44.
The 188 byte data packets are clocked into the buffer 46 (FIGS. 11 and 12) every 188/313 cycles of the 3/8SC clock. During the remaining 125 cycles of the 3/8SC clock, no data is clocked into the FIFO 46. The input data rate to buffer 46 is uniform and accurately matches the output data rate from buffer 46. The output data rate is controlled by the data frame packet request signal from circuit 40. The data frame packet request signal and the packet request signal to the transport are not synchronized but are related to each other by 3/8SC and 1/4SC clock relationships.
Controller 44 comprises a logical network responsive to 3/8 the SC clock, the data field packet request signal, a buffer fullness indicator (fig. 15) from buffer 46, and a start of packet (SOP) indicator received from regulation network 45 via buffer 46, among other things. The controller 44 provides control signals (fig. 14) to a Read Enable (REN) input of the buffer 46 to enable buffered transport packet data to be read to the network 17 at the appropriate time. This process occurs as follows with reference to fig. 13-16. The signals of fig. 13 are similar to those of fig. 10 discussed previously.
In general, the read enable signal (FIG. 14) and the field data packet request signal (FIG. 13) are synchronized. The SOP flag, which is typically present at the beginning of each packet, causes controller 44 to provide an output to the REN input of buffer 46 to stop the buffer from reading data. Specifically, the controller 44 is programmed to read 188 bytes from the buffer 46 based on the SOP flag and then stop reading the buffer for a 20 byte PEC interval. This allows the FEC network 50 in the transport encoder 17 to calculate its error coding information for the packet immediately preceding the current packet held by the buffer 46. The error coding information is inserted into the data stream during the end 20 byte FEE attachment interval of the preceding packet. The need for insertion of 20 bytes of FEC overhead information by unit 50 of network 17 and for insertion of longer duration field sync overhead information by unit 58 both present a non-uniform inter-packet gap structure in the presence of data field packet requests (fig. 13) and buffer read enable signals (fig. 14). The data flow is not interrupted to accomplish this insertion of housekeeping information.
Referring to fig. 4, inserting field sync segments without stopping or disturbing the data stream is facilitated by the timing of the read/write of the buffer 46 in combination with a predetermined buffer fullness level. Packets are written from the transport processor into the buffer 46 continuously with requests for packets. Over a data field period, the exact number of data bytes needed to form a data field will be transferred from transport processor 14 to buffer 46. The buffer 46 is relatively small, in this example it is sized to accommodate 4 data packets. The predetermined buffer fullness level is 2 data packets, but this level may vary depending on the needs of the particular system. In practice, this level should be determined such that the buffer does not overflow when the buffer stops reading and inserts overhead information into the data stream for the known data interval and data inhibit interval for a given system, and otherwise it is not empty. When the buffer read is momentarily stopped to insert overhead information (e.g., field sync) into the data stream, the data packets continue to be written to the buffer 46 at a constant uniform rate (fig. 11). During this time, the buffer 46 is not completely full. The constant uniform gap between data packets (fig. 11) allows sufficient time for buffer 46 to be refilled while reading is momentarily disabled to insert overhead information. After the housekeeping information is inserted during the read inhibit interval, the data is read out of the buffer 46 again. During all of these times, transport processor 14 continuously sends data packets to buffer 46 so that the data stream flows uninterrupted while transport processor 14 processes the data packets uninterrupted.
When a faster byte clock is used, such as 3/4SC or 3/2SC, the buffer 46 will not run to full empty because of the longer inter-packet spacing in the 8-VSB. This allows additional time to refill the buffer from the transport processor.
Read enabling of the buffer 46 is also disabled by the controller 44 if the buffer fullness flag exhibits a logic low level indicating that the buffer 46 contains less than the predetermined number of data packets. At this point, the data valid signal from network 44 (fig. 16) is "low" (absent) because the read out of buffer 46 has been disabled. This may occur, for example, when the system is at initialization or after a system reset, such as at time T1. Typically, the data field structure starts at the beginning of the transmission day, and the transmission of data packets continues uninterrupted from this time on until the transmitting station is powered off at the end of the transmission day. During this time, transport processor 14 continues to send data packets to buffer 46 in accordance with the packet request to transport signal from controller 44 while read out of buffer 46 is disabled. After a predetermined number of packets have been stored and the buffer fullness condition has been met, the fullness flag (fig. 15) changes state and assumes a high logic level. The buffer 46 again receives the read enable signal to output the data packet. The operation of the buffer read enable begins at the leading edge of the first data enable interval that occurs after the fullness flag goes high due to the fullness condition being satisfied. Thus, at time T2, the first (sync) byte of the data packet is aligned with the start of the packet request from the data field packet request signal (fig. 13) and with the start of the data valid signal (fig. 16).
The adjustment circuit 45 of fig. 4 facilitates the above-described operation illustrated by fig. 13-16. Circuit 45 is shown in fig. 28 along with networks 17, 42, 44 and 46 in fig. 4. The adjustment circuit 45 includes cascaded D-type flip-flops (registers) 102 and 104 clocked by the 1/4SC read clock of the buffer 46 and by a read enable input (REN) provided from the system controller 44 to the buffer 46 as an enable signal. Data from buffer 46 is sent to transmit encoder 17 via flip-flops 102 and 104. Controller 44 generates a buffer read enable signal based on a start of packet (SOP) flag (a register delayed replica of the input packet start signal) from the output of flip-flop 102. The packet start signal is a buffer delayed replica of the SOP signal input to the buffer 46.
With continued reference to fig. 4, the 8-byte parallel data packets and the data valid signal (fig. 16) output from the network 45 are applied to respective corresponding inputs of the FEC unit 50 in the transcoder 17. The FEC unit 50 adds 20 bytes of FEC data to the data stream during the overhead interval where data is "invalid" between each data packet interval, in accordance with the waveform of fig. 16. The data stream from the FEC unit 50 is applied to a parallel-to-serial data converter 52. Unit 52 converts each parallel 8-bit byte into a set of 4 2-bit words that are output serially. The data from unit 52 is trellis encoded 2/3 by unit 54 using well known techniques to produce three output bits (two information bits and a derived redundancy bit) from every two input bits to improve signal-to-noise performance. These bits are provided according to a predetermined algorithm, examples of which are well known in the art. The encoder 54 operates in conjunction with a bit generation unit 56 which provides a third bit in accordance with a predetermined algorithm.
The output of trellis encoder 54 comprises a series of 3-bit trellis code words, with 4 3-bit words constituting a byte. A symbol converter 58 converts each 3-bit input word from encoder 54 into an output symbol and time multiplexes the output symbols with the field sync component of the predetermined value from unit 60 to produce a data stream of output symbols. In the transform function of unit 58, the output values of the 8 incremented binary numbers from unit 54, 000, 001, 010, … through 111, are transformed into the following 8 symbol levels, respectively:
-7，-5，-3，-1，+1，+3，+5，+7。
control signals for the field sync generator 60 and the inverter 58 are provided by a timing control network 40, for example, a microprocessor. The network 40 controls the operation of the field sync generator 60 so that the unit 60 can output field sync segment information during a predetermined duration of time between adjacent data fields, i.e. after every 312 data segments in question. Each field sync segment is multiplexed as intended into the data stream between the field data groups without interrupting the data flow, as discussed previously in relation to the operation of the buffer 46. Multiplexer 58 also replaces the MPEG sync portion at the start of each packet with a segment sync before output processing by unit 18.
The 8-level symbol data signal from unit 58 is provided to output processor 18 where a small pilot signal may be added to the compressed RF carrier to allow robust recovery of the carrier at the receiver under difficult reception conditions. The 8-VSB modulator in the processor 18 receives the trellis-encoded composite data signal, filters and spectrally shapes the signal for transmission in a standard 6MHz television channel, modulates (upconverts) the data signal to an Intermediate Frequency (IF) carrier, and converts the resulting signal to an RF carrier, using well-known signal processing techniques. The frequency spectrum of the baseband VSB modulated signal for this example is depicted in the upper graph of fig. 5, and the lower graph shows the relative standard 6MHz NTSC channel frequency spectrum.
Fig. 17 depicts a VSB receiver incorporating the principles of the present invention. The baseband demodulated symbol data stream from the pre-processor 72 exhibits a sequence data field structure having a non-uniform data rate as previously described. The data field processor 75, which is associated with the system transport layer, processes the symbol data field structure having a non-uniform data rate to produce output data at a non-uniform rate. Buffer interface network 84 converts the data into an MPEG byte data stream exhibiting a constant uniform data rate. The data stream is processed by a transport decoder 86 that operates uninterrupted at a constant uniform data rate to provide decoded byte data to an output processor 88. Transport decoder 86 is associated with the system transport layer.
More specifically, the signal received from the transport channel is processed by an RF tuner 70, which includes channel selection and mixing circuitry, to produce a down-converted signal. The signal is intermediate frequency filtered and synchronously detected by a pre-processing unit in a well-known signal processing technique to produce a baseband signal. The unit 72 also comprises an equalizer to compensate for amplitude and phase disturbances of the transmission channel. The symbol data output signal from unit 72 is then trellis decoded, forward error detection/correction and other signal processing in a manner inverse to that done by the transmitter system of fig. 4.
The symbol clock SC and the derived clocks 1/4SC and 3/8SC are the same as the corresponding clocks at the transmitter. Thus, the output data stream (MPEG byte data) provided to transport processor/decoder 86 corresponds to the data stream (MPEG byte data) provided by transport processor 14 in the transmitter system of fig. 4. The input symbol data applied to the symbol transformer and demultiplexer unit 74 corresponds to the output symbol data from the network 17 of fig. 4. The data stream of input symbol data contains field sync portions of relatively long duration between relatively short duration data packet groups defining respective adjacent data fields (fig. 1 and 3). Thus, the input symbol data stream of the receiver exhibits a non-uniform data rate. The non-uniform rate input symbol data stream is converted to an MPEG byte data output signal (from the network 84) containing data packets spaced by uniform gaps between packets and occurring at a constant uniform data rate before being applied to the receiver input processor 86. Such a constant uniform rate data stream advantageously facilitates data processing and data demultiplexing by transport decoder 86 in a manner that does not disrupt the data stream.
More specifically, the non-uniform rate baseband input symbol data stream produced after demodulation and equalization is applied to a symbol transformer and demultiplexer 74 which performs the inverse of the operation performed by transformer 58 of fig. 4. Unit 74 converts each symbol into a 3-bit word which is in turn trellis decoded by trellis decoder 76 into a 2-bit word in conjunction with unit 78. Unit 74 also replaces the segment sync at the beginning of each segment with the MPEG packet sync. The symbol data stream processed by element 74 is monitored by element 90 to detect the presence of control information present during field synchronization, e.g., "training" signal information for the pre-equalizer in element 72, mode selection information, and other information. This information is extracted by unit 90 and passed to the previous circuits as required by the particular system.
The output set of 4 2-bit codewords from the trellis decoder 76 is converted from a serial form to an 8-bit (1 byte) parallel form by a serial-to-parallel converter 80. The serial words from the converter 80 are applied to an error detection and correction unit 82, such as an RS (reed-solomon) decoder. The error corrected data signal from unit 82 is applied to the receiver buffer/interface network 84 along with the data valid signal, clocks SC and 1/4SC, and the packet start signal from controller 92. The SC symbol clock and 1/4SC clock are synchronized and are generated by a local oscillator in the controller. The packet start signal is generated based on the presence of a sync byte at the start of each packet. The FEC unit 82 generates a data valid signal based on the packet start signal.
The buffer/interface network 84 is similar to the transmitter network 16 and is shown in fig. 29. The interface network of fig. 29 includes FIFO buffers 100, system controllers 120, 3/8, SC clock generator 122, and scaling circuit 145, all of which exhibit characteristics similar to the inverse components used in the transmitter network of fig. 28. The buffer 100 of fig. 29 is essentially the same as the FIFO buffer 46 in the transmitter buffer network 16 of fig. 4, except that the read clock and the write clock are swapped. Specifically, the write clock input WCK of register 100 is responsive to the 1/4SC clock, while the read clock input RCK of register 100 is responsive to the 3/8SC clock. In fig. 29, the SOP input signal to register 110 is a buffered copy of the packet start signal and the SOP input to transport processor 86 is a delayed copy of the input to register 110.
With continued reference to fig. 17, the packetized baseband MPEG byte data from the network 84 is processed by a transport processor/decoder 86, which essentially performs the inverse of the operations performed by the transport processor 14 (fig. 4) at the transmitter end. Transport processor 86 decodes the data into its constituent parts. Processor 86 includes various data processing and demultiplexing circuits including header analyzers, signal routers responsive to header information, MPEG decompression networks, and other image and audio data processors that provide signals formatted as desired by video/audio processor 88 of fig. 17. The video and audio data recovered by the transport decoder 86 are processed by the video and audio networks of unit 88, respectively, to provide image and sound information suitable for reproduction.
The detector 90 in the network 75 also provides a field marking signal to a control unit 92. The field mark command controller 92 does not write field sync segments to the buffer network 84, thereby resulting in an output data stream without field sync portions. The output data packets from the buffer network 84 form a single data stream without a synchronization portion, whereby the MPEG byte data stream from the network 84 exhibits a constant uniform data rate and a constant uniform gap between packets.
Removal of the additional field sync bytes without stopping or disturbing the data stream is facilitated by the timed manner of reading/writing of the buffer 84 in combination with a predetermined buffer fullness level. When packets are available, the packets are continuously read from the buffer 46 to the transport processor. The exact number of data bytes required to form a data field will be transferred from buffer 84 to transport processor 86 during a data field period. Buffer 84 has the same capacity and fullness requirements as buffer 46 at the transmitter end. When writing to the buffer 84 is briefly disabled to remove overhead information (e.g., field sync) from the data stream, data packets continue to be read to the transport processor at a constant uniform rate. During this time, buffer 84 is not completely empty. The constant uniform gap between data packets allows sufficient time for the buffer 84 to partially empty while writing is briefly disabled to remove overhead information from the data stream. After the overhead information is removed during the write inhibit interval, the data is again written to the buffer 84. At all these times, transport processor 86 continuously receives data packets from buffer 84, whereby the data stream flows uninterrupted while transport processor 86 processes the data packets uninterrupted.
The waveforms shown in fig. 18-27 pertain to the receiver operating conditions. Clock synchronization at the receiver end is achieved using the packet synchronization byte, which, as explained above, is the first byte of each data packet. As in the case of the transmitter, the symbol clock SC (fig. 18) and the 1/4SC clocks (fig. 19) synchronized with each other are generated after the sync byte at the start of the packet is detected (fig. 21). Also as in the transmitter, a counter is used to count 1/4SC clock cycles to generate the 3/8SC clock for the receiver (fig. 20). The counter is synchronously reset to zero for each packet sync byte. The results previously obtained for the structure and characteristics of the transmitter side 3/8SC symbol clock are equally applicable to the receiver side 3/8SC clock. The 1/4SC clock and the 3/8SC clock should be the same at the transmitter and receiver.
Figure 22 shows the output data valid timing signal generated by unit 82 of network 75 occurring simultaneously with the data signal from processor 75. The waveform of the data valid signal conforms to the waveform of the data signal from the processor 75. The data valid timing signal exhibits non-uniform characteristics with non-uniform inter-packet gaps including a gap of 20 (clock) counts corresponding to FEC data inserted in the data signal and a much wider gap of 228 counts corresponding to field sync inserted in the data signal. Data packets in the digital signal occur during the forward 188 count intervals of the data valid signal. Thus, the data signals from the network 82 exhibit a non-uniform data flow with respect to the packet data. Waveforms at the transmitter end relative to the data valid signal of fig. 22 are shown in fig. 3 and 10.
In contrast, the data valid signal (fig. 23) provided from the buffer network 84 to the transport processor/decoder 86 exhibits a uniform structure with uniform inter-packet gaps. This signal indicates that the data stream of MPEG byte data from buffer network 84 consists of constant uniform inter-packet intervals (3/8SC clock 125 count "data disable" intervals) between each constant uniform data packet (3/8SC clock 188 count "data enable" intervals). In this way, the data stream of MPEG byte data exhibits a constant uniform data flow, so that transport processor 86 is susceptible to uninterrupted operation. In accordance with the data valid signal of fig. 23, transport processor 86 obtains data packets to be processed during each 188 count clock intervals on an uninterrupted data flow basis. The portion of the data valid signal opposite the transmitter of fig. 23 is shown in fig. 11 and 12.
The receiver's buffer/interface network 84 operates in a similar manner to the transmitter network portion shown in fig. 28. As previously indicated, the respective FIFO buffers are different for read and write clock inputs. In addition, the transmitter system controller 44 of fig. 28 provides a packet request signal to the transport in response to a data field packet request, and the corresponding receiver network of fig. 29 sends an SOP flag to the receiver transport processor 86 to indicate the start of a new packet. As is the case with the corresponding buffer 46 at the transmitter end, the receiver buffer 100 in fig. 29 is cleared and refilled to a predetermined level each time the receiver is reset. The buffer 100 must reach a predetermined "fullness" level before the data is allowed to be read out. This operation is illustrated in fig. 24-27 and is similar to that previously discussed with respect to fig. 13-16 with respect to the transmitter.
The controller 120 generates a self-oscillating internal timing waveform, shown in dashed line form in fig. 24. The signal exhibits a constant uniform structure. Specifically, the signal consists of a constant uniform interval of 125 counts of 3/8SC clock (corresponding to a data disable interval between packets) between a constant uniform interval of 188 counts of 3/8SC clock (corresponding to a data packet data enable interval). From this signal, the controller 120 generates a FIFO read enable signal (FIG. 25) to the buffer 100 and a data valid signal (FIG. 27) to the transport processor 86, both of which have a constant uniform structure. These signals are generated based on the buffer fullness signal (fig. 26) and the SOP flag input to register 110. The SOP flag is a buffered and delayed replica of the packet start signal. The SOP output (register delayed) of register 110 is applied to a control input of unit 120 and to transport processor 86. The buffer fullness signal is generated when the buffer 100 exhibits a predetermined fullness. The operation of the buffer read enable begins at the leading edge of the first (positive going) data enable interval that occurs after the fullness signal goes high based on the buffer fullness condition being satisfied. Thus, at time T2, the first (sync) byte of the data packet is aligned with the beginning of the valid data interval (fig. 27) of the data valid signal.
The Read Clock (RCK) inputs of flip-flops and buffers 84 are all clocked by unit 122 according to the SC and 1/4SC clocks by the locally generated 3/8SC clock as previously discussed. 3/8 the SC clock is also applied to the controller 120. When flip-flops 110 and 112 are controlled to be enabled by a read enable signal generated by controller 120, the MPEG byte data is passed through these flip-flops to the data input of transport processor 86. At the same time, the SOP identification is passed to the transport processor 86 along with a data valid signal (fig. 27) from the controller 120. The data valid signal is provided to the transport processor 86 so that it can obtain data during the interval when valid packet data is present.
The interface between the transport processor and the transport processor, including the network 17, is important in many applications. For example in television broadcasting, the transmission processor will be required to generate and output a data field without interruption once transmission has begun. Television receivers rely on such uninterrupted data streams of data fields including field sync segments to maintain synchronization. Any variation in the data field rate or structure during the broadcast will cause the receiver to lose synchronization. Television broadcasters typically pre-program combinations of multiple video tape players to automatically switch to the appropriate source material in a timed manner. These tape players output transport packets containing transport stream information. Each tape player synchronizes its output with the data stream being fed to the transport processor, which is not allowed to change its field rate or field structure. The non-uniform gaps in the packet stream sent from the transport processor to the transport processor have the effect that the transport data field structure becomes an artifact in the data stream at the interface, which will have both packet and data field structures. Each broadcaster video recorder would undesirably require a complex interface that would synchronize the video tape output to both packet boundaries and field boundaries. Additional information about the field structure may be required to be derived through the interface or by monitoring the data stream at the interface. The video tape interface will contain a means for packet sync detection, a means for field detection and sufficient memory to buffer the data field structure. Additional complexity is introduced by the pre-recorded tape and the insertion of local programs and advertisements. These complexities and other difficulties can be successfully addressed by a recording/playback device utilizing the principles of the present invention as shown in fig. 33 and 34.
Fig. 33 and 34 show the transmitter and receiver systems of fig. 4 and 17, respectively, with the difference that the systems of fig. 33 and 34 include a video recording device. In fig. 33, the video tape recording/playback device 15 receives a data stream of uniform data rate from the transport processor 14 and provides playback data of uniform rate for delivery to the encoder and data field construction network 17 via the buffer/interface 16. As in the case of the system of fig. 4, the system of fig. 33 presents a uniform data flow at the interface between the transport layer and the transport layer. In this example, the data source 12 includes a broadcast station camera and an MPEG encoder for encoding the camera output signal prior to packetization by the transport processor 14.
The video recorder 15 may be a commercial device for recording bytes to bytes on tape, such as a Song D3 tape recorder. In some video recorder designs, the interface 16 may be included in the video recording device itself. The video recorder 15 may become one of several video recorder combinations as said commonly used at broadcast stations to facilitate the delivery of different types of program material by the broadcast stations.
In fig. 34, the video tape recording/playback device 85 receives and processes the uniform data rate data stream (with overhead information removed) from the interface/buffer 84 and provides the uniform rate playback data to the transport processor/decoder 86. The system of fig. 34 also presents a uniform data flow at the interface between the transport layer and the transport layer. In this system, video recorder 85 represents a consumer device (VCR) capable of recording images from a broadcast, or for playing back material prerecorded by a device having the characteristics of unit 15 of fig. 33. Unit 85 may be a separate unit in the system and components 72, 75, 84 and 86 may be included in the television receiver. Alternatively, the components 72, 75, 84, and 86 may also be included in the video recorder 85.