2309825 SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a metal oxide semiconductor (11MOS11) transistor formed on a silicon-oninsulator (11SOIll) wafer that prevents substrate floating effect and a method of fabricating the same. - - In general, SOI wafer has advantages of preventing RC delay due to a parasitic capacitance and leakage current of semiconductor devices and so it is provided as substrate for low powered high speed semiconductor devices.
There are two methods for the fabrication of the SO: wafer, a separation by implanted oxygen (11SIMOX11) method and a bonding method. The SIMOX method implants oxygen ons within a Si substrate to form SOI wafer. The bonding method bonds the device substrate on which an insulator is formed to the handling substrate, and thinly grinds the device substraze to form the SOI wafer.
As shown in FIG.1, there is Drovided a SOI substrate 100 comprising a handing substrate 1, an insulation film 2 and a Si layer 3 on which a MOS transistor is to be formed.
Herein, the Si 'layer 3 is doped with impurity ions of a first conductivity type and is formed to a thickness of 300-1500 in order to prevent punchthrough and short channel effect of a MOS transistor which formed on the Si 1 layer 3. A field oxide 4 is formed at the -predetermined zortion of the Si layer 3 by a conventional LOCOS method to define an active region. As the bottom of the field oxide 4 is in contact with the insulation film 2, the active region where the MOS transistor is formed is completely isolated.
Next, a gate oxide 5 and a polysilicon layer are formed ovir the SOI wafer 100 and then zatterned to form a gate electrode 6. impurity ions of a second conductivity type are implanted into the Si layer 3 to form source/drain regions 7 between the gate electrode 6 and the field oxide 4. Herein, as the bottoms of source/drain regions 6 are in contact with the insulation film 2, junction capacitance and leakage current does not occur. An intermediate insulation layer 8 is then deposited over the resultant structure at the predetermined thickness and then etched to expose the source/drain regions 7. Next, a metal interconnection -9 is formed to be contacted with the exposed source/drain regions 7.
However, in case where the Si layer where a MOS transistor is formed has a thin thickness, when a channel region is completely depleted, -,..he potential of the channel region in the MOS transistor of FIG.1 is higher than that of a conventional MOS transistor. Also, the potential barrier between source/drain regions and a channel region becomes low and holes which are generated by impact ions in depletion region of the drain region are temporarily 2 accumulated in the channel region-. The accumulated holes increase the height of the potential in the channel region. Therefore electrons from source region are rapidly injected into the channel region, resulting in substrate floatin.g effect wherein an endurance voltage between source/drain regions lowers easily.
SMWY Oi THE INVENTION An object of the present invention is to provide a semiconductor and a method of fabricating the same, wherein a body electrode region is formed to prevent floating generated in a 501 wafer without a reduction in degree of integration.
In accordance with one embodiment, there is provided a semiconductor device, comprising: a SOI substrate Jncluding a Si substrate, an insulation film and a Si layer having a first conductivity type formed on the Si substrate, and conduction layer formed between the Si layer and the insulation film; a field oxide formed in the Si layer to define the Si layer to a first active region and a second active region; a gate electrode formed on the Si layer of the first active region; source/drain regions having a second conductivity type formed in the Si layer at the both sides of the gate electrode; and a body electrode region having a predetermined conductivity type formed in the Si layer of the second active region and contacted with 3 the Si layer through the conduction layer.
In addition, there is also provided a method of fabricating a Sol substrate, comprising the steps: providing a handling substrate where a first oxide film is 5 formed; providing a device substrate where a field oxide is formed to define a first active region and a second active region; forming a first insulation film over the device substrate: to expose a predetermined portion of the device substrate in the first active region and a predetermined portion of the device substrate in the second act:Lve region; forming a conduction layer having a predetermined conductivity type over the first insulat-Lon film to be contac-ed with the exposed portions of the device substrate n the first and second active regions; forming a second 15 oxide film on the conduction layer; contacting surfaces of the first cx-Jde film of the handling substrate and the second oxide of the device substrate to bond the device substrate and the handling substrate; etching the device substrate to form a Si layer, thereby forming the silicon20 on-insulator including the handling substrate, the Si layer, and a second insulation film including the first oxide film and the second oxide film between the handling substrate and the Si layer; doping the Si layer with a.lirst conduc-Jvity type impurity ions; f=ming a gate electrode over the exposed portion of the device substrate which is contacted with the conduction layer in the first active region; and implanting impurity ions of a second 4 conductivity type into the Si layer to form source/drain regions at both sides of the gate electrode in the first active region and to &form a body electrode region in the second active region, the sou.-ce/d--ain regions being isolated with the conduction layer by the first insulation film and the body electrode region being contacted with the Si layer between source/drain regions through the conduction layer.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects and feature of the invention may be better understood with reference to the following detailed description, appended claims, and attached drawings wherein:
FIG.1 is a sectional view of a MOS transistor which is tormed on the S01 wafer in the prior art;
FIG.2 is a sectional view of a MOS transistor which is formed on the SOI wafer in accordance with an embodiment of the present invention; and F1G.3A through F1G.3D are sectional views illustrating a process of fabricating a M05 transistor on a S01 wafer in accordance with an embodiment of the mresent invention.
:S DETAILED DESCRIPTION OF TRE INVENTION
Referring to FIG.2, in accordance with an embodiment of. the present invention, there is provided a SOI wafer 200 comprising a Si handling substrate 10, an insulation -E-ilm 20 made of an oxide film formed on the Si handling substrate 10 and a Si layer 40 where a MOS transistor is to be formed. A field oxide 31 is formed at the predetermined portion of the Si layer 40 of the Si handling substrate 10 to define a first active region AA where a MOS transistor is to be formed and a second active region BB where a body electrode region is to be formed. Herein, the-Si layer where the first active region AA and the second active region BB are defined is doped with a first conductivity type impurity ions, such as N type impurity ions or P type impurity ions.
A aate oxide 41 and a gate electrode 42 are formed on the first active region AA in the Si layer. Source/drain regions 43A and 43B, having a second conductivity type, are formed at the both sides of the gate electrode 42 in the.-First active region AA and the body electrode region 43C is, having a second conductivity type, Js formed the second active region BB. At this time, if the Si layer has a N type, the source/drain regions 43A and 43B are a P type. on the other hand, if the Si layer is a P type, the source/drain regions are a N type.
A conduction layer 33 is formed between the Si layer 40 and the insulation film 20 to be isolated with the Si handling substrate 10 by the insulation film 20. In addition, the conduction layer 33 is isolated with the 6 source/drain regions 43A and 43B by an oxide 32 underlying the source/drain regions 43A and 43B. The conduction layer 33 is contacted with a channel region between the source/drain regions 43A. and 43B and the body electrode region 43C. Thus, the channel region is electrically contacted with the body electrode region through the conduction layer. Herein, the conduction layer has the same first conductivity type as the Si layer 40. The conduction layer 33 can be comprised one of silicmn layer, nolysilcon layer, amormhous silicon or silicide layer.
A method of fabricating the MOS transistor on a S01 wafer will be described in more detail with reference to FIG.3A to FIG.3D.
Referring to FIG.3A, there are provided a Si handling substrate 10 where an oxide film 20A is formed and a device substrate 30 having a predetermined conductivity type, such as a Si substrate or a GaAs substrate. A field oxide 31 is to be formed at the predetermined portion of the device substrate 30 by a conventional LOCOS process. With formation of zhe field oxide 31, a first active region AA where a MOS transistor is to be formed and a second active region BB where a body electrode region is to be formed are defined in the device substrate 30.
An oxide film 32 is formed over the surface of the :5 device substrate 30 including the field oxide 31. The oxide film 32 is formed at the predetermined thickness by a chemical vamor deposition (IICVDII) method and then etched
7 to expose the portions of the device substrate 30 where a channel region is to be formed in the first active region AA and where a body electrode region is to be f ormed in the second active region BB.
Next, a conduction layer 33 is formed over the device substrate 30 to be contacted with the exposed portions of the device substrate. Herein, the conduction layer 33 has the same conductivity type as the device substrate 30 and is preferably comprised one of a Si layer, pc71ysil-Jcon layer, amorphous silicon or silicide layer. An oxide film 20B serving as an buried insulation film of a SOI wafer is formed on the conduction layer 33 and then polished in order to mlanarize the device substrate 30.
As described above, in the mentioned embodiment, the oxide film 20A serving as an buried insulation film of a SOI wafer is formed on the handling substrate 10 and the conduction layer 33 and the oxide film 20B serving as an buried insulation film of a SOI wafer are formed on the device substrate 30. Alternatively, the oxide 'film 20A may be formed to serve as an buried insulation film of a SOI wafer on the device substrate 30, and the conduction layer 33 and the oxide film 20BO, may be formed to serve as an buried insulation film of a SOI wafer on the handling substrate 10.
Referring to FIG.3B, the device substrate 30 is put on the handling substrate 10 to be contacted with the surfaces of the oxide film 20A of the device substrate 30 and the 8 oxide film 20B of the handling substrate 10 and then bonded by a thermal treatment. The device substrate 30 bonded to the handing substrate 10 is etched to form a Si layer 40, thereby providing a SOI wafer 200. The device substrate 30 is etched by a etching back process or a chemical and mechanical polishing method until the surface of the field oxide 31 is exposed, to mlanarize the surface of the Si layer 40.
Referring to FIG.3C, impurity ions of -a first conductivity type, such as N type impurity ions or P type impurity ions are implanted into the Si layer 40, thereby doping L-he Si layer 40 with the first conductivity type impurity ions. Next, a gate oxide 41 is formed on the Si layer 40 to a thickness of 150-200A and a polysilicon layer is formed on the gate oxide 41 to a predetermined thickness and L-hen patterned to form a gate electrode 42 in the first active region AA.
Impurity ions of a second conductivity type are implanted into the Si layer 40 to form source/drain regions 43A and 43B at the both sides of the gate electrode 42 in the frist active region AA of the Si layer 40 and to form the body electrode region 43C in the second active reion BB of the Si layer 40, thereby fabricating the MOS transistor on the SOI substrate 200. Herein, although the body electrode region 43 has the same conductivity type as the source/drain regions, it may have a conductivity type opposite to the source/drain regions 43A and 43B.
9 Referring to FIG.3D, a metal interconnection process is carried out. Thus, an intermediate insulation layer 44 is formed over Si layer 40 where a MOS transistor is formed and then etched to expose the source/drain regions 43A and 43B and to expose the body electrode region 43C. Next, a metal layer is formed over the resultant and then etched to form metal interconnections 45 which are contacted with the source/drain regions 43A and 43B and with the body electrode region 43C.
In one embodiment, although the doped Si layer 40 is used for the conduction layer for connecting the channel region to the body electrode region 43C, it may use the doped material having a predetermined conductivity type, for example a polysilicon layer, amorphous Si layer, silicide layer as the conduction layer.
According to the present invention, in a MOS transistor formed on a SO1 wafer, a body electrode region for supplying a constant voltage to a substrate can be f=med regardless of degree of integration.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
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