2309823 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
BACKGROUND OF THE INVENTION
In on a SOI is The present invention relates to a semiconductor device, and more particularly to a metal oxide semiconductor ("MOS") transistor formed on a silicon-on insulator ("SOI") substrate and a method of fabricating the same.
general, since a MOS transistor which is formed substrate reduces junction capacitance, improves endurance voltage of an isolation film and prevents latch-up that a parasitic thyristor turns on is prevented as compared with a MOS transistor which is formed on a bulk Si substrate, it is excellent in the performance speed of a device and resistant-soft error of integration degree.
A conventional method of fabricating a MOS transistor on such SOI substrate is illustrated FIG.1A and FIG.1B. As shown in FIG.1A, a SCI wafer 100 where an insulation film 12 and a thin Si layer are formed on a Si base substrate 11 is prepared. Herein, the base substrate 11 wherein the insulation film 12 is formed is bonded to a Si substrate and then the Si substrate is ground to form a thin Si layer, thereby obtaining the SOI wafer. To forming the Si layer thinly is to improve a gate electric 1 field dominance in a channel region, control punchthrough, and form a device minutely. Preferably, the Si layer is formed to be 500-1500A in a thickness.
Then, a field oxide 14 for isolation is formed at the predetermined portion of the Si layer 13 and a gate oxide 15 and a polysilicon layer 16 are formed on the Si layer.
As shown in FIG.1B, the polysilicon layer 16 and the gate oxide 15 are patterned to form a gate electrode 16A. In order to form a lightly doped drain ("LDW), impurity ions of low concentration are implanted into an exposed Si layer 13 to form a low concentration impurity region 17. An insulation film is deposited over the resultant and then anisotropically blanket-etched to form sidewall spacers 18 at the both sides of the gate electrode 16A. Impurity ions of high concentration are implanted into an exposed Si layer using the gate electrode 16A and the sidewall spacers as a mask to form a high concentration impurity region 19, thereby forming a junction region 20 of a LDD structure.
However, according to the conventional method of fabricating a MOS transistor, since the Si layer is thinly formed, the depth of the junction region in the MOS transistor is shallow according to the thickness of the Si layer 13. The depth of the junction region 2 formed, however, is insufficient, resulting in the junction resistance of the junction region is increased.
SUMARY OF THE INVENTION
An object of the present invention is to provide a MOS transistor formed on a SOI substrate and a method of fabricating the same which can reduce the junction resistance of a junction region.
Another object of the present invention is to provide a MOS transistor formed on a SOI substrate and a method of fabricating the same which can improve the performance speed thereof.
In accordance with one embodiment, there is provided a semiconductor device comprising: a SOI wafer including a Si base substrate and an insulation film and a Si layer which are formed on said Si base substrate; an isolation film formed at the selected portion of said Si layer; a gate electrode formed on said Si layer; a conduction layer spaced apart from said gate electrode, said conduction layer formed over said Si layer and said insulation film; sidewall spacers formed over said Si layer between said gate electrode and said conduction layer and at one side of said conduction layer over said isolation film; low concentration impurity regions formed at said Si layer below said sidewall spacers; and high 3 concentration impurity regions formed adjacent to said low concentration impurity regions at said Si layer below said conduction layer.
And, there is also provided a method of fabricating a semiconductor, comprising the steps of: providing a SOI substrate including a Si base substrate and an insulation film and a Si layer which are formed on said Si base substrate, said Si layer including an isolation film where is formed; forming conduction layers over said Si layer and said isolation film, said conduction layers spaced part from each other; forming a gate oxide film and a gate electrode on said Si layer between said conduction layers; forming low concentration impurity regions in said Si layer at both sides of said gate electrode; forming sidewall spacers over said Si layer between said gate electrode and said conduction layer and at one side of said conduction over said isolation film; and forming high concentration impurity regions in said conduction layers and said underlying Si layer adjacent to each low concentration impurity region.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects and feature of the invention may be 25 better understood with reference to the following detailed description, appended claims, and attached 4 drawings wherein:
FIG.1A and FIG.1B are sectional views illustrating a process of fabricating a MOS transistor on a SOI substrate according to the prior art; and
FIG.2A through FIG.2E are sectional views illustrating a process of fabricating a MOS transistor on a SOI substrate in accordance with one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG.2A, in accordance with one embodiment of the present invention, there is provided a SOI wafer 200 comprising a Si base substrate 21, an insulating film 22 and a Si layer 23 which are formed on the Si base substrate 21. A field oxide 24 for isolation between devices is formed at a predetermined portion of the Si layer 23 by a conventional selective oxidation method, and a first poly silicon layer 25 is formed over 20 the SOI wafer 200 to a thickness of 2000-5000A by a chemical vapor deposition("CVD"). Referring to FIG.2B, the poly silicon layer 25 is patterned to be remained over only the portion of the Si layer where a high concentration impurity region is to formed is to be formed and the field oxide 24 adjacent to the portion, thereby forming a polysilicon pattern 25A. 5
Herein, the polysilicon pattern 25A is form in order to make sure of the sufficient junction depth which is to be formed hereinafter. A gate oxide 26 is uniformly deposited in a thickness of 50-200A over the exposed Si layer 23 existing in between the polysilicon pattern 25A, the polysilicon patterns 25A itself, and the field oxide 26. A second polysilicon 27 for a gate electrode is deposited in a thickness of 2000-4000A over the gate oxide 26.
Referring to FIG.2C, the second polysilicon layer 27 is patterned to form a gate electrode 27A to be positioned between the polysilicon patterns 25A. Subsequently, impurity ions, for example phosphorous(P) ions are implanted into the portion of the Si layer between the polysilicon pattern 25A and the gate electrode 27A at a low concentration of 1x101' - 1x10"' atoms /CM3 with energy of 50-100KeV, to form low concentration impurity regions 28.
insulation film for a spacer. for example TEOS oxide film, is uniformly deposited to a thickness of approximately 1000-2000A over the resultant structure and then anisotropically etched to form sidewall spacers 29 at the both sides of the gate electrode 27A and the polysilicon pattern 25A.
Next, impurity ions, for example arsenic(As) ions are implanted into the polysilicon pattern 25A and the Referring to FIG.2D, an 6 underlying Si layer 23 at high 1X1019 atoms / CM3 with energy of concentration of 1X1013 _ 80-150KeV, to form high concentration impurity regions 30, and thereby form a junction region 31 of a LDD structure. Herein, the junction region 31 comprises the low concentration impurity region 28 and the high concentration impurity region 30 which are f ormed in the Si layer 23 and the highly doped polysilicon pattern 25A.
Referring to the FIG.2E, in order to increase the conductivity of the polysil-icon pattern 25A and the gate electrode 27A, a metal silicide 32 is selectively deposited only on the gate electrode 27A and the polysilicon pattern 25A by a selective deposition method. For use as the metal silicide, titanium silicide, tungsten silicide, tantalum silicide, or molybdenum silicide, are available, and any one of which can be used.
According to the MOS transistor formed on the SOI substrate of this invention, the shallow junction region is formed as well as the sufficient junction depth is ensured, thereby reducing the junction resistance.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense.
Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be 7 1 apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
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