METHOD FOR STORING REPAIR DATA IN A MICRO PROCESSORSYIEMField of the InventionThe invention relates to a method for storing first data for the replacement of second data in a micro processor system as well as to a micro processor system having cache memory means.
Background of the InventionMicro processors such as digital signal processors are usually controlled by program instructions which are sequentially inputted into the micro processor on a corresponding request. It is common practice to store a part of the program instructions in a read only memory. The read only memory is often integrated together with the micro processor on one single chip. This integration allows to shorten access times from the processor to the read only memory (ROM). It is also common practice to store another part of the program instructions in a random access memory (RAM). The RAM can also be integrated on the same integrated circuit chip as the processor or it can be an external memory which is implemented on a separate chip.
The access to the external memory is often implemented by means of a cache memory. Cache memories such as store in or write through memories are well known in the art and are widely used in order to reduce the bus traffic on external busses. Thereby access times to the external memory are reduced. On the internal and external memory devices program data such as program instructions or other kinds of data or a mixture of both can be stored according to the architecture of a particular micro processor system and the specific application for which it is used.
A problem encountered in the development of such a micro processor system is that data which is stored in the ROM of the system can not easily be changed or corrected. If a developer of the micro processor system finds faulty data or with other words a bug in the ROM there usually is no easy way to correct the bug. Exchanging the faulty data by the correct data in theROM requires the fabrication of a new mask for production of a new ROM which is expensive both in terms of production costs and development time.
One way to circumvent this problem is the usage of a so called jump table mechanism. This prior art method works as follows: If a certain program routine is suspected before ROM programming to include a bug then a jump command to an internal RAM is included in the routine. If later on afterROM programming it is found that the routine in fact contains a bug then the jump command is used to trigger the execution of a sequence of repair data, such as a subroutine.
The subroutine contains another jump command to jump back to the next program instruction in the ROM. The of the subroutine which is stored in theRAM for repair purposes is accomplished by means of the boot strap program.
The drawback of this jump table mechanism is that the developer has to guess where he might have a bug or where he might want to add a small enhancement. The developer should also choose between specifying a lot of jumps and having enough room in the RAM for the future code modifications. Usually he will compromise and eventually find a bug that he cannot correct so that the production of a new ROM mask is inevitable.
FIG. 1 shows a typical prior art micro processor system, in this case a digital signal processor system, in which usage of a jump table mechanism can be made. The system comprises an integrated circuit chip 1 which carries a digital signal processor (DSP) 2, an internal memory 3 and a cache 4. TheDSP 2 comprises an address decoder 5, access circuitry 6 and a cache controller 7. The cache controller 7 incorporates a cache directory 8. The address decoder 5 is connected with the access circuitry 6 via a communication channel 9, whereas the cache controller 7 is connected with the address decoder 5 via a communication channel 10.
The internal memory 3 comprises a ROM 11 and a RAM 12. Both the ROM 11 and the RAM 12 comprise a plurality of storage lines. The ROM 11 has the storage lines from the physical address 0 to a physical address R whereas theRAM 12 has storage lines from the physical address 0 to the physical addressQ. The same applies analogously for the cache 4 which has storage lines in the physical address range from 0 to P. The access circuitry 6 is coupled to the internal memory 3 via the communication channel 13 whereas the cache controller 7 is coupled to the cache 4 via the communication channel 14 and to the access circuitry 6 via the communication channel 19. The communication 14 is bi-directional for the transmittal of data from and to the cache 4.
Furthermore the micro processor system shown in FIG. 1 comprises an external memory 15 which is a random access memory. The external memory 15 is coupled to the access circuitry 6 via the communication channel 16 and to the cache 4 via the communication channel 17. The core of the DSP 2 is not shown in the drawing. An access request to data from the core of the DSP 2 is inputted into the address decoder 5 via the communication channel 18. Via the communication channel 18 the virtual address j of the data to be accessed is inputted into the address decoder 5.
This corresponds to step 20 in the flow chart shown in FIG. 2. In the step 21 the address decoder 5 decodes the virtual address j of the access request.
Subsequently by means of logical circuitry of the address decoder 5 it is decided whether the physical address belonging to the virtual address j is in the internal or in the external memory. If the storage location is situated in the internal memory 3 then either the ROM 11 or the RAM 12 is accessed via the communication channel 13 and the access circuitry 6. A corresponding signal is inputted into the access circuitry 6 via the communication channel 9. The access to the internal memory 3 is carried out in step 23.
If the storage location to be accessed is not situated in the internal memory 3 the cache controller is activated via the communication channel 10 by the address decoder 5. In step 24 the cache directory 8 is accessed to check whether there is a cache hit or a cache miss. If valid data having the virtual address j is stored in the cache 4, the cache 4 is accessed in step 26. This is decided in step 25 by means of logic circuitry of the cache controller.
If the data is not present in the cache 4 the external memory 15 is accessed in step 27. If the access request is due to a write request the write is executed to both the external memory location and to the cache memory in case of a cache hit. In case of a cache miss the write is executed only to the external memory location. A cache hit or miss is signaled to the access circuitry 6 via communication channel 19. Also the corresponding cache data are transmitted via the communication channel 19.
For the development of a processor system of the type shown in FIG. 1, a debugger program is normally used in order to find faulty data in the program instructions or in other kinds of data. Such a debugger program is often integrated into a micro program development software tool. Such a tool gives an environment to the developer which simplifies and speeds up the development of a program for the microprocessor system. If a bug has been found by means of the debugger program normally the above described jump table mechanism is used in order to correct the bug. Since this is not always possible it often happens that during the development of a micro processor system one or. two new ROMs 11 have to be fabricated to stepwise correct the faulty data.
It is therefore an object of the invention to provide an improved method for storing data for the replacement of other data in a micro processor system and to provide for an improved micro processor system. Furthermore the invention is aimed to provide an improved debugger program and an improved micro processor development tool.
Summarv of the InventionAccording to the present invention there is provided a method for storing first data for the replacement of second data in a micro processor system , said micro processor system comprising processor means, such as a digital signal processor, read only memory means, said second data being stored in said read only memory means, cache memory means adopted to be coupled to external memory means, said method comprising the steps of: logically assigning an address of said second data to said cache memory means, storing of first data in said cache memory means said first data being accessible via said address.
The invention further provides for a method for operating cache memory means, said cache memory means having first data stored therein according to the method of anyone of the preceding claims, said method for operating a cache memory means comprising a step of checking the cache memory means for a hit or a miss on an access request irrespective of the access request being directed on data belonging to an internal or external address space.
Furthermore the invention provides for a micro processor system comprising micro processor means, such as a digital signal processor, read only memory means, cache memory means adopted to be coupled to external memory means, means for logically assigning an internal address to said cache memory means, and means for checking the cache memory means for a hit or a miss on an access request irrespective of the access request being directed on data belonging to an internal or external address space.
The invention as claimed allows to change the data in a micro processor, such as code modifications, without a need to generate a new ROM mask.
For the development of a micro processor system this results in a much shorter turn around time, especially when bugs are discovered or when small enhancements are required in the program code.
In contrast to the prior art jump table mechanism the developer has complete freedom to modify data or program code or both. This is particularly beneficial when the need for modification arises after fabrication of the ROM.
The only limit for the implementation of modifications is the size of the cache memory and the size of the available RAM in the system. Also the cache of the microprocessor system can be used as such RAM for the purposes of the inventions.
The modification of data stored in the ROM can be accomplished irrespective of the nature of the data. For example, the data can be program data, such as program code or non executable data, such as coefficients for a digital signal processing algorithm or image data.
According to a first embodiment of the invention the data which is to replace the data in the ROM is stored in the cache memory of the processor system on the same virtual address as the data to be replaced. In the case of program data the program counter will increase after the replacement data in the cache has been accessed so that the next program command stored in theROM next to the replaced command will be accessed and executed.
The replacement data can comprise a jump command. If the jump command is stored in the cache memory on the virtual address of the data to be replaced this gives the developer complete freedom to store a sequence of further replacement data anywhere in the RAM or cache memory of the processor system: by means of the jump command which replaces the original command stored in the ROM the program control jumps to a sequence of replacement instructions stored somewhere in the RAM or cache memory of the system. The jump can be either to an internal or external address. At the end of the sequence of replacement data it is advantageous to store a further jump command to jump back to an address next to the original instruction in the ROM. This however will not always be required according to the nature of the modification the developer seeks to achieve.
It is particularly advantageous to integrate the method of the invention into a computer program, such as a debugger program. Debugger programs are widely used to find faulty data during the development of a micro processor system.
If faulty data are detected after the fabrication of the ROM of the processor system, the debugger program can carry out the method of the invention to correct the faulty data. The debugger program can be an integral part of a development tool which is used for the development of the micro processor system. Development tools for developing micro programs for processor systems such as digital signal processors are known as such in the art. The invention allows to correct faulty data stored in the ROM by means of the debugger program of the development tool.
According to a further preferred embodiment of the invention, the method for storage of replacement data is always carried out when the micro processor system is initialized by a boot strap program. The boot strap program carries out the steps of logically assigning the virtual address of the data to be replaced to the cache memory and storage of replacement data in the cache or the RAM of the micro processor system.
Furthermore the invention provides for a micro processor system which features an improved usage of the resources of its cache. In contrast to the prior art, the cache of the present system is also checked for a cache hit or a cache miss on an access request for data having a virtual address belonging to the internal memory. This allows the cache memory to be used for storage of replacement data. Another advantage is that such a microprocessor system can also be used stand alone without an additional external memory if the cache is used like an external memory.
It is advantageous to implement the micro processor system in one single integrated circuit chip in order to minimize the silicon space required. This however is not a prerequisite for carrying out the invention. Normally "internal data", such as an internal program, is the part of the data which reside in the chip, for example in the ROM or the RAM on the chip, while "external data", such as an external program, is the part of the data that resides in other memory chips, outside of the micro processor chip. It is also possible to use a memory extension bus that has the ability to extend the internal memory, ROM or RAM, by additional external memory chips likeFSRAMS or DRAMS.
Brief Description of the DrawingsThe invention will now be described by way of example and with reference to the accompanying drawings in which:FIG. 1 is a block diagram of a prior art micro processor system;FIG. 2 is a flow chart showing the operation of the prior art processor system of FIG. 1;FIG. 3 shows a block diagram of a first embodiment of the invention;FIG. 4 is a flow chart illustrating the initialization of the processor system ofFIG. 3;FIG. 5 is a flow chart illustrating the operation of the system of FIG. 3 after the initialization;FIG. 6 is a block diagram of a second embodiment of the invention;FIG. 7 is a flow chart illustrating the initialization of the processor system ofFIG. 6;FIG. 8 is a block diagram of a third embodiment of the invention;FIG. 9 is a flow chart illustrating the operation of the processor system ofFIG. 8.
Detailed Description of a Preferred EmbodimentIn FIG. 3 like reference numerals are used for parts of the processor system which correspond to parts of the prior art processor system of FIG. 1 having added "100" to the reference numerals.
The micro processor system shown in FIG. 3 comprises a chip 101 having a digital signal processor (DSP) 102, an internal memory 103 and a cache memory 104. The DSP 102 comprises an address decoder 105, access circuitry 106 and a cache controller 107. The cache controller 107 has a cache directory 108. The access circuitry 106 is coupled via the communication channel 109 to the address decoder 105 and the cache controller 107 is coupled via the communication channel 110 to the address decoder 105 and via the communication channel 119 to the access circuitry 106.
The internal memory 103 comprises a ROM 111 and a RAM 112. The internal memory 103 is coupled via the communication channel 113 to the access circuitry 106. The external memory 115 is coupled via the communication channel 116 to the access circuitry 106. The cache 104 is coupled to the cache controller 107 via the communication channel 114 and to the external memory 115 via the communication channel 117. The storage locations in the memories of the processor system of FIG. 3 will be referred to the same way as in the micro processor system of FIG. 1. Virtual addresses of data to be accessed are inputted into the address decoder 105 via the communication channel 118. In the example considered here the program instruction ADDX, Y is stored-on the physical address 2 of the ROM 111.
The virtual address of the program instruction ADD X, Y is j. During the development of the micro processor system it is found by means of a debugger program that the instruction ADD X, Y having the virtual address j is not correct and should be replaced by the instruction MPY X, Y. The step of detecting that faulty data having the virtual address j is stored in the ROM 111 is illustrated in step 401 of FIG. 4.
The replacement data MPY X, Y for the faulty data ADD X,Y is to be stored in the cache 104. Prior to the storage of the replacement data MPY X, Y in the cache memory the virtual address j of the faulty data has to be logically assigned to the cache memory 104.
In the preferred embodiment considered here this is accomplished by the so called PLOCK instruction. The PLOCK instruction is a cache specific instruction which is provided in the instruction set of the micro processor 102. This instruction permits the user to lock sectors of the cache 104. The instruction PLOCK as such is known from the prior art. In the prior art cache locking is used for locking some time-critical code parts in the cache memory. When a cache sector is locked, the sector replacement unit (SRU) can not replace this sector even if it becomes the least recently used sector or with other words the bottom of the least recently used stack.
A sector can be locked by the instructions PLOCK or PLOCKR. Their operand is a virtual memory address, absolute in the case of PLOCK or relative in the case of PLOCKR. The cache sector to which this address belongs, if there is such one, is locked. If the specified virtual address does not belong to one of the current cache sectors, a memory sector containing this address will be allocated into the cache, thereby replacing the least recently used cache sector. This cache sector will be locked but empty. If all cache sectors are already locked, this memory sector will not be allocated into the cache and the lock operation will not be executed. The locked cache sector becomes the most recently used (MRU).
Locking a cache sector does not affect the contents of the data stored in that cache sector, especially not the value of the valid bits of these data. A cache sector can be an individual storage location in the cache such as one of the storage lines 0,1,..i,i+1,..P of the cache 104 or it can be a group of such storage lines. In the latter case the cache is logically divided into a set of sectors, each of the sectors containing a plurality of neighboring storage lines.
In the preferred embodiment of the invention considered here the instructionPLOCK is used for another purpose as in the prior art.
The instruction PLOCK is used to logically assign the address j of the data to be replaced in the ROM, which in this case is ADD X, Y, to the cache memory 104.
This is accomplished by executing the command PLOCK j in step 402 as shown in FIG. 4. Subsequently the replacement data MPY X,Y is written on the virtual address j: The virtual address j which is one of the operands of the write instruction is inputted via the communication channel 118 into the address decoder 105. Even though the virtual address j belongs to an address space which corresponds to the internal memory 103 the cache controller 107 is activated via the communication channel 110. The cache controller 107 checks by means of its cache directory 108 whether there is a cache hit or a cache miss for the virtual address j. Due to the previous PLOCK instruction a cache hit is detected and signaled back via the communication channel 119 to the access circuitry 106.The cache controller 114 writes the replacement dataMPY X,Y via the communication channel 114 into the cache memory 104 on its physical address i. The physical address i of the cache 104 is logically assigned to the virtual address j which is stored in the cache directory 108 of the cache controller 107. Thereby the faulty instruction ADD X, Y is replaced by the write instruction MPY X, Y and thereby the bug is corrected. This is accomplished in step 403 of the flow chart shown in FIG. 4 where repair data in this case MPY X, Y is written into the locked sector of the cache 104.
In the following the operation of the system shown in FIG. 3 after the correction of the bug is explained in more detail with reference to FIG. 5. If the core of the digital signal processor (DSP) 2 wants to access the instruction stored on the virtual address j during the execution of a micro program a corresponding access request is issued and the virtual address j is inputted via the communication channel 118 into the address decoder 105. This is done in step 501. The virtual address j is decoded in the address decoder 105 in step 502. If the physical address belonging to the virtual address j does not belong to the internal memory 103 the sequence of steps 28 comprising steps 24, 25, 26 and 27 is carried out as it is the case in the prior art (cf. FIG. 2).
If the contrary is true, i.e. if the physical address corresponding to the virtual address j belongs to the internal memory 103, the directory 108 of the cache controller 107 is checked for a cache miss or a cache hit even though the address j belongs to an internal memory location. The decision whether the virtual address belongs to a physical address of the internal memory 103 or not is taken in step 503. The cache directory 108 is accessed in step 504.
In step 505 it is decided whether data having the virtual address j is stored in the cache 104 or with other words if there is a cache hit. If the answer is "yes" the cache 104is accessed in step 506 be it for a read or write request. If the answer is "no" a feedback signal is issued via the communication channel 119 to the access circuitry 106 so that the data being stored on the physical address which originally was assigned to the virtual address j is outputted from the internal memory 103 by means of the access circuitry 106 and the communication channel 113. The access circuitry 106 is triggered by a signal on the communication channel 109. The access to the internal memory location having the virtual address j is accomplished in step 507.
In the example considered here the situation is as follows: The virtual address j has been assigned to the cache 104 and the replacement data MPYX, Y has been stored on the physical address i. If the core of the DSP 102 issues an access request to the instruction which has the virtual address j it is decided in step 503 that the physical address belonging to the virtual address j is a storage location in the internal memory 103. Nevertheless the cache directory 108 is accessed in step 504 to check for a cache hit. In step 505 it is decided that there is a cache hit because of the previous PLOCK j. As a consequence not the internal memory 103 but the cache 104 is accessed in order to fetch the required program instruction having the virtual address j.
As a consequence not the original instruction ADD X, Y is outputted for input into the core of the DSP 102 but the replacement data MPY X, Y from the cache 104.
With reference to FIG. 6 and 7 a second embodiment of the invention will be described in the following. The hardware of the processor system shown inFIG. 6 is the same as the hardware shown in FIG. 3. However, the processor system is programmed differently. Again it is assumed that there is a faulty instruction ADD X, Y stored on the same storage location in the ROM 111.
The faulty instruction ADD X, Y is to be replaced by a sequence of instructions "instruction 1, instruction 2" which in this example consists of only two instructions but which in practice can consist of a much longer sequence of instructions.
The existence of the faulty instruction ADD X, Y is detected in step 701 whereupon a sector of the cache 104 is locked by the command PLOCK j in the step 702. The steps 701 and 702 correspond to the steps 401 and 402 of FIG. 4.
Instead of the replacement data MPY X, Y as in the first embodiment of the invention (cf. FIG. 3) a jump command is stored on the physical address i'of the cache 104. The operand of the jump instruction is a virtual address k. The virtual address k corresponds to the storage line of the RAM 112 having the physical address 2. The storage of the jump command is accomplished in step 703.
The sequence of replacement data - in this case instruction 1 and instruction 2 - is then written into the RAM 112 into the storage lines having the physical addresses 2 and 1. This is done in step 704.
At the end of the sequence of replacement instructions a further jump command is stored in step 705. By means of this jump command the control flow returns back to the next instruction stored in the ROM 111 next to the faulty instruction ADD X,Y. Hence the operand of the jump back command is the virtual address j+1. In the more general case when the sequence of replacement data has a length x the jump back command is stored on a virtual address k +x + 1 in the RAM 112.
When the core of the DSP 102 wants to access the instruction having the virtual address j not the original instruction ADD X, Y, but the instruction jump k is outputted from the cache 104 because of the cache hit. When the instruction jump k is carried out the control flow is directed to the instruction 1 which is the first instruction in the sequence of replacement data.
Subsequently the other replacement instructions - in this case only instruction 2 - is accessed by the core of the DSP. After the instructions of this sequence of replacement data have been carried out, the control flow returns back to the starting point by means of the instruction "jump back". The next instruction which is accessed by the DSP 102 is the instruction having the virtual address j + 1, i.e. the instruction which is next to the faulty instruction ADD X, Y in the ROM 111.
Instead of storing the sequence of replacement data in the RAM 112 of the internal memory 103 it is also possible to store the sequence of replacement data in any other RAM of the micro processor system. This can be a memory integrated on the chip 101, the external memory 115 or any other optional memory device. To accomplish this only the address k of the jump command stored in the cache 104 has to be changed correspondingly.
With reference to FIG. 8 and FIG. 9 the third embodiment of the invention will be described in the following. Again the hardware of the system remains unchanged with respect to the processor system shown in FIG. 3. Also the steps 901 and 902 of the flow chart of FIG. 9 correspond to the steps 401 and 402 of the flow chart shown in FIG. 4. Again a jump command is stored in the cache 104 in step 903 like in the step 703 of FIG. 7. However, in this case the virtual address of the jump command is the virtual address 1 which belongs to an external memory location. The problem is, that in fact no external memory 115 is present in the system so that the jump can not be executed to an external memory storage location.
In step 904 it is decided whether the virtual address 1 belongs to the same sector than the virtual address j. If this is not the case then the PLOCK command is executed again having the virtual address 1 as an operand in step 905. Subsequently in step 906 a sequence of replacement data is written into the cache 104 from the virtual address 1 to the virtual address 1 + y, where y = 2 in this case because the sequence only contains the instruction 1 and the instruction 2.
If the decision of step 904 is "yes" the step 906 is directly carried out since in this case there is no need for a PLOCK because the sector has already been locked by the PLOCK of step 902. In step 907 again a jump back command is stored on the virtual address l+y+1 in the cache 104 to jump back to the virtual address + 1 in the ROM 111.
If the core of the DSP 102 wants to access the virtual address j the instruction jump 1 is outputted from the cache 104 to the DSP 102 similar to the preferred embodiment of the invention shown in FIG. 6. However this time the virtual address 1 is not an internal address, but an external address. When the DSP 102 carries out the instruction jump 1 the cache controller 107 is accessed to check the cache directory 108 for a cache hit. Because of the previous PLOCK in step 902 and / or in step 905 there is a cache hit so that the sequence of instructions "instruction 1, instruction 2" stored in the cache 104 is outputted to the DSP 102.
The jump back command causes the control flow to return to the instruction stored on the virtual address j + 1 in the ROM 111. Hence, the preferred embodiment considered here allows to test and operate the micro processor system without an external memory 115.