SPECIFICATIONSemiconductor devicesThis invention relates to semiconductor devices.
It is an object of the present invention to provide a field-effect semiconductor device of a form suitable for incorporation in integrated circuits with a view to obtaining high packing density and/or radiation hardness.
According to one aspect of the present invention there is provided a field-effect semiconductor device including a channel region in the form of a layer of semiconductor material and two control electrodes respectively overlying and underlying said channel region layer and insulated therefrom by respective insulating layers.
Normally each said control electrode is provided with a respective lead.
It will be appreciated that a device in accordance with the invention is normally carried on an insuiating substrate.
According to a second aspect of the invention there is provided a method of fabrication of a device according to the invention comprising the steps of: forming a first layer of insulating material on a single crystal semiconductor wafer; forming a first strip of electrically conductive material on said first layer of insulating material; forming a second layer of in sulating material on said first layer of insulating material and overlying said first strip; forming an island of semiconductor material on said second layer of insulating material and positioned so as to bridge said first strip; forming a third layer of insulating material on said second layer of insulating material and overlying said island; forming a second strip of electrically conductive material on said third layer of insulating material and overlying said first strip; introducing impurities into regions of said islnd at either side of the second strip forming a fourth layer of insulating material on said third layer of insulating material and overlying said second strip; forming on the fourth layer of insulating material leads contacting said regions of the island and said first and second strips via windows in said third and fourth layers of insulating material.
One semiconductor device in accordance with the invention and its method of fabrication will now be described with reference to the accompanying drawings in which:Figures 1 to 5 are schematic sectional views illustrating various stages of the method; andFigure 6 is a plan view corresponding to the stage of Figure 5 which is the completed device.
Referring to Figure 1,the starting material is a single crystal silicon wafer 1.
After cleaning in conventional manner, the main face of the wafer 1 is provided with a layer 3 of silicon dioxide using a conventional thermal oxidation process. This layer serves as a substrate for the device which is a transistor device.
A layer 5 of polycrystalline silicon, hereinafter referred to as polysilicon, is then deposited on the oxide layer 3 and the polysilicon layer 5 is doped to render it electrically conductive. Using a photolithographic technique, the doped polysilicon is selectively etched to leave a strip 7 (see Figures 2 and 6) comprising a portion 7a, which is to become one of two gate electrodes in the completed device, and a portion 7b which constitutes a buried lead to the gate electrode portion 7a in the completed device.
A further thermally grown oxide layer 9 is then formed covering the strip 7, and a further polysilicon layer 11 is formed on the oxide layer 9.
Using, for example a focussed laser radiation technique the polysilicon layer 11 is then annealed to convert the layer 11 into crystalline form and thus render its electrical properties comparable with the single crystal wafer 1.
Using a photolithographic technique the layer 11 is then selectively etched to form a silicon island 13 which bridges the portion 7a of the strip 7 which is to become a gate electrode (see Figure 3).
Afurtherthermally grown oxide layer 15 of the same thickness as the layer 9 is then formed, covering the island 13, and an electrically conductive doped polysilicon layer 17 is formed on the oxide layer 15.
Using a photolithographictechniquethe layer 17 is selectively etched to leave a strip 19 (see Figures 4 and 6) which in the completed transistor constitutes the second gate electrode and a lead thereto. Thus the strip 19 comprises a gate electrode portion 19a which overlies the portion 7a of the strip 7 and a lead portion 19b which lies on the side on the portion 19a remote from portion 7b of strip 7.
To facilitate registration, the gate electrode portion 19a is of slightly smallerwidth than the gate electrode portion 7a.
With the strip 19 acting as a mask a suitable impurity is introduced into regions 21 and 23 of the silicon island 13 on either side of the portion 19a of strip 19 by an ion implantation technique, the regions 21 and 23 constituting the source and drain of the completed transistor. Alternatively, the impurity may be introduced by diffusion, via windows (not shown) formed through the oxide layer 15 on either side of the portion 19a of strip 19.
Finally, as shown in Figure 5, a further oxide layer 25 is formed on the structure by vapour deposition and aluminium leads 27, 29,31,33 contacting the source 21, drain 23 and two gate electrode leads 7b and 19b respectively via windows in the vapour deposited oxide layer 25, and where necessary oxide layer 15, are fabricated in conventional manner by photolithographic definition and etching of an aluminium layer deposited on the layer 25.
It will be understood that whilst the fabrication of a single device only on the substrate has been described, normally a large number of devices of various forms are simultaneously fabricated which together constitute an integrated circuit.
It will be appreciated that in operation of the device the source to drain current is controllable by both gate electrodes. By suitable choice of the potentials applied to the gates and/or the threshold voltages at which source to drain current starts to flow, the device can be arranged to perform an OR orNOR function or an AND or NAND function. A single device in accordance with the invention can thus perform functions which require two conventional transistors while occupying substantially the same substrate area as a single conventional transistor.
Thus the use of devices in accordance with the invention in an integrated circuit can significantly increase packing density.
in addition, increased flexibility in respect of interconnections between devices in a circuit using devices according to the invention may be expected due to the gate electrodes being constituted by electrically conducting layers at different levels separated by an intervening electrically insulating layer.
When intended for use in environments subjectto radiation, the lower gate of a device according to the invention, i.e. the gate 7a of the devices of Figures 1 to 6, may be used to compensate for changes in the device characteristics due to radiation. When subjected to radiation, source-to-drain leakage currents sometimes occur in transistors fabricated on insulating substrates due to the radiation causing positive charge trappings in the substrate adjacent the semiconductor/substrate interface. In a device according to the invention the lower gate may be biassed so as to compensate for, or drain away such radiation induced charge. By suitable design of its geometry the lower gate may also be arranged to eliminate radiation induced charges at the edges of the silicon island.Such induced charges can give riseto problems since they are likely to effect differently the electrical characteristics of a transistor fabricated on the island and any associated parasitic transistor.
It will be appreciated that a device in accordance with the invention may be either of the n-channel or p-channel type and either of the depletion or enhancement type. For adjustment of threshold voltage, appropriate impurity material may be introduced into selected regions of the silicon island 13 via a suitable mask immediately prior to the deposition of the polysilicon layer 17.
It will be understood that whilst the device described by way of example is fabricated on a silicon dioxide insulating substrate formed on a silicon wafer, other devices in accordance with the invention may be fabricated on other insulating substrates, for example, a sapphire substrate.