GB201310002D0 - Method,system and program for cache coherency control - Google Patents

Method,system and program for cache coherency control

Info

Publication number: GB201310002D0
Authority: GB; United Kingdom
Prior art keywords: program; cache coherency; coherency control; control; cache
Prior art date: 2010-11-26
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

International Business Machines Corp

Original Assignee

International Business Machines Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2010-11-26

Filing date

2011-09-05

Publication date

2013-07-17

2011-09-05Application filed by International Business Machines CorpfiledCriticalInternational Business Machines Corp

2013-07-17Publication of GB201310002D0publicationCriticalpatent/GB201310002D0/en

2013-08-07Publication of GB2499168ApublicationCriticalpatent/GB2499168A/en

2014-04-16Application grantedgrantedCritical

2014-04-16Publication of GB2499168BpublicationCriticalpatent/GB2499168B/en

StatusActivelegal-statusCriticalCurrent

2031-09-05Anticipated expirationlegal-statusCritical

Classifications

- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Memory System Of A Hierarchy Structure (AREA)

GB1310002.9A2010-11-262011-09-05Cache coherency control method, system, and programActiveGB2499168B (en)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP2010263714		2010-11-26
PCT/JP2011/070116WO2012070291A1 (en)	2010-11-26	2011-09-05	Method, system, and program for cache coherency control

Publications (3)

Publication Number	Publication Date
GB201310002D0true GB201310002D0 (en)	2013-07-17
GB2499168A GB2499168A (en)	2013-08-07
GB2499168B GB2499168B (en)	2014-04-16

Family

ID=46145651

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
GB1310002.9AActiveGB2499168B (en)	2010-11-26	2011-09-05	Cache coherency control method, system, and program

Country Status (6)

Country	Link
JP (1)	JP5414912B2 (en)
CN (1)	CN103229152B (en)
DE (1)	DE112011103433B4 (en)
GB (1)	GB2499168B (en)
TW (1)	TW201234180A (en)
WO (1)	WO2012070291A1 (en)

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JP6303632B2 (en)*	2014-03-10	2018-04-04	富士通株式会社	Arithmetic processing device and control method of arithmetic processing device
US9785554B2 (en)*	2014-05-30	2017-10-10	International Business Machines Corporation	Synchronizing updates of page table status indicators in a multiprocessing environment
US9514058B2 (en)*	2014-12-22	2016-12-06	Texas Instruments Incorporated	Local page translation and permissions storage for the page window in program memory controller
CN104750561B (en)*	2015-04-15	2019-09-10	苏州中晟宏芯信息科技有限公司	Dynamic release method, system and a kind of processor of register file cache resources
GB2539383B (en)*	2015-06-01	2017-08-16	Advanced Risc Mach Ltd	Cache coherency
CN106326146B (en)*	2015-06-29	2019-05-14	上海华虹集成电路有限责任公司	Check the method whether cache hits
US10262721B2 (en)*	2016-03-10	2019-04-16	Micron Technology, Inc.	Apparatuses and methods for cache invalidate
US10503641B2 (en)*	2016-05-31	2019-12-10	Advanced Micro Devices, Inc.	Cache coherence for processing in memory
JP6235088B2 (en)*	2016-08-24	2017-11-22	ルネサスエレクトロニクス株式会社	Information processing device
CN108536473B (en)*	2017-03-03	2021-02-23	华为技术有限公司	Method and apparatus for reading data
TWI622881B (en)*	2017-04-25	2018-05-01	Chunghwa Telecom Co Ltd	Cache replacement system and method thereof for memory computing cluster
KR20190009580A (en)*	2017-07-19	2019-01-29	에스케이하이닉스 주식회사	Controller and operation method thereof
GB2570474B (en)*	2018-01-26	2020-04-15	Advanced Risc Mach Ltd	Region fusing
CN112612726B (en)*	2020-12-08	2022-09-27	海光信息技术股份有限公司	Data storage method, device, processing chip and server based on cache coherence
CN113779649B (en)*	2021-09-08	2023-07-14	中国科学院上海高等研究院	A Defense Method Against Speculative Execution Attacks
KR102571197B1 (en)	2022-12-07	2023-08-30	성균관대학교산학협력단	Method for maintaining cache coherency of cluster file system
TWI853567B (en)*	2023-05-11	2024-08-21	台達電子工業股份有限公司	Distributed data backup, restore and synchronization method for multiple devices, electronic device, and data management system

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JPH083805B2 (en)*	1985-06-28	1996-01-17	ヒューレット・パッカード・カンパニー	TLB control method
JPH0736170B2 (en)*	1991-04-03	1995-04-19	工業技術院長	Multiprocessor system
US5437017A (en)*	1992-10-09	1995-07-25	International Business Machines Corporation	Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system
CA2107056C (en)*	1993-01-08	1998-06-23	James Allan Kahle	Method and system for increased system memory concurrency in a multiprocessor computer system
JP3713312B2 (en)*	1994-09-09	2005-11-09	株式会社ルネサステクノロジ	Data processing device
JP2000067009A (en)*	1998-08-20	2000-03-03	Hitachi Ltd	Shared memory multiprocessor
US6553460B1 (en)*	1999-10-01	2003-04-22	Hitachi, Ltd.	Microprocessor having improved memory management unit and cache memory
US6829683B1 (en)*	2000-07-20	2004-12-07	Silicon Graphics, Inc.	System and method for transferring ownership of data in a distributed shared memory system
US6633967B1 (en)*	2000-08-31	2003-10-14	Hewlett-Packard Development Company, L.P.	Coherent translation look-aside buffer
US6854046B1 (en)*	2001-08-03	2005-02-08	Tensilica, Inc.	Configurable memory management unit
US7082500B2 (en)*	2003-02-18	2006-07-25	Cray, Inc.	Optimized high bandwidth cache coherence mechanism
US7073043B2 (en)*	2003-04-28	2006-07-04	International Business Machines Corporation	Multiprocessor system supporting multiple outstanding TLBI operations per partition
US20080191920A1 (en)*	2007-02-12	2008-08-14	Sangbeom Park	Low-voltage drop reference generation circuit for A/D converter
US7809922B2 (en)*	2007-10-21	2010-10-05	International Business Machines Corporation	Translation lookaside buffer snooping within memory coherent system
US20100325374A1 (en)*	2009-06-17	2010-12-23	Sun Microsystems, Inc.	Dynamically configuring memory interleaving for locality and performance isolation

2011
- 2011-09-05DEDE112011103433.4Tpatent/DE112011103433B4/ennot_activeExpired - Fee Related
- 2011-09-05GBGB1310002.9Apatent/GB2499168B/enactiveActive
- 2011-09-05CNCN201180056650.2Apatent/CN103229152B/ennot_activeExpired - Fee Related
- 2011-09-05WOPCT/JP2011/070116patent/WO2012070291A1/enactiveApplication Filing
- 2011-09-05JPJP2012545639Apatent/JP5414912B2/ennot_activeExpired - Fee Related
- 2011-11-07TWTW100140540Apatent/TW201234180A/enunknown

Also Published As

Publication number	Publication date
DE112011103433B4 (en)	2019-10-31
WO2012070291A1 (en)	2012-05-31
JP5414912B2 (en)	2014-02-12
CN103229152A (en)	2013-07-31
GB2499168B (en)	2014-04-16
JPWO2012070291A1 (en)	2014-05-19
TW201234180A (en)	2012-08-16
DE112011103433T5 (en)	2013-07-25
CN103229152B (en)	2016-10-19
GB2499168A (en)	2013-08-07

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Legal Events

Date	Code	Title	Description
2014-06-11	746	Register noted 'licences of right' (sect. 46/1977)	Effective date:20140515

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