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GB1316205A - Electrical control system - Google Patents

Electrical control system

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Publication number
GB1316205A
GB1316205AGB1237271AGB1237271AGB1316205AGB 1316205 AGB1316205 AGB 1316205AGB 1237271 AGB1237271 AGB 1237271AGB 1237271 AGB1237271 AGB 1237271AGB 1316205 AGB1316205 AGB 1316205A
Authority
GB
United Kingdom
Prior art keywords
key
output
gate
logic
receptacle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1237271A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PHINIZY RB
Original Assignee
PHINIZY RB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PHINIZY RBfiledCriticalPHINIZY RB
Publication of GB1316205ApublicationCriticalpatent/GB1316205A/en
Expiredlegal-statusCriticalCurrent

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Abstract

1316205 Locks R B PHINIZY 30 April 1971 [6 May 1970] 12372/71 Heading E2A [Also in Division G4] An electrical control system includes means 10 for generating electrical signals representative of control actuating information, means 12 for generating electrical signals representative of control identification information which is associated with said means for generating electrical signals representative of control actuating information, a controlled device 14, means 13, 15 for voiding selected control identification information and responsive to the generation of the voided selected control identification information to provide an output inhibit control signal, sensing means 17 for sensing the control actuating information for a preselected actuating pattern of electrical signals and providing an output control signal in response thereto and gating means 16 responsive to said sensing means output control signal and said output inhibit control signal and connected to said controlled device, said gating means preventing the output control signal operating the controlled device when the output inhibit control signal is present. In the system shown in Figure 1, the means 17 also provides a second output signal if the signals from the means 10 are not representative of the control actuating information or in addition to signals representative of the control actuating information and this second output signal is also fed to the gating means 16 and inhibits operation of the controlled device 14, also when the second signal is produced by the means 17 and/or a signal is provided by the means 13, 15 an alarm is operated. The means 10 and 12 are combined and consist of a key receptacle and a key the key consisting of a carrier made of insulating material on one side of which is a pattern of conductive strips 'which provide the control actuating information and on the other side a pattern of strips which provide the identification information the receptacle having appropriate contacts for engaging the strips; the control actuating information includes a strip which when the key is inserted into the receptacle is connected to a voltage source and this voltage is applied to those of the other strips which are connected to it; one of such strips provides a signal to indicate that the key has been properly inserted into the receptacle. The remaining strips provide the control actuating information; and hence if a strip carrying a voltage is considered as providing a logic 1 signal then a strip not connected provides a logic 0 signal; thus the actuating information provided by the key is in the form of a binary code similarly the opposite side of the key has a strip connected to the voltage source when the key is in the receptacle and other strips which provide a binary code for identification information; as described both sets of information are in a binary coded decimal form. The means 17 consists of an AND gate 17a and an OR gate 17b; the inputs of the AND gate 17a are connected to those contacts of the receptacle which when a correct key is inserted in the receptacle engage those strips which provide control actuating logic 1 information, whereas the inputs of the OR gate 17b are connected to those contacts of the receptacle which engage the strips of the correct key which are not connected to the voltage source and hence provides control actuating logic 0 information; thus with a correct key in the receptacle the inputs of the AND gate 17a are all at logic 1 so that the gate produces a logic 1 output and the inputs of the OR gate 17b are all at logic 0 so that the output of the OR gate is at logic 0 and under these conditions and provided that no inhibit signal is received from the means 13, 15 the means 16 produces a logic 1 output to the controlled device 14 to operate it. With an incorrect key in the receptacle three conditions can ensure (1) neither of the gates 17a or 17b produce a logic 1 output (2) both gates produce a logic 1 output or (3) the output of gate 17a is at logic 0 and the output of gate 17b is at logic 1; none of these conditions can produce an output from the means 16 to operate the controlled device. A decoder 57 Fig. 5B is connected to the receptacle 22 Fig. 5A; since the identification information provided by the key 20 is in binary coded decimal form, each decimal decade is represented by four strips of the key and each group of four strips are connected to a unit of the decoder directly and via inverters 111 to enable the binary coded decimal information to be converted to decimal information so that a decimal signal for each decade appears on one of the ten output lines of each decoder unit; in Fig. 5B two units 57U and 57T are shown providing the decimal unit digit and the decimal ten digit. The means 13, 15, consists of a device 13 and a detector 15, the device 13 includes a patch panel having a plurality of sockets which can be connected by patch cords and each decoder unit has its outputs connected to ten sockets of the patch panel. The patch panel also has a number of groups of four sockets U, T, H, TH each group being connected to an individual logic element 120, 121 of the detector 15 and the outputs of each of the elements 120, 121 being connected to an OR gate 122 and via an amplifier 123 to the gating means 16. Each group of four sockets enables one key identification number or a group of such numbers to be voided; thus to void a single identification number the U socket of the group is connected by a patch cord to the appropriate units socket connected to the decoder unit 57U the T socket of the group is connected to the appropriate tens sockets which is connected to the decoder unit 57T and so on for the H and TH sockets of the group for the hundreds and thousands digits of a number; to void a group of ten numbers only the U and TH sockets are connected, to void a group of a hundred numbers only the H and TH sockets are connected and to void a group of a thousand numbers only the TH socket is connected to the appropriate decoder unit or units. Each logical element 120, 121 is a diode-resistor AND gate consisting of three diodes 121A, 121B, 121C and a resistor 120I as shown in Fig. 7; the AND gate is only energised when the TH socket is connected to the decoder unit 57TH so that if it is desire to void a number a patch cord must be connected from the TH socket of the group to one of the ten sockets connected to the decoder unit 57TH although this can of course be the decimal 0 socket; the H, T and U sockets of the group are connected to the diodes and any socket which is not connected leaves the appropriate diode floating so that it is effectively at logic 1, hence when the TH socket is energised by the decoder unit and any or all of the H, T or U sockets of the group are at logic 1 from the appropriate decoder units a logic 1 output is provided to the OR gate 122 which is amplified by the amplifier 123 and applied to the gating means 16 to inhibit operation of the controlled device 14. The circuit shown in Fig. 5 A and B is for controlling two doors Fig. 3 each door having a controlled device 14 and means 16 and 17 with the means 13, 15 common to the two doors. Associated with each door are two of the receptacles one for controlling entry and the other for controlling exit all of the contacts of the pair of receptacles for each door except one for each receptacle are connected in parallel; the ones which are not connected are for identifying the particular receptacle which is in use; means are provided so that when a key is in one of the receptacles of one door the insertion of a key in one of the receptacles of the other door is prevented from operating the various means; this is achieved by a pair of relays (not shown) and the key-in strip of the key since when the first key is inserted the relay connected to the keyin strip is operated to remove the voltage source from the receptacles of the other door. The contacts of the receptacle which provide key identification information are connected via OR gates 110 to the decoder units so that the receptacles of either door can operate the decoder units and to record the identification number of any key which is inserted into any receptacles a printer is used, respective printing wheels of the printer being connected to the respective decoder units; each wheel is rotatable by a stepping motor 80, or 81 and has ten segments, each segment being associated with a decimal digit, the segments being connected to the outputs of the appropriate decoder unit. There is also an arm 70b for engaging the segments in turn and which stops the wheel at the appropriate segment; when a key is inserted in any of the receptacles the voltage appearing on the key-in line is applied to an OR gate 103 and the logic 1 signal at its output is applied to one input of an AND gate 93 the other input of which is connected to an oscillator 90 which produces pulses for operating the stepping motors; hence the AND gate 93 produces a pulsed output which is applied via an inhibit gate 94 and an amplifier 95 to the stepping motor 80 or 81 which each steps its print wheel until the arm 70b reaches the segment of the print wheel which is at logic 1, when this happens the signal is applied via the arm 50b to the respective inhibit gate 94 and this prevents the pulses from the oscillator reaching the stepping motor so that the wheel stops in the appropriate position; the printer also has a wheel for indicating whether the key is good or bad and which of the four receptacles the key hae been inserted into; the wheel having eight indications for this purpose; its segments are connected to the outputs of a decoder which has four inputs connected to respective receptacles, an input connected via an amplifier 116 to the output of the detector 15 and the output of the OR gate 17b which thus provides the bad key information,
GB1237271A1970-05-061971-04-30Electrical control systemExpiredGB1316205A (en)

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
US3506170A1970-05-061970-05-06

Publications (1)

Publication NumberPublication Date
GB1316205Atrue GB1316205A (en)1973-05-09

Family

ID=21880389

Family Applications (1)

Application NumberTitlePriority DateFiling Date
GB1237271AExpiredGB1316205A (en)1970-05-061971-04-30Electrical control system

Country Status (7)

CountryLink
US (1)US3732542A (en)
CA (1)CA963121A (en)
CH (1)CH533224A (en)
DE (1)DE2122124A1 (en)
FR (1)FR2091277A5 (en)
GB (1)GB1316205A (en)
SE (1)SE7105829L (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US3838395A (en)*1972-12-041974-09-24Commplex IncElectronic variable combination lock and monitoring system
US3851314A (en)*1973-05-141974-11-26Eaton CorpElectronic identifying security system
US4044331A (en)*1973-07-161977-08-23International Business Machines CorporationData input apparatus having bidirectional reader for inputting alternative messages
US3860911A (en)*1973-11-011975-01-14Pitney Bowes IncElectronic combination lock and lock system
US3944976A (en)*1974-08-091976-03-16Rode FranceElectronic security apparatus
JPS533797A (en)*1976-06-301978-01-13Nippon Keibi Hosho KkSafety locking system
DE2824392C2 (en)*1978-06-031984-05-10Securiton AG, 3052 Zollikofen, Bern Maneuvering and testing equipment for at least one alarm loop in an alarm system
DE2911160A1 (en)*1979-03-221980-10-02Daimler Benz Ag DEVICE FOR PREVENTING UNAUTHORIZED STARTING OF VEHICLES
DE2928913C2 (en)*1979-07-181988-03-24Bayerische Motoren Werke AG, 8000 München Anti-theft device for motor vehicles
US4525713A (en)*1983-03-011985-06-25Lockheed Electronics Co., Inc.Electronic tag identification system
US4565922A (en)*1983-05-191986-01-21Rockwell International CorporationKey card apparatus
DE3326266A1 (en)*1983-07-211985-01-31Schulte-Schlagbaum Ag, 5620 Velbert ELECTRICALLY OPERABLE LOCKING DEVICE
FR2555641B1 (en)*1983-11-241989-11-03Lewiner Jacques IMPROVEMENTS TO ACCESS CONTROL DEVICES COMPRISING SEVERAL LOCKS
DE3819955A1 (en)*1988-06-111989-12-14Schulte Schlagbaum Ag LOCKING DEVICE WITH KEY-CODED PRINTER CONNECTION
US5359322A (en)*1992-09-281994-10-25Stanley Home AutomationMethod and apparatus for interconnected electronic locks

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US3184714A (en)*1963-04-151965-05-18Texas Instruments IncApparatus for use with a credit card
US3353006A (en)*1963-06-111967-11-14PollockMethod and device for destroying credit cards
US3500326A (en)*1965-08-171970-03-10Bowles BenfordMechanically programmed encoder system
GB1117728A (en)*1966-04-061968-06-26Tateisi Electronics CompanyAn entry or exit recording control apparatus
US3401830A (en)*1967-01-191968-09-17San Francisco Bay Area Rapid TVending machine for credit card purchasing
US3544769A (en)*1967-04-051970-12-01Digital Identification SystemsElectronic identification and credit card system
US3601805A (en)*1967-12-221971-08-24Res Systems CorpCredit card verifier apparatus
GB1285445A (en)*1968-08-301972-08-16Smiths Industries LtdImprovements in or relating to access-control equipment and item-dispensing systems including such equipment
US3648242A (en)*1968-10-231972-03-07Strategic Metals Research IncCard validating apparatus and method
US3564210A (en)*1968-11-291971-02-16Farrington Mfg CoApparatus combining a variable amount imprinter with credit verification circuitry

Also Published As

Publication numberPublication date
FR2091277A5 (en)1972-01-14
US3732542A (en)1973-05-08
CH533224A (en)1973-01-31
SE7105829L (en)1971-11-08
CA963121A (en)1975-02-18
DE2122124A1 (en)1971-11-18

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Legal Events

DateCodeTitleDescription
PSPatent sealed [section 19, patents act 1949]
PLNPPatent lapsed through nonpayment of renewal fees

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