FR3041471B1 - METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR - Google Patents

METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR Download PDF

Info

Publication number: FR3041471B1
Authority: FR; France
Prior art keywords: grid; transistor; forming spacers; spacers; forming
Prior art date: 2015-09-18
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

FR1558845A

Other languages

French (fr)

Other versions

FR3041471A1 (en

Inventor

Olivier POLLET

Nicolas Posseme

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

Original Assignee

Commissariat a lEnergie Atomique CEA

Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2015-09-18

Filing date

2015-09-18

Publication date

2018-07-27

2015-09-18Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEAfiledCriticalCommissariat a lEnergie Atomique CEA

2015-09-18Priority to FR1558845ApriorityCriticalpatent/FR3041471B1/en

2016-09-16Priority to EP16189263.3Aprioritypatent/EP3144973B1/en

2016-09-16Priority to US15/267,624prioritypatent/US10043890B2/en

2017-03-24Publication of FR3041471A1publicationCriticalpatent/FR3041471A1/en

2018-07-27Application grantedgrantedCritical

2018-07-27Publication of FR3041471B1publicationCriticalpatent/FR3041471B1/en

StatusExpired - Fee Relatedlegal-statusCriticalCurrent

2035-09-18Anticipated expirationlegal-statusCritical

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
- H10D30/6744—Monocrystalline silicon
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0147—Manufacturing their gate sidewall spacers
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0184—Manufacturing their gate sidewall spacers
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]

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Engineering & Computer Science (AREA)
Physics & Mathematics (AREA)
Computer Hardware Design (AREA)
Microelectronics & Electronic Packaging (AREA)
Power Engineering (AREA)
Condensed Matter Physics & Semiconductors (AREA)
General Physics & Mathematics (AREA)
Manufacturing & Machinery (AREA)
Chemical & Material Sciences (AREA)
High Energy & Nuclear Physics (AREA)
Chemical Kinetics & Catalysis (AREA)
General Chemical & Material Sciences (AREA)
Inorganic Chemistry (AREA)
Toxicology (AREA)
Health & Medical Sciences (AREA)
Plasma & Fusion (AREA)
Insulated Gate Type Field-Effect Transistor (AREA)

FR1558845A2015-09-182015-09-18 METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTORExpired - Fee RelatedFR3041471B1 (en)

Priority Applications (3)

Application Number	Priority Date	Filing Date	Title
FR1558845AFR3041471B1 (en)	2015-09-18	2015-09-18	METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR
EP16189263.3AEP3144973B1 (en)	2015-09-18	2016-09-16	Method for forming spacers of a transistor gate
US15/267,624US10043890B2 (en)	2015-09-18	2016-09-16	Method of forming spacers for a gate of a transistor

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
FR1558845AFR3041471B1 (en)	2015-09-18	2015-09-18	METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR
FR1558845		2015-09-18

Publications (2)

Publication Number	Publication Date
FR3041471A1 FR3041471A1 (en)	2017-03-24
FR3041471B1true FR3041471B1 (en)	2018-07-27

Family

ID=55178103

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
FR1558845AExpired - Fee RelatedFR3041471B1 (en)	2015-09-18	2015-09-18	METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR

Country Status (3)

Country	Link
US (1)	US10043890B2 (en)
EP (1)	EP3144973B1 (en)
FR (1)	FR3041471B1 (en)

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FR3051966B1 (en)	2016-05-27	2018-11-09	Commissariat A L'energie Atomique Et Aux Energies Alternatives	METHOD FOR FORMING A FUNCTIONALIZED GUIDING PATTERN FOR A GRAPHO-EPITAXY PROCESS
FR3051964B1 (en)	2016-05-27	2018-11-09	Commissariat A L'energie Atomique Et Aux Energies Alternatives	METHOD FOR FORMING A FUNCTIONALIZED GUIDING PATTERN FOR A GRAPHO-EPITAXY PROCESS
US10312102B2 (en)*	2016-08-29	2019-06-04	Tokyo Electron Limited	Method of quasi-atomic layer etching of silicon nitride
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KR102537097B1 (en)	2017-02-23	2023-05-25	도쿄엘렉트론가부시키가이샤	Pseudo-Atomic Layer Etching Method of Silicon Nitride
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FR3116379B1 (en)*	2020-11-18	2022-12-16	Commissariat Energie Atomique	Process for manufacturing a doped zone of a microelectronic device
FR3120158B1 (en)	2021-02-25	2023-04-14	Commissariat Energie Atomique	Process for forming the spacers of a gate of a transistor
FR3122525B1 (en)*	2021-04-28	2024-01-19	Commissariat Energie Atomique	Method for forming the spacers of a transistor gate
CN118077031A (en)*	2021-10-07	2024-05-24	谷歌有限责任公司	Hard mask stripping process

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2015
- 2015-09-18FRFR1558845Apatent/FR3041471B1/ennot_activeExpired - Fee Related
2016
- 2016-09-16EPEP16189263.3Apatent/EP3144973B1/enactiveActive
- 2016-09-16USUS15/267,624patent/US10043890B2/enactiveActive

Also Published As

Publication number	Publication date
EP3144973B1 (en)	2020-03-04
US10043890B2 (en)	2018-08-07
EP3144973A1 (en)	2017-03-22
FR3041471A1 (en)	2017-03-24
US20170084720A1 (en)	2017-03-23

Publication	Publication Date	Title
FR3023973B1 (en)	2016-08-05	METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR
FR3041471B1 (en)	2018-07-27	METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR
FR3013895B1 (en)	2017-04-14	METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR
FR3000601B1 (en)	2016-12-09	METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR
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Legal Events

Date	Code	Title	Description
2016-09-29	PLFP	Fee payment	Year of fee payment:2
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