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FR2704690B1 - Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions. - Google Patents

Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions.

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Publication number
FR2704690B1
FR2704690B1FR9304962AFR9304962AFR2704690B1FR 2704690 B1FR2704690 B1FR 2704690B1FR 9304962 AFR9304962 AFR 9304962AFR 9304962 AFR9304962 AFR 9304962AFR 2704690 B1FR2704690 B1FR 2704690B1
Authority
FR
France
Prior art keywords
chips
wafers
interconnection
dimensions
application
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9304962A
Other languages
French (fr)
Other versions
FR2704690A1 (en
Inventor
Val Christian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SAfiledCriticalThomson CSF SA
Priority to FR9304962ApriorityCriticalpatent/FR2704690B1/en
Priority to PCT/FR1994/000427prioritypatent/WO1994025987A1/en
Priority to JP6523941Aprioritypatent/JPH07509104A/en
Priority to EP94913654Aprioritypatent/EP0647357A1/en
Publication of FR2704690A1publicationCriticalpatent/FR2704690A1/en
Application grantedgrantedCritical
Publication of FR2704690B1publicationCriticalpatent/FR2704690B1/en
Anticipated expirationlegal-statusCritical
Expired - Fee Relatedlegal-statusCriticalCurrent

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Abstract

According to the method of the invention, conductive leads are directly wired onto a semiconductor wafer carrying a large number of chips, the wafer is bonded to a resilient film and cut to separate each chip, after which the film is stretched to space the chips; the totality of the chips and leads are then held in an insulating material such as a polymerizable resin, and, after polishing, metal plating is applied over the leads to connect them to the sides of the chips; the assembly is then cut in order to separate the chips.
FR9304962A1993-04-271993-04-27 Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions.Expired - Fee RelatedFR2704690B1 (en)

Priority Applications (4)

Application NumberPriority DateFiling DateTitle
FR9304962AFR2704690B1 (en)1993-04-271993-04-27 Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions.
PCT/FR1994/000427WO1994025987A1 (en)1993-04-271994-04-15Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection
JP6523941AJPH07509104A (en)1993-04-271994-04-15 Method for encapsulating semiconductor chips, device obtained by this method, and application to three-dimensional chip interconnection
EP94913654AEP0647357A1 (en)1993-04-271994-04-15Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
FR9304962AFR2704690B1 (en)1993-04-271993-04-27 Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions.

Publications (2)

Publication NumberPublication Date
FR2704690A1 FR2704690A1 (en)1994-11-04
FR2704690B1true FR2704690B1 (en)1995-06-23

Family

ID=9446488

Family Applications (1)

Application NumberTitlePriority DateFiling Date
FR9304962AExpired - Fee RelatedFR2704690B1 (en)1993-04-271993-04-27 Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions.

Country Status (4)

CountryLink
EP (1)EP0647357A1 (en)
JP (1)JPH07509104A (en)
FR (1)FR2704690B1 (en)
WO (1)WO1994025987A1 (en)

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US7829438B2 (en)2006-10-102010-11-09Tessera, Inc.Edge connect wafer level stacking
US7901989B2 (en)2006-10-102011-03-08Tessera, Inc.Reconstituted wafer level stacking
US7943952B2 (en)2006-07-312011-05-17Cree, Inc.Method of uniform phosphor chip coating and LED package fabricated using method
US8043895B2 (en)2007-08-092011-10-25Tessera, Inc.Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8167674B2 (en)2007-12-142012-05-01Cree, Inc.Phosphor distribution in LED lamps using centrifugal force
US8232564B2 (en)2007-01-222012-07-31Cree, Inc.Wafer level phosphor coating technique for warm light emitting diodes
US8337071B2 (en)2005-12-212012-12-25Cree, Inc.Lighting device
US8513789B2 (en)2006-10-102013-08-20Tessera, Inc.Edge connect wafer level stacking with leads extending along edges
US8637883B2 (en)2008-03-192014-01-28Cree, Inc.Low index spacer layer in LED devices
US8680662B2 (en)2008-06-162014-03-25Tessera, Inc.Wafer level edge stacking
US8878219B2 (en)2008-01-112014-11-04Cree, Inc.Flip-chip phosphor coating method and devices fabricated utilizing method
US8969908B2 (en)2006-04-042015-03-03Cree, Inc.Uniform emission LED package
US9024349B2 (en)2007-01-222015-05-05Cree, Inc.Wafer level phosphor coating method and devices fabricated utilizing method
US9041285B2 (en)2007-12-142015-05-26Cree, Inc.Phosphor distribution in LED lamps using centrifugal force
US9093616B2 (en)2003-09-182015-07-28Cree, Inc.Molded chip fabrication method and apparatus
US9159888B2 (en)2007-01-222015-10-13Cree, Inc.Wafer level phosphor coating method and devices fabricated utilizing method
US9166126B2 (en)2011-01-312015-10-20Cree, Inc.Conformally coated light emitting devices and methods for providing the same

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JP3065309B1 (en)1999-03-112000-07-17沖電気工業株式会社 Method for manufacturing semiconductor device
US7382142B2 (en)2000-05-232008-06-03Nanonexus, Inc.High density interconnect system having rapid fabrication cycle
US7247035B2 (en)2000-06-202007-07-24Nanonexus, Inc.Enhanced stress metal spring contactor
US6812718B1 (en)1999-05-272004-11-02Nanonexus, Inc.Massively parallel interface for electronic circuits
AU6001599A (en)*1999-10-012001-05-10Hitachi LimitedSemiconductor device and method of manufacture thereof
DE10023539B4 (en)*2000-05-132009-04-09Micronas Gmbh Method for producing a component
US7579848B2 (en)2000-05-232009-08-25Nanonexus, Inc.High density interconnect system for IC packages and interconnect assemblies
ATE311604T1 (en)*2000-06-202005-12-15Nanonexus Inc INTEGRATED CIRCUIT TEST SYSTEM
US20020100600A1 (en)*2001-01-262002-08-01Albert Douglas M.Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
DE10137184B4 (en)*2001-07-312007-09-06Infineon Technologies Ag Method for producing an electronic component with a plastic housing and electronic component
DE10149689A1 (en)2001-10-092003-04-10Philips Corp Intellectual PtyElectrical/electronic component has lateral, rear cover materials at least partly of electrically conductive material and/or of electrically conductive material in layers but in connected manner
KR100886292B1 (en)*2003-09-092009-03-04산요덴키가부시키가이샤Semiconductor module and semiconductor device including circuit components, manufacturing method and display device thereof
AU2003279044A1 (en)*2003-09-302005-05-11International Business Machines CorporationFlexible assembly of stacked chips
US20050104027A1 (en)*2003-10-172005-05-19Lazarev Pavel I.Three-dimensional integrated circuit with integrated heat sinks
US7215018B2 (en)2004-04-132007-05-08Vertical Circuits, Inc.Stacked die BGA or LGA component assembly
US7217583B2 (en)2004-09-212007-05-15Cree, Inc.Methods of coating semiconductor light emitting elements by evaporating solvent from a suspension
US7759166B2 (en)2006-10-172010-07-20Tessera, Inc.Microelectronic packages fabricated at the wafer level and methods therefor
US10295147B2 (en)2006-11-092019-05-21Cree, Inc.LED array and method for fabricating same
US7952195B2 (en)2006-12-282011-05-31Tessera, Inc.Stacked packages with bridging traces
US8723332B2 (en)2007-06-112014-05-13Invensas CorporationElectrically interconnected stacked die assemblies
US10505083B2 (en)2007-07-112019-12-10Cree, Inc.Coating method utilizing phosphor containment structure and devices fabricated using same
JP5572089B2 (en)2007-07-272014-08-13テッセラ，インコーポレイテッド Reconfigured wafer stack packaging with pad extension after application
US8551815B2 (en)2007-08-032013-10-08Tessera, Inc.Stack packages using reconstituted wafers
WO2009035849A2 (en)2007-09-102009-03-19Vertical Circuits, Inc.Semiconductor die mount by conformal die coating
CN101999167B (en)2008-03-122013-07-17伊文萨思公司Support mounted electrically interconnected die assembly
US9153517B2 (en)2008-05-202015-10-06Invensas CorporationElectrical connector between die pad and z-interconnect for stacked die assemblies
US7863159B2 (en)2008-06-192011-01-04Vertical Circuits, Inc.Semiconductor die separation method
WO2010026527A2 (en)2008-09-082010-03-11Koninklijke Philips Electronics N.V.Radiation detector with a stack of converter plates and interconnect layers
FR2940521B1 (en)2008-12-192011-11-113D Plus COLLECTIVE MANUFACTURING METHOD OF ELECTRONIC MODULES FOR SURFACE MOUNTING
WO2010104610A2 (en)2009-03-132010-09-16Tessera Technologies Hungary Kft.Stacked microelectronic assemblies having vias extending through bond pads
WO2010151578A2 (en)2009-06-262010-12-29Vertical Circuits, Inc.Electrical interconnect for die stacked in zig-zag configuration
WO2011056668A2 (en)2009-10-272011-05-12Vertical Circuits, Inc.Selective die electrical insulation additive process
TWI544604B (en)2009-11-042016-08-01英維瑟斯公司Stacked die assembly having reduced stress electrical interconnects
US10546846B2 (en)2010-07-232020-01-28Cree, Inc.Light transmission control for masking appearance of solid state light sources
US9490195B1 (en)2015-07-172016-11-08Invensas CorporationWafer-level flipped die stacks with leadframes or metal foil interconnects
US9871019B2 (en)2015-07-172018-01-16Invensas CorporationFlipped die stack assemblies with leadframe interconnects
US9825002B2 (en)2015-07-172017-11-21Invensas CorporationFlipped die stack
US9508691B1 (en)2015-12-162016-11-29Invensas CorporationFlipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en)2016-04-112020-02-18Invensas CorporationMicroelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en)2016-05-122017-03-14Invensas CorporationMicroelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en)2016-06-302017-08-08Invensas CorporationEnhanced density assembly having microelectronic packages mounted at substantial angle to board
US11654609B2 (en)*2016-12-012023-05-23Ecole Polytechnique Federale De Lausanne (Epfl)Engineering reversible elasticity in ductile or brittle thin films and products resulting from said engineering
JP6827676B2 (en)*2017-01-102021-02-10株式会社ディスコ Semiconductor device chip and manufacturing method of semiconductor device chip
US10615057B1 (en)2018-12-112020-04-07Northrop Grumman Systems CorporationEncapsulation process for semiconductor devices

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FR2645681B1 (en)*1989-04-071994-04-08Thomson Csf DEVICE FOR VERTICALLY INTERCONNECTING PADS OF INTEGRATED CIRCUITS AND ITS MANUFACTURING METHOD
WO1991000619A1 (en)*1989-06-301991-01-10Raychem CorporationFlying leads for integrated circuits
AU648417B2 (en)*1991-03-271994-04-21Integrated System Assemblies CorporationMultichip integrated circuit module and method of fabrication

Cited By (18)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US9105817B2 (en)2003-09-182015-08-11Cree, Inc.Molded chip fabrication method and apparatus
US9093616B2 (en)2003-09-182015-07-28Cree, Inc.Molded chip fabrication method and apparatus
US8337071B2 (en)2005-12-212012-12-25Cree, Inc.Lighting device
US8969908B2 (en)2006-04-042015-03-03Cree, Inc.Uniform emission LED package
US7943952B2 (en)2006-07-312011-05-17Cree, Inc.Method of uniform phosphor chip coating and LED package fabricated using method
US7901989B2 (en)2006-10-102011-03-08Tessera, Inc.Reconstituted wafer level stacking
US7829438B2 (en)2006-10-102010-11-09Tessera, Inc.Edge connect wafer level stacking
US8513789B2 (en)2006-10-102013-08-20Tessera, Inc.Edge connect wafer level stacking with leads extending along edges
US9024349B2 (en)2007-01-222015-05-05Cree, Inc.Wafer level phosphor coating method and devices fabricated utilizing method
US8232564B2 (en)2007-01-222012-07-31Cree, Inc.Wafer level phosphor coating technique for warm light emitting diodes
US9159888B2 (en)2007-01-222015-10-13Cree, Inc.Wafer level phosphor coating method and devices fabricated utilizing method
US8043895B2 (en)2007-08-092011-10-25Tessera, Inc.Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8167674B2 (en)2007-12-142012-05-01Cree, Inc.Phosphor distribution in LED lamps using centrifugal force
US9041285B2 (en)2007-12-142015-05-26Cree, Inc.Phosphor distribution in LED lamps using centrifugal force
US8878219B2 (en)2008-01-112014-11-04Cree, Inc.Flip-chip phosphor coating method and devices fabricated utilizing method
US8637883B2 (en)2008-03-192014-01-28Cree, Inc.Low index spacer layer in LED devices
US8680662B2 (en)2008-06-162014-03-25Tessera, Inc.Wafer level edge stacking
US9166126B2 (en)2011-01-312015-10-20Cree, Inc.Conformally coated light emitting devices and methods for providing the same

Also Published As

Publication numberPublication date
EP0647357A1 (en)1995-04-12
WO1994025987A1 (en)1994-11-10
FR2704690A1 (en)1994-11-04
JPH07509104A (en)1995-10-05

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